Add OUTPUT_PYTHON test-cases for all PDs.

[sigrok-test.git] / decoder / test / parallel / test.conf

diff --git a/decoder/test/parallel/test.conf b/decoder/test/parallel/test.conf
index e894ee2738d1b9cd2459e8b7c5557dc0f17574af..b6dd18c6f93e4575f7115f5942fc8025a05281c4 100644 (file)
--- a/decoder/test/parallel/test.conf
+++ b/decoder/test/parallel/test.conf
@@ -2,18 +2,22 @@ test incremental_8ch_short_noclock
        protocol-decoder parallel channel d0=0 channel d1=1 channel d2=2 channel d3=3 channel d4=4 channel d5=5 channel d6=6 channel d7=7
        input misc/demo/incremental_8ch_short.sr
        output parallel annotation match incremental_8ch_short_noclock.output
+       output parallel python match incremental_8ch_short_noclock.python
 
 test incremental_8ch_short_clock
        protocol-decoder parallel channel clk=0 channel d0=0 channel d1=1 channel d2=2 channel d3=3 channel d4=4 channel d5=5 channel d6=6 channel d7=7
        input misc/demo/incremental_8ch_short.sr
        output parallel annotation match incremental_8ch_short_clock.output
+       output parallel python match incremental_8ch_short_clock.python
 
 test incremental_8ch_long_noclock
        protocol-decoder parallel channel d0=0 channel d1=1 channel d2=2 channel d3=3 channel d4=4 channel d5=5 channel d6=6 channel d7=7
        input misc/demo/incremental_8ch_long.sr
        output parallel annotation match incremental_8ch_long_noclock.output
+       output parallel python match incremental_8ch_long_noclock.python
 
 test incremental_8ch_long_clock
        protocol-decoder parallel channel clk=0 channel d0=0 channel d1=1 channel d2=2 channel d3=3 channel d4=4 channel d5=5 channel d6=6 channel d7=7
        input misc/demo/incremental_8ch_long.sr
        output parallel annotation match incremental_8ch_long_clock.output
+       output parallel python match incremental_8ch_long_clock.python