spiflash: Updates due to recent PD chages.

[sigrok-test.git] / decoder / test / uart / rxtx_overlapped.python

59-76 uart: ['STARTBIT', 0, 0]
76-215 uart: ['DATA', 0, (126, [[0, 76, 92], [1, 93, 109], [1, 111, 127], [1, 128, 144], [1, 145, 161], [1, 163, 179], [1, 180, 196], [0, 198, 214]])]
215-232 uart: ['STOPBIT', 0, 1]
232-249 uart: ['STARTBIT', 0, 0]
249-388 uart: ['DATA', 0, (0, [[0, 249, 265], [0, 266, 282], [0, 284, 300], [0, 301, 317], [0, 318, 334], [0, 336, 352], [0, 353, 369], [0, 371, 387]])]
388-405 uart: ['STOPBIT', 0, 1]
405-422 uart: ['STARTBIT', 0, 0]
501-518 uart: ['STARTBIT', 1, 0]
422-561 uart: ['DATA', 0, (16, [[0, 422, 438], [0, 439, 455], [0, 457, 473], [0, 474, 490], [1, 491, 507], [0, 509, 525], [0, 526, 542], [0, 544, 560]])]
561-578 uart: ['STOPBIT', 0, 1]
578-595 uart: ['STARTBIT', 0, 0]
518-657 uart: ['DATA', 1, (126, [[0, 518, 534], [1, 535, 551], [1, 553, 569], [1, 570, 586], [1, 587, 603], [1, 605, 621], [1, 622, 638], [0, 640, 656]])]
657-674 uart: ['STOPBIT', 1, 1]
674-691 uart: ['STARTBIT', 1, 0]
595-734 uart: ['DATA', 0, (32, [[0, 595, 611], [0, 612, 628], [0, 630, 646], [0, 647, 663], [0, 664, 680], [1, 682, 698], [0, 699, 715], [0, 717, 733]])]
734-751 uart: ['STOPBIT', 0, 1]
752-769 uart: ['STARTBIT', 0, 0]
691-830 uart: ['DATA', 1, (0, [[0, 691, 707], [0, 708, 724], [0, 726, 742], [0, 743, 759], [0, 760, 776], [0, 778, 794], [0, 795, 811], [0, 813, 829]])]
830-847 uart: ['STOPBIT', 1, 1]
847-864 uart: ['STARTBIT', 1, 0]
769-908 uart: ['DATA', 0, (1, [[1, 769, 785], [0, 786, 802], [0, 804, 820], [0, 821, 837], [0, 838, 854], [0, 856, 872], [0, 873, 889], [0, 891, 907]])]
908-925 uart: ['STOPBIT', 0, 1]
925-942 uart: ['STARTBIT', 0, 0]
864-1003 uart: ['DATA', 1, (3, [[1, 864, 880], [1, 881, 897], [0, 899, 915], [0, 916, 932], [0, 933, 949], [0, 951, 967], [0, 968, 984], [0, 986, 1002]])]
1003-1020 uart: ['STOPBIT', 1, 1]
1021-1038 uart: ['STARTBIT', 1, 0]
942-1081 uart: ['DATA', 0, (192, [[0, 942, 958], [0, 959, 975], [0, 977, 993], [0, 994, 1010], [0, 1011, 1027], [0, 1029, 1045], [1, 1046, 1062], [1, 1064, 1080]])]
1081-1098 uart: ['STOPBIT', 0, 1]
1098-1115 uart: ['STARTBIT', 0, 0]
1038-1177 uart: ['DATA', 1, (137, [[1, 1038, 1054], [0, 1055, 1071], [0, 1073, 1089], [1, 1090, 1106], [0, 1107, 1123], [0, 1125, 1141], [0, 1142, 1158], [1, 1160, 1176]])]
1177-1194 uart: ['STOPBIT', 1, 1]
1194-1211 uart: ['STARTBIT', 1, 0]
1115-1254 uart: ['DATA', 0, (168, [[0, 1115, 1131], [0, 1132, 1148], [0, 1150, 1166], [1, 1167, 1183], [0, 1184, 1200], [1, 1202, 1218], [0, 1219, 1235], [1, 1237, 1253]])]
1254-1271 uart: ['STOPBIT', 0, 1]
1272-1289 uart: ['STARTBIT', 0, 0]
1211-1350 uart: ['DATA', 1, (1, [[1, 1211, 1227], [0, 1228, 1244], [0, 1246, 1262], [0, 1263, 1279], [0, 1280, 1296], [0, 1298, 1314], [0, 1315, 1331], [0, 1333, 1349]])]
1350-1367 uart: ['STOPBIT', 1, 1]
1367-1384 uart: ['STARTBIT', 1, 0]
1289-1428 uart: ['DATA', 0, (176, [[0, 1289, 1305], [0, 1306, 1322], [0, 1324, 1340], [0, 1341, 1357], [1, 1358, 1374], [1, 1376, 1392], [0, 1393, 1409], [1, 1411, 1427]])]
1428-1445 uart: ['STOPBIT', 0, 1]
1445-1462 uart: ['STARTBIT', 0, 0]
1384-1523 uart: ['DATA', 1, (0, [[0, 1384, 1400], [0, 1401, 1417], [0, 1419, 1435], [0, 1436, 1452], [0, 1453, 1469], [0, 1471, 1487], [0, 1488, 1504], [0, 1506, 1522]])]
1523-1540 uart: ['STOPBIT', 1, 1]
1541-1558 uart: ['STARTBIT', 1, 0]
1462-1601 uart: ['DATA', 0, (31, [[1, 1462, 1478], [1, 1479, 1495], [1, 1497, 1513], [1, 1514, 1530], [1, 1531, 1547], [0, 1549, 1565], [0, 1566, 1582], [0, 1584, 1600]])]
1601-1618 uart: ['STOPBIT', 0, 1]
1618-1635 uart: ['STARTBIT', 0, 0]
1558-1697 uart: ['DATA', 1, (117, [[1, 1558, 1574], [0, 1575, 1591], [1, 1593, 1609], [0, 1610, 1626], [1, 1627, 1643], [1, 1645, 1661], [1, 1662, 1678], [0, 1680, 1696]])]
1697-1714 uart: ['STOPBIT', 1, 1]
1635-1774 uart: ['DATA', 0, (154, [[0, 1635, 1651], [1, 1652, 1668], [0, 1670, 1686], [1, 1687, 1703], [1, 1704, 1720], [0, 1722, 1738], [0, 1739, 1755], [1, 1757, 1773]])]
1774-1791 uart: ['STOPBIT', 0, 1]