uart: Add more UART test-cases.

[sigrok-test.git] / decoder / test / swd / test.conf

test ftdi_openocd_init_write_0xabbabeeb
	protocol-decoder swd
	input swd/ftdi_openocd/init_write_0xabbabeeb.sr
	output swd annotation match ftdi_openocd/init_write_0xabbabeeb.output
	output swd python match ftdi_openocd/init_write_0xabbabeeb.python

test ftdi_openocd_init_noreply
	protocol-decoder swd
	input swd/ftdi_openocd/init_noreply.sr
	output swd annotation match ftdi_openocd/init_noreply.output

test ftdi_openocd_init_wait_fault
	protocol-decoder swd
	input swd/ftdi_openocd/init_wait_fault.sr
	output swd annotation match ftdi_openocd/init_wait_fault.output

test stlink_init_write_0xabbabeeb
	protocol-decoder swd
	input swd/stlink_openocd/init_write_0xabbabeeb.sr
	output swd annotation match stlink_openocd/init_write_0xabbabeeb.output
	output swd python match stlink_openocd/init_write_0xabbabeeb.python

test stlink_wait_retry
	protocol-decoder swd
	input swd/stlink_openocd/wait_retry.sr
	output swd annotation match stlink_openocd/wait_retry.output

# With the strict_start option set, this capture doesn't include a LINERESET
# so output is empty.
test stlink_wait_retry
	protocol-decoder swd option strict_start=yes
	input swd/stlink_openocd/wait_retry.sr
	output swd annotation match stlink_openocd/empty.output