[sigrok-test.git] / decoder / test / modbus / test.conf

test brainchild_io_16do
	protocol-decoder uart channel rx=0 channel tx=1 option baudrate=19200 option invert_rx=yes option invert_tx=yes option parity_type=even
	protocol-decoder modbus option scchannel=RX option cschannel=TX
	stack uart modbus
	input uart/modbus_rtu/brainchild_io_16do/brainchild-io-16do.sr
	output modbus annotation match brainchild_io_16do.output
Commit	Line	Data
87e6446b	1	test brainchild_io_16do
60062a44	2	protocol-decoder uart channel rx=0 channel tx=1 option baudrate=19200 option invert_rx=yes option invert_tx=yes option parity_type=even
fc163ecc	3	protocol-decoder modbus option scchannel=RX option cschannel=TX
87e6446b UH	4	stack uart modbus
	5	input uart/modbus_rtu/brainchild_io_16do/brainchild-io-16do.sr
	6	output modbus annotation match brainchild_io_16do.output