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Added MAX6921 shift register signal dumps.
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1-------------------------------------------------------------------------------
2MAX6921 Shift Register
3-------------------------------------------------------------------------------
4
5This is a capture of data output to a MAX6921 high voltage shift register that
6was outputting data for a VFD clock.
7
8The signals were grabbed on a 28-pin PLCC chip (MAX6921) which outputs 20-bits
9that is crafted as a design for VFD applications.
10
11Logic analyzer setup
12--------------------
13
14The logic analyzer used was Open Bench Logic Sniffer (at 10Mhz):
15
16 Probe MAX6921 Pin
17 --------------------------
18 0 LOAD
19 1 DATA
20 2 CLK
21 3 BLANK (PWM Brightness Control)
22
23Data
24----
25
26The data contain various values for the VFD being driven, as reference at the
27prototype Nixie Cape for the Beaglebone.
28
29 Digit Bit
30 --------------------------
31 0 1<<12
32 1 1<<19
33 2 1<<13
34 3 1<<18
35 4 1<<14
36 5 1<<17
37 6 1<<16
38 7 1<<15
39 8 1<<15
40 9 1<<11
41
42 Segment Bit
43 ---------------------------
44 SEG_A 1<<0
45 SEG_B 1<<1
46 SEG_C 1<<2
47 SEG_D 1<<3
48 SEG_E 1<<4
49 SEG_F 1<<5
50 SEG_G 1<<6
51 SEG_H 1<<7
52
53
54References:
55-----------
56
57 * BeagleBoard.org Vendor Tree (https://github.com/beagleboard/kernel)
58 * Beagle Nixie GitHub (https://github.com/mranostay/beagle-nixie/)
59 * MAX6921 Datasheet (http://datasheets.maximintegrated.com/en/ds/MAX6921-MAX6931.pdf)
60
61The sigrok command line used was:
62
63 sigrok-cli --driver=ols:conn=/dev/ttyACM0 -d samplerate=10mhz \
64 -samples=24576 -p 0=LOAD,1=DATA,2=CLK,3=BLANK -o max6921_data_10mhz.sr
65