projects / sigrok-dumps.git / blame
| Commit | Line | Data |
|---|---|---|
| 8e055025 MJ |
1 | ------------------------------------------------------------------------------- |
| 2 | SWIM | |
| 3 | ------------------------------------------------------------------------------- | |
| 4 | ||
| 5 | These are captures of an ST-Link V2 programming an STM8 using the SWIM protocol. | |
| 6 | ||
| 7 | Details: | |
| 8 | https://www.st.com/content/ccc/resource/technical/document/user_manual/ca/89/41/4e/72/31/49/f4/CD00173911.pdf/files/CD00173911.pdf/jcr:content/translations/en.CD00173911.pdf | |
| 9 | ||
| 10 | ||
| 11 | Logic analyzer setup | |
| 12 | -------------------- | |
| 13 | ||
| 14 | The logic analyser used was a DreamSourceLab DSLogic (at 10MHz). | |
| 15 | ||
| 16 | Probe Target | |
| 17 | ------------------ | |
| 18 | 0 RST | |
| 19 | 1 SWIM | |
| 20 | ||
| 21 | ||
| 22 | Data | |
| 23 | ---- | |
| 24 | ||
| 25 | Using stm8flash with an ST-Link V2 adapter to program an STM8S003F3. | |
| 26 | ||
| 27 | Command line: | |
| 28 | ||
| 29 | $ stm8flash -c stlinkv2 -p stm8s003f3 -s opt -r /tmp/data; stm8flash -c \ | |
| 30 | stlinkv2 -p stm8s003f3 -s opt -r /tmp/data | |
| 31 | ||
| 32 | stm8flash is modified both for correctness and to generate the test sequences. | |
| 33 | The updated version can be found at https://github.com/mjagdis/stm8flash. | |
| 34 | ||
| 35 | ||
| 36 | tests/sample1.sr | |
| 37 | ---------------- | |
| 38 | ||
| 39 | Read of two blocks of memory from an STM8S103 starting at the base address | |
| 40 | of the OPTs. Repeated twice with no SRST to disable SWIM in between. | |
| 41 | Note that the second enter sequence is not seen as an enter sequence. Since | |
| 42 | SWIM is already active on the target it does NOT recognise a second enter | |
| 43 | sequence and instead sees each low sent by the host as a SWIM reset request | |
| 44 | to which it responds, if you zoom in enough, with its own 16μs sync frame. | |
| 45 | ||
| 46 | ||
| 47 | tests/sample2.sr | |
| 48 | ---------------- | |
| 49 | ||
| 50 | As sample1 but each of the runs ends with an SWIM reset followed by an SRST | |
| 51 | (system reset) SWIM command. Note that the SWIM reset consists of the host | |
| 52 | pulling the SWIM line low for 16μs to reset the target's SWIM module followed | |
| 53 | by the target acknowledging with its own synchronization frame (i.e. it pulls | |
| 54 | the line low for another 16μs). Note too that the RST bit is not set in | |
| 55 | SWIM_CSR so the SRST does not disable SWIM and the second enter sequence is | |
| 56 | treated as resyncing just as in sample1. | |
| 57 | ||
| 58 | ||
| 59 | tests/sample3.sr | |
| 60 | ---------------- | |
| 61 | ||
| 62 | As sample2 but now we modify stm8flash to set RST (bit 2) in SWIM_CSR (0x7f80) | |
| 63 | as part of its shutdown. This causes the SRST to disable SWIM as well as reset | |
| 64 | the target and now the subsequent enter sequence behaves as expected. | |
| 65 | ||
| 66 | ||
| 67 | tests/sample4.sr | |
| 68 | ---------------- | |
| 69 | ||
| 70 | As sample3 but the SRST at the end of each run is removed again. The second | |
| 71 | enter sequence is no longer recognised as an enter sequence and the target | |
| 72 | again responds to each low by with a sync frame indicating it is treating them | |
| 73 | as SWIM reset requests. This demonstrates that the SRST SWIM command is indeed | |
| 74 | responsible for disabling the SWIM module and that an external reset via the | |
| 75 | RST pin is insufficient regardless of the setting of the RST bit in SWIM_CSR. |