[sigrok-dumps.git] / spi / sqi / README

------------------------------------------------------------------------
SQI communication (multi-I/O SPI)
------------------------------------------------------------------------

This capture demonstrates SQI communication, which is a form of SPI data
exchange where transmitters use multiple I/O data lines in parallel to
communicate the same amount of data in fewer clock cycles.

In contrast to e.g. QuadSPI flash memory chips which may change the data
line count or clock scheme several times within a transaction, SQI keeps
the clock and the number of data lines used by the transmitter consistent
across the full length of the SPI transaction. Only the direction of data
lines could change, when e.g. a master first transmits a request which
the slave then responds to, while both use the same number of data lines.
Full duplex communication as with the traditional MISO/MOSI scheme is
not possible with SQI.


Logic analyzer setup
--------------------

The capture was taken at a samplerate of 100MHz.

  Probe       SPI
  ----------------------------
  2           SCK (clock)
  3           CS (select)
  4           IO0 (data, LSB)
  5           IO1
  6           IO2
  7           IO3 (data, MSB)


sqi-four-data-lines-one-transfer.sr
-----------------------------------

This capture uses four I/O data lines. Data gets sampled at the rising
clock edge (single data rate). Data is sent in MSB first order. The SPI
transaction's data byte sequence is:

  80 00 00 10 22 42 4f 4f 54 00 80 00 00 a8 85 77 00 20 4e 00 00


sqi-four-data-lines-three-transfers.sr
--------------------------------------

This capture was constructed from the above single-transfer example
capture. The SPI transfer is repeated three times.
Commit	Line	Data
e7a4e115 GS	1	------------------------------------------------------------------------
	2	SQI communication (multi-I/O SPI)
	3	------------------------------------------------------------------------
	4
	5	This capture demonstrates SQI communication, which is a form of SPI data
	6	exchange where transmitters use multiple I/O data lines in parallel to
	7	communicate the same amount of data in fewer clock cycles.
	8
	9	In contrast to e.g. QuadSPI flash memory chips which may change the data
	10	line count or clock scheme several times within a transaction, SQI keeps
	11	the clock and the number of data lines used by the transmitter consistent
	12	across the full length of the SPI transaction. Only the direction of data
	13	lines could change, when e.g. a master first transmits a request which
	14	the slave then responds to, while both use the same number of data lines.
	15	Full duplex communication as with the traditional MISO/MOSI scheme is
	16	not possible with SQI.
	17
	18
	19	Logic analyzer setup
	20	--------------------
	21
	22	The capture was taken at a samplerate of 100MHz.
	23
	24	Probe SPI
	25	----------------------------
	26	2 SCK (clock)
	27	3 CS (select)
	28	4 IO0 (data, LSB)
	29	5 IO1
	30	6 IO2
	31	7 IO3 (data, MSB)
	32
	33
	34	sqi-four-data-lines-one-transfer.sr
	35	-----------------------------------
	36
	37	This capture uses four I/O data lines. Data gets sampled at the rising
	38	clock edge (single data rate). Data is sent in MSB first order. The SPI
	39	transaction's data byte sequence is:
	40
	41	80 00 00 10 22 42 4f 4f 54 00 80 00 00 a8 85 77 00 20 4e 00 00
	42
	43
	44	sqi-four-data-lines-three-transfers.sr
	45	--------------------------------------
	46
	47	This capture was constructed from the above single-transfer example
	48	capture. The SPI transfer is repeated three times.