[sigrok-dumps.git] / pjon / pjdl / README

-------------------------------------------------------------------------------
PJON over PJDL
-------------------------------------------------------------------------------

This is a collection of example PJON communication which uses the PJDL
link layer. Which does serial communication on a single wire, and the
reference library happens to implement it by means of software bitbang
(which affects the timing of signals on the wire).


Logic analyzer setup
--------------------

The capture was taken with a logic analyzer at a samplerate of 4MSa/s.
Communication is done on a single channel.

  Probe       PJDL
  ----------------
  1           data


pjon-pjdl-glitch-and-ack-and-failed-ack.sr
------------------------------------------

Two STM32F103 (Blue Pill boards) run the example code which resides in
the examples/ARDUINO/Local/SoftwareBitBang/SendAndReceive/Device1/ and
Device2/ directories. Communication mode 1 translates to 44us and 116us
for data and pad bits. Device addresses are 44 and 45. The letter 'B' is
sent as the payload data in both directions. Synchronous responses get
requested, but one device won't respond. The capture also contains a few
glitches which as a byproduct exercise the decoder's robustness, and
recovery after synchronization loss.


pjon-pjdl-incomplete-frame-missing-ack-repetitive.sr
----------------------------------------------------

This is a longer capture taken from the above setup. Some of the glitches
happen to fall into a PJON frame's period and can prevent or can disturb
the accumulation of the frame's content.
Commit	Line	Data
55a8021a GS	1	-------------------------------------------------------------------------------
	2	PJON over PJDL
	3	-------------------------------------------------------------------------------
	4
	5	This is a collection of example PJON communication which uses the PJDL
	6	link layer. Which does serial communication on a single wire, and the
	7	reference library happens to implement it by means of software bitbang
	8	(which affects the timing of signals on the wire).
	9
	10
	11	Logic analyzer setup
	12	--------------------
	13
	14	The capture was taken with a logic analyzer at a samplerate of 4MSa/s.
	15	Communication is done on a single channel.
	16
	17	Probe PJDL
	18	----------------
	19	1 data
	20
	21
	22	pjon-pjdl-glitch-and-ack-and-failed-ack.sr
	23	------------------------------------------
	24
	25	Two STM32F103 (Blue Pill boards) run the example code which resides in
	26	the examples/ARDUINO/Local/SoftwareBitBang/SendAndReceive/Device1/ and
	27	Device2/ directories. Communication mode 1 translates to 44us and 116us
	28	for data and pad bits. Device addresses are 44 and 45. The letter 'B' is
	29	sent as the payload data in both directions. Synchronous responses get
	30	requested, but one device won't respond. The capture also contains a few
	31	glitches which as a byproduct exercise the decoder's robustness, and
	32	recovery after synchronization loss.
	33
	34
	35	pjon-pjdl-incomplete-frame-missing-ack-repetitive.sr
	36	----------------------------------------------------
	37
	38	This is a longer capture taken from the above setup. Some of the glitches
	39	happen to fall into a PJON frame's period and can prevent or can disturb
	40	the accumulation of the frame's content.