projects / sigrok-dumps.git / blame
| Commit | Line | Data |
|---|---|---|
| f83bdf56 UH |
1 | ------------------------------------------------------------------------------- |
| 2 | Onewire dumps, sockit_owm master | |
| 3 | ------------------------------------------------------------------------------- | |
| 4 | ||
| 5 | This directory contains waveforms created by accessing various onewire devices | |
| d3149842 IJ |
6 | using the 'sockit_owm' Verilog master. The master is used in a demo hardware |
| 7 | (Terasic DE1 development board, and a Quartus/Qsys project) and software (also | |
| f83bdf56 | 8 | available as a Nios II project) implementation. |
| d3149842 | 9 | |
| f83bdf56 | 10 | Details: |
| d3149842 IJ |
11 | https://github.com/jeras/sockit_owm |
| 12 | ||
| 13 | ||
| f83bdf56 UH |
14 | Logic analyzer setup |
| 15 | -------------------- | |
| 16 | ||
| 17 | The logic analyzer used was a Saleae Logic (at 8MHz): | |
| 18 | ||
| 19 | Probe 1-Wire pin | |
| 20 | ---------------------- | |
| 21 | 1 (black) OWR | |
| 22 | ||
| 23 | ||
| 24 | Data | |
| 25 | ---- | |
| d3149842 | 26 | |
| f83bdf56 | 27 | The sigrok command line used was: |
| b636dd75 | 28 | |
| f83bdf56 | 29 | sigrok-cli -d 0:samplerate=8000000 --time 4s -p 1=OWR -t OWR=0 -o onewire.sr |
| d3149842 IJ |
30 | |
| 31 | This is the console output after running the demo: | |
| 32 | ||
| b636dd75 IJ |
33 | (0) 6700000003A6A842 25.9 Celsius |
| 34 | (1) 3F000000C8CF9B28 25.8 Celsius | |
| 35 | (2) 44000801E51EC510 25.9 Celsius | |
| 36 |