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Onewire dumps, sockit_owm master
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This directory contains waveforms created by accessing various onewire devices
using the 'sockit_owm' Verilog master. The master is used in a demo hardware
(Terasic DE1 development board, and a Quartus/Qsys project) and software (also
available as a Nios II project) implementation.

Details:
https://github.com/jeras/sockit_owm


Logic analyzer setup
--------------------

The logic analyzer used was a Saleae Logic (at 8MHz):

  Probe       1-Wire pin
  ----------------------
  1 (black)   OWR


Data
----

The sigrok command line used was:

  sigrok-cli -d 0:samplerate=8000000 --time 4s -p 1=OWR -t OWR=0 -o onewire.sr

This is the console output after running the demo:

(0) 6700000003A6A842  25.9 Celsius
(1) 3F000000C8CF9B28  25.8 Celsius
(2) 44000801E51EC510  25.9 Celsius