projects / sigrok-dumps.git / blame
| Commit | Line | Data |
|---|---|---|
| 13f998d4 MR |
1 | ------------------------------------------------------------------------------- |
| 2 | WS2801 LED strip | |
| 3 | ------------------------------------------------------------------------------- | |
| 4 | ||
| 5 | This is a capture of data output an LED universes of 50 RGB LEDS. | |
| 6 | ||
| 7 | Every universe at full capacity of has a frame size of 768 bytes and can clock | |
| 8 | out at roughly 100 frames per second. | |
| 9 | ||
| 10 | Details: | |
| 11 | - Koen Kooi's evil vendor tree: https://github.com/koenkooi/kernel | |
| 12 | - PRU WS2801 firmware: https://github.com/mranostay/ws28xx-lighting-pru | |
| 13 | - WS2801 datasheet: http://www.adafruit.com/datasheets/WS2801.pdf | |
| 14 | ||
| 15 | ||
| 16 | WS2812B protocol overview | |
| 17 | ------------------------- | |
| 18 | ||
| 19 | Each LED receives and the stores the first 24-bits of RGB ordered data then | |
| 20 | passes any more out the Data Output pin to the next LED in the chain. | |
| 21 | ||
| 22 | There is no CS line but latching is done when CLK is held low for >500 uS | |
| 23 | ||
| 24 | This functions as a "reverse" shift register and allows the strip length not to | |
| 25 | be defined in the protocol. | |
| 26 | ||
| 27 | ||
| 28 | Logic analyzer setup | |
| 29 | -------------------- | |
| 30 | ||
| 31 | The logic analzyer used was a Saleae Logic16 (at 5mhz) | |
| 32 | ||
| 33 | Probe WS2812B LED strip | |
| 34 | ------------------------- | |
| 35 | 1 (black) Universe #1 | |
| 36 | 2 (brown) Clock | |
| 37 | ||
| 38 | Data | |
| 39 | ---- | |
| 40 | ||
| 41 | The data contains various RGB values and frames. | |
| 42 | ||
| 43 | The sigrok command line used was: | |
| 44 | ||
| 45 | sigrok-cli --driver saleae-logic16 --samples 10M --config samplerate=5mhz \ | |
| 46 | -p 0=UNI1,1=CLK -o ws2801_2ch_5mhz.sr |