]> sigrok.org Git - pulseview.git/blobdiff - test/logicdatasnapshot.cpp
Corrected project name in header comments
[pulseview.git] / test / logicdatasnapshot.cpp
index cf3898e2fa10edecfe0ec08e7549f280ad06c458..4e31bfae8f0a1d21fb10e324043f6f17fb9307b3 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * This file is part of the sigrok project.
+ * This file is part of the PulseView project.
  *
  * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
  *
@@ -23,6 +23,7 @@
 
 #include <boost/test/unit_test.hpp>
 
+#include "../extdef.h"
 #include "../logicdatasnapshot.h"
 
 using namespace std;
@@ -254,8 +255,8 @@ BOOST_AUTO_TEST_CASE(LargeData)
        }
 
        //----- Test LogicDataSnapshot::get_subsampled_edges -----//
+       // Check in normal case
        vector<LogicDataSnapshot::EdgePair> edges;
-
        s.get_subsampled_edges(edges, 0, Length-1, 1, 7);
 
        BOOST_CHECK_EQUAL(edges.size(), 32);
@@ -267,6 +268,12 @@ BOOST_AUTO_TEST_CASE(LargeData)
        }
 
        BOOST_CHECK_EQUAL(edges[31].first, 999999);
+
+       // Check in very low zoom case
+       edges.clear();
+       s.get_subsampled_edges(edges, 0, Length-1, 50e6f, 7);
+
+       BOOST_CHECK_EQUAL(edges.size(), 2);
 }
 
 BOOST_AUTO_TEST_CASE(Pulses)
@@ -291,6 +298,7 @@ BOOST_AUTO_TEST_CASE(Pulses)
        }
 
        LogicDataSnapshot s(logic);
+       delete[] (uint8_t*)logic.data;
 
        //----- Check the mip-map -----//
        // Check mip map level 0
@@ -341,19 +349,20 @@ BOOST_AUTO_TEST_CASE(LongPulses)
 
        //----- Create a LogicDataSnapshot -----//
        sr_datafeed_logic logic;
-       logic.unitsize = 1;
+       logic.unitsize = 8;
        logic.length = Length;
-       logic.data = (uint64_t*)new uint8_t[Length];
-       uint8_t *p = (uint8_t*)logic.data;
+       logic.data = (uint64_t*)new uint64_t[Length];
+       uint64_t *p = (uint64_t*)logic.data;
 
        for(int i = 0; i < Cycles; i++) {
                for(j = 0; j < PulseWidth; j++)
-                       *p++ = 0xFF;
+                       *p++ = ~0;
                for(j; j < Period; j++)
-                       *p++ = 0x00;
+                       *p++ = 0;
        }
 
        LogicDataSnapshot s(logic);
+       delete[] (uint64_t*)logic.data;
 
        //----- Check the mip-map -----//
        // Check mip map level 0
@@ -366,14 +375,14 @@ BOOST_AUTO_TEST_CASE(LongPulses)
                for(j = 0; i < s._mip_map[0].length && j < 2; j++) {
                        BOOST_TEST_MESSAGE(
                                "Testing mip_map[0].data[" << i << "]");
-                       BOOST_CHECK_EQUAL(s.get_subsample(0, i++) & 0xFF, 0xFF);
+                       BOOST_CHECK_EQUAL(s.get_subsample(0, i++), ~0);
                }
 
                for(j; i < s._mip_map[0].length &&
                        j < Period/LogicDataSnapshot::MipMapScaleFactor; j++) {
                        BOOST_TEST_MESSAGE(
                                "Testing mip_map[0].data[" << i << "]");
-                       BOOST_CHECK_EQUAL(s.get_subsample(0, i++) & 0xFF, 0x00);
+                       BOOST_CHECK_EQUAL(s.get_subsample(0, i++)0);
                }
        }
 
@@ -417,4 +426,52 @@ BOOST_AUTO_TEST_CASE(LongPulses)
        BOOST_CHECK_EQUAL(edges.back().second, false);
 }
 
+BOOST_AUTO_TEST_CASE(LisaMUsbHid)
+{
+       /* This test was created from the beginning of the USB_DM signal in
+        * sigrok-dumps-usb/lisa_m_usbhid/lisa_m_usbhid.sr
+        */
+
+       const int Edges[] = {
+               7028, 7033, 7036, 7041, 7044, 7049, 7053, 7066, 7073, 7079,
+               7086, 7095, 7103, 7108, 7111, 7116, 7119, 7124, 7136, 7141,
+               7148, 7162, 7500
+       };
+       const int Length = Edges[countof(Edges) - 1];
+
+       bool state = false;
+       int lastEdgePos = 0;
+
+       //----- Create a LogicDataSnapshot -----//
+       sr_datafeed_logic logic;
+       logic.unitsize = 1;
+       logic.length = Length;
+       logic.data = new uint8_t[Length];
+       uint8_t *data = (uint8_t*)logic.data;
+
+       for(int i = 0; i < countof(Edges); i++) {
+               const int edgePos = Edges[i];
+               memset(&data[lastEdgePos], state ? 0x02 : 0,
+                       edgePos - lastEdgePos - 1);
+
+               lastEdgePos = edgePos;
+               state = !state;
+       }
+
+       LogicDataSnapshot s(logic);
+       delete[] (uint64_t*)logic.data;
+
+       vector<LogicDataSnapshot::EdgePair> edges;
+
+
+       /* The trailing edge of the pulse train is falling in the source data.
+        * Check this is always true at different scales
+        */
+
+       edges.clear();
+       s.get_subsampled_edges(edges, 0, Length-1, 33.333332f, 1);
+       BOOST_CHECK_EQUAL(edges[edges.size() - 2].second, false);
+}
+
+
 BOOST_AUTO_TEST_SUITE_END()