LogicSegment: Remove constructor requiring sigrok::Logic

[pulseview.git] / pv / data / logicsegment.cpp

diff --git a/pv/data/logicsegment.cpp b/pv/data/logicsegment.cpp
index 5191a3f03e76a2654202f84039e18d574898b56e..25aa2d0aa445bd2671129e60d51585f746dda6a2 100644 (file)
--- a/pv/data/logicsegment.cpp
+++ b/pv/data/logicsegment.cpp
@@ -35,6 +35,7 @@ using std::max;
 using std::min;
 using std::pair;
 using std::shared_ptr;
+using std::vector;
 
 using sigrok::Logic;
 
@@ -46,15 +47,13 @@ const int LogicSegment::MipMapScaleFactor = 1 << MipMapScalePower;
 const float LogicSegment::LogMipMapScaleFactor = logf(MipMapScaleFactor);
 const uint64_t LogicSegment::MipMapDataUnit = 64*1024; // bytes
 
-LogicSegment::LogicSegment(pv::data::Logic& owner, shared_ptr<sigrok::Logic> data,
+LogicSegment::LogicSegment(pv::data::Logic& owner, unsigned int unit_size,
        uint64_t samplerate) :
-       Segment(samplerate, data->unit_size()),
+       Segment(samplerate, unit_size),
        owner_(owner),
        last_append_sample_(0)
 {
-       lock_guard<recursive_mutex> lock(mutex_);
        memset(mip_map_, 0, sizeof(mip_map_));
-       append_payload(data);
 }
 
 LogicSegment::~LogicSegment()
@@ -143,12 +142,19 @@ void LogicSegment::append_payload(shared_ptr<sigrok::Logic> logic)
        assert(unit_size_ == logic->unit_size());
        assert((logic->data_length() % unit_size_) == 0);
 
+       append_payload(logic->data_pointer(), logic->data_length());
+}
+
+void LogicSegment::append_payload(void *data, uint64_t data_size)
+{
+       assert((data_size % unit_size_) == 0);
+
        lock_guard<recursive_mutex> lock(mutex_);
 
        uint64_t prev_sample_count = sample_count_;
-       uint64_t sample_count = logic->data_length() / unit_size_;
+       uint64_t sample_count = data_size / unit_size_;
 
-       append_samples(logic->data_pointer(), sample_count);
+       append_samples(data, sample_count);
 
        // Generate the first mip-map from the data
        append_payload_to_mipmap();
@@ -298,7 +304,7 @@ uint64_t LogicSegment::get_unpacked_sample(uint64_t index) const
 }
 
 void LogicSegment::get_subsampled_edges(
-       std::vector<EdgePair> &edges,
+       vector<EdgePair> &edges,
        uint64_t start, uint64_t end,
        float min_length, int sig_index)
 {