'''
OUTPUT_PYTHON format:
-SPI packet:
-[<cmd>, <data1>, <data2>]
+Packet:
+[<ptype>, <data1>, <data2>]
-Commands:
- - 'DATA': <data1> contains the MISO data, <data2> contains the MOSI data.
+<ptype>:
+ - 'DATA': <data1> contains the MOSI data, <data2> contains the MISO data.
The data is _usually_ 8 bits (but can also be fewer or more bits).
Both data items are Python numbers (not strings), or None if the respective
- probe was not supplied.
- - 'BITS': <data1>/<data2> contain a list of bit values in this MISO/MOSI data
+ channel was not supplied.
+ - 'BITS': <data1>/<data2> contain a list of bit values in this MOSI/MISO data
item, and for each of those also their respective start-/endsample numbers.
- 'CS CHANGE': <data1> is the old CS# pin value, <data2> is the new value.
Both data items are Python numbers (0/1), not strings.
(1, 1): 3, # Mode 3
}
+class SamplerateError(Exception):
+ pass
+
+class MissingDataError(Exception):
+ pass
+
class Decoder(srd.Decoder):
- api_version = 1
+ api_version = 2
id = 'spi'
name = 'SPI'
longname = 'Serial Peripheral Interface'
license = 'gplv2+'
inputs = ['logic']
outputs = ['spi']
- probes = [
+ channels = (
{'id': 'clk', 'name': 'CLK', 'desc': 'Clock'},
- ]
- optional_probes = [
+ )
+ optional_channels = (
{'id': 'miso', 'name': 'MISO', 'desc': 'Master in, slave out'},
{'id': 'mosi', 'name': 'MOSI', 'desc': 'Master out, slave in'},
{'id': 'cs', 'name': 'CS#', 'desc': 'Chip-select'},
- ]
- options = {
- 'cs_polarity': ['CS# polarity', 'active-low'],
- 'cpol': ['Clock polarity', 0],
- 'cpha': ['Clock phase', 0],
- 'bitorder': ['Bit order within the SPI data', 'msb-first'],
- 'wordsize': ['Word size of SPI data', 8], # 1-64?
- 'format': ['Data format', 'hex'],
- }
- annotations = [
- ['miso-data', 'MISO data'],
- ['mosi-data', 'MOSI data'],
- ['miso-bits', 'MISO bits'],
- ['mosi-bits', 'MOSI bits'],
- ['warnings', 'Human-readable warnings'],
- ]
+ )
+ options = (
+ {'id': 'cs_polarity', 'desc': 'CS# polarity', 'default': 'active-low',
+ 'values': ('active-low', 'active-high')},
+ {'id': 'cpol', 'desc': 'Clock polarity', 'default': 0,
+ 'values': (0, 1)},
+ {'id': 'cpha', 'desc': 'Clock phase', 'default': 0,
+ 'values': (0, 1)},
+ {'id': 'bitorder', 'desc': 'Bit order',
+ 'default': 'msb-first', 'values': ('msb-first', 'lsb-first')},
+ {'id': 'wordsize', 'desc': 'Word size', 'default': 8},
+ )
+ annotations = (
+ ('miso-data', 'MISO data'),
+ ('mosi-data', 'MOSI data'),
+ ('miso-bits', 'MISO bits'),
+ ('mosi-bits', 'MOSI bits'),
+ ('warnings', 'Human-readable warnings'),
+ )
annotation_rows = (
('miso-data', 'MISO data', (0,)),
('miso-bits', 'MISO bits', (2,)),
self.oldcs = -1
self.oldpins = None
self.have_cs = self.have_miso = self.have_mosi = None
- self.state = 'IDLE'
def metadata(self, key, value):
if key == srd.SRD_CONF_SAMPLERATE:
self.out_bitrate = self.register(srd.OUTPUT_META,
meta=(int, 'Bitrate', 'Bitrate during transfers'))
- def putpw(self, data):
- self.put(self.startsample, self.samplenum, self.out_python, data)
-
def putw(self, data):
self.put(self.startsample, self.samplenum, self.out_ann, data)
si = self.mosidata if self.have_mosi else None
so_bits = self.misobits if self.have_miso else None
si_bits = self.mosibits if self.have_mosi else None
- self.putpw(['BITS', si_bits, so_bits])
- self.putpw(['DATA', si, so])
+
+ if self.have_miso:
+ ss, es = self.misobits[-1][1], self.misobits[0][2]
+ if self.have_mosi:
+ ss, es = self.mosibits[-1][1], self.mosibits[0][2]
+
+ self.put(ss, es, self.out_python, ['BITS', si_bits, so_bits])
+ self.put(ss, es, self.out_python, ['DATA', si, so])
# Bit annotations.
if self.have_miso:
# Dataword annotations.
if self.have_miso:
- ss, es = self.misobits[-1][1], self.misobits[0][2]
self.put(ss, es, self.out_ann, [0, ['%02X' % self.misodata]])
if self.have_mosi:
- ss, es = self.mosibits[-1][1], self.mosibits[0][2]
self.put(ss, es, self.out_ann, [1, ['%02X' % self.mosidata]])
def reset_decoder_state(self):
self.cs_was_deasserted = False
if self.have_cs:
active_low = (self.options['cs_polarity'] == 'active-low')
- deasserted = (cs == 1) if active_low else (cs == 0)
- if deasserted:
- self.cs_was_deasserted = True
+ self.cs_was_deasserted = (cs == 1) if active_low else (cs == 0)
ws = self.options['wordsize']
self.handle_bit(miso, mosi, clk, cs)
def decode(self, ss, es, data):
- if self.samplerate is None:
- raise Exception("Cannot decode without samplerate.")
+ if not self.samplerate:
+ raise SamplerateError("Cannot decode without samplerate.")
# Either MISO or MOSI can be omitted (but not both). CS# is optional.
for (self.samplenum, pins) in data:
# Either MISO or MOSI (but not both) can be omitted.
if not (self.have_miso or self.have_mosi):
- raise Exception('Either MISO or MOSI (or both) pins required.')
+ raise MissingDataError('Either MISO or MOSI (or both) pins required.')
- # State machine.
- if self.state == 'IDLE':
- self.find_clk_edge(miso, mosi, clk, cs)
- else:
- raise Exception('Invalid state: %s' % self.state)
+ self.find_clk_edge(miso, mosi, clk, cs)
projects / libsigrokdecode.git / blobdiff