2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 import sigrokdecode as srd
30 class Decoder(srd.Decoder):
34 longname = 'Texas Instruments TLC5620'
35 desc = 'Texas Instruments TLC5620 8-bit quad DAC.'
40 {'id': 'clk', 'name': 'CLK', 'desc': 'Serial interface clock'},
41 {'id': 'data', 'name': 'DATA', 'desc': 'Serial interface data'},
44 {'id': 'load', 'name': 'LOAD', 'desc': 'Serial interface load control'},
45 {'id': 'ldac', 'name': 'LDAC', 'desc': 'Load DAC'},
48 ('dac-select', 'DAC select'),
50 ('value', 'DAC value'),
51 ('data-latch', 'Data latch point'),
52 ('ldac-fall', 'LDAC falling edge'),
55 def __init__(self, **kwargs):
56 self.oldpins = self.oldclk = self.oldload = self.oldldac = None
59 self.ss_dac = self.es_dac = 0
60 self.ss_gain = self.es_gain = 0
61 self.ss_value = self.es_value = 0
62 self.dac_select = self.gain = self.dac_value = None
65 # self.out_python = self.register(srd.OUTPUT_PYTHON)
66 self.out_ann = self.register(srd.OUTPUT_ANN)
68 def handle_11bits(self):
69 s = "".join(str(i) for i in self.bits[:2])
70 self.dac_select = s = dacs[int(s, 2)]
71 self.put(self.ss_dac, self.es_dac, self.out_ann,
72 [0, ['DAC select: %s' % s, 'DAC sel: %s' % s,
73 'DAC: %s' % s, 'D: %s' % s, s, s[3]]])
75 self.gain = g = 1 + self.bits[2]
76 self.put(self.ss_gain, self.es_gain, self.out_ann,
77 [1, ['Gain: x%d' % g, 'G: x%d' % g, 'x%d' % g]])
79 s = "".join(str(i) for i in self.bits[3:])
80 self.dac_value = v = int(s, 2)
81 self.put(self.ss_value, self.es_value, self.out_ann,
82 [2, ['DAC value: %d' % v, 'Value: %d' % v, 'Val: %d' % v,
83 'V: %d' % v, '%d' % v]])
85 def handle_falling_edge_load(self):
86 s, v, g = self.dac_select, self.dac_value, self.gain
87 self.put(self.samplenum, self.samplenum, self.out_ann,
88 [3, ['Setting %s value to %d (x%d gain)' % (s, v, g),
89 '%s=%d (x%d gain)' % (s, v, g)]])
91 def handle_falling_edge_ldac(self):
92 self.put(self.samplenum, self.samplenum, self.out_ann,
93 [4, ['Falling edge on LDAC pin', 'LDAC fall', 'LDAC']])
95 def handle_new_dac_bit(self):
96 self.bits.append(self.datapin)
98 # Wait until we have read 11 bits, then parse them.
99 l, s = len(self.bits), self.samplenum
103 self.es_dac = self.ss_gain = s
105 self.es_gain = self.ss_value = s
111 def decode(self, ss, es, data):
112 for (self.samplenum, pins) in data:
114 # Ignore identical samples early on (for performance reasons).
115 if self.oldpins == pins:
117 self.oldpins, (clk, self.datapin, load, ldac) = pins, pins
119 # DATA is shifted in the DAC on the falling CLK edge (MSB-first).
120 # A falling edge of LOAD will latch the data.
122 if self.oldload == 1 and load == 0:
123 self.handle_falling_edge_load()
124 if self.oldldac == 1 and ldac == 0:
125 self.handle_falling_edge_ldac()
126 if self.oldclk == 1 and clk == 0:
127 self.handle_new_dac_bit()