2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, write to the Free Software
18 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 # LPC protocol decoder
23 import sigrokdecode as srd
27 # START field (indicates start or stop of a transaction)
29 0b0000: 'Start of cycle for a target',
31 0b0010: 'Grant for bus master 0',
32 0b0011: 'Grant for bus master 1',
42 0b1101: 'Start of cycle for a Firmware Memory Read cycle',
43 0b1110: 'Start of cycle for a Firmware Memory Write cycle',
44 0b1111: 'Stop/abort (end of a cycle for a target)',
46 # Cycle type / direction field
47 # Bit 0 (LAD[0]) is unused, should always be 0.
48 # Neither host nor peripheral are allowed to drive 0b11x0.
52 0b0100: 'Memory read',
53 0b0110: 'Memory write',
56 0b1100: 'Reserved / not allowed',
57 0b1110: 'Reserved / not allowed',
59 # SIZE field (determines how many bytes are to be transferred)
60 # Bits[3:2] are reserved, must be driven to 0b00.
61 # Neither host nor peripheral are allowed to drive 0b0010.
63 0b0000: '8 bits (1 byte)',
64 0b0001: '16 bits (2 bytes)',
65 0b0010: 'Reserved / not allowed',
66 0b0011: '32 bits (4 bytes)',
68 # CHANNEL field (bits[2:0] contain the DMA channel number)
79 # SYNC field (used to add wait states)
90 0b1001: 'Ready more (DMA only)',
100 class Decoder(srd.Decoder):
104 longname = 'Low-Pin-Count'
105 desc = 'Protocol for low-bandwidth devices on PC mainboards.'
110 {'id': 'lframe', 'name': 'LFRAME#', 'desc': 'TODO'},
111 {'id': 'lreset', 'name': 'LRESET#', 'desc': 'TODO'},
112 {'id': 'lclk', 'name': 'LCLK', 'desc': 'TODO'},
113 {'id': 'lad0', 'name': 'LAD[0]', 'desc': 'TODO'},
114 {'id': 'lad1', 'name': 'LAD[1]', 'desc': 'TODO'},
115 {'id': 'lad2', 'name': 'LAD[2]', 'desc': 'TODO'},
116 {'id': 'lad3', 'name': 'LAD[3]', 'desc': 'TODO'},
119 {'id': 'ldrq', 'name': 'LDRQ#', 'desc': 'TODO'},
120 {'id': 'serirq', 'name': 'SERIRQ', 'desc': 'TODO'},
121 {'id': 'clkrun', 'name': 'CLKRUN#', 'desc': 'TODO'},
122 {'id': 'lpme', 'name': 'LPME#', 'desc': 'TODO'},
123 {'id': 'lpcpd', 'name': 'LPCPD#', 'desc': 'TODO'},
124 {'id': 'lsmi', 'name': 'LSMI#', 'desc': 'TODO'},
128 ['Text', 'Human-readable text'],
131 def __init__(self, **kwargs):
143 self.oldpins = (-1, -1, -1, -1, -1, -1, -1)
145 def start(self, metadata):
146 # self.out_proto = self.add(srd.OUTPUT_PROTO, 'lpc')
147 self.out_ann = self.add(srd.OUTPUT_ANN, 'lpc')
152 def handle_get_start(self, lad, lad_bits, lframe):
153 # LAD[3:0]: START field (1 clock cycle).
155 # The last value of LAD[3:0] before LFRAME# gets de-asserted is what
156 # the peripherals must use. However, the host can keep LFRAME# asserted
157 # multiple clocks, and we output all START fields that occur, even
158 # though the peripherals are supposed to ignore all but the last one.
159 s = fields['START'][lad]
160 self.put(0, 0, self.out_ann, [0, [s]])
162 # Output a warning if LAD[3:0] changes while LFRAME# is low.
164 if (self.lad != -1 and self.lad != lad):
165 self.put(0, 0, self.out_ann,
166 [0, ['Warning: LAD[3:0] changed while '
167 'LFRAME# was asserted']])
169 # LFRAME# is asserted (low). Wait until it gets de-asserted again
170 # (the host is allowed to keep it asserted multiple clocks).
174 self.start_field = self.lad
175 self.state = 'GET CT/DR'
177 def handle_get_ct_dr(self, lad, lad_bits):
178 # LAD[3:0]: Cycle type / direction field (1 clock cycle).
180 self.cycle_type = fields['CT_DR'][lad]
182 # TODO: Warning/error on invalid cycle types.
183 if self.cycle_type == 'Reserved':
184 self.put(0, 0, self.out_ann,
185 [0, ['Warning: Invalid cycle type (%s)' % lad_bits]])
188 self.put(0, 0, self.out_ann, [0, ['Cycle type: %s' % self.cycle_type]])
190 self.state = 'GET ADDR'
194 def handle_get_addr(self, lad, lad_bits):
195 # LAD[3:0]: ADDR field (4/8/0 clock cycles).
197 # I/O cycles: 4 ADDR clocks. Memory cycles: 8 ADDR clocks.
198 # DMA cycles: no ADDR clocks at all.
199 if self.cycle_type in ('I/O read', 'I/O write'):
200 addr_nibbles = 4 # Address is 16bits.
201 elif self.cycle_type in ('Memory read', 'Memory write'):
202 addr_nibbles = 8 # Address is 32bits.
204 addr_nibbles = 0 # TODO: How to handle later on?
206 # Addresses are driven MSN-first.
207 offset = ((addr_nibbles - 1) - self.cur_nibble) * 4
208 self.addr |= (lad << offset)
210 # Continue if we haven't seen all ADDR cycles, yet.
211 if (self.cur_nibble < addr_nibbles - 1):
215 s = 'Address: 0x%%0%dx' % addr_nibbles
216 self.put(0, 0, self.out_ann, [0, [s % self.addr]])
218 self.state = 'GET TAR'
221 def handle_get_tar(self, lad, lad_bits):
222 # LAD[3:0]: First TAR (turn-around) field (2 clock cycles).
224 self.put(0, 0, self.out_ann, [0, ['TAR, cycle %d: %s'
225 % (self.tarcount, lad_bits)]])
227 # On the first TAR clock cycle LAD[3:0] is driven to 1111 by
228 # either the host or peripheral. On the second clock cycle,
229 # the host or peripheral tri-states LAD[3:0], but its value
230 # should still be 1111, due to pull-ups on the LAD lines.
231 if lad_bits != '1111':
232 self.put(0, 0, self.out_ann,
233 [0, ['Warning: TAR, cycle %d: %s (expected 1111)'
234 % (self.tarcount, lad_bits)]])
236 if (self.tarcount != 1):
241 self.state = 'GET SYNC'
243 def handle_get_sync(self, lad, lad_bits):
244 # LAD[3:0]: SYNC field (1-n clock cycles).
246 self.sync_val = lad_bits
247 self.cycle_type = fields['SYNC'][lad]
249 # TODO: Warnings if reserved value are seen?
250 if self.cycle_type == 'Reserved':
251 self.put(0, 0, self.out_ann, [0, ['Warning: SYNC, cycle %d: %s '
252 '(reserved value)' % (self.synccount, self.sync_val)]])
254 self.put(0, 0, self.out_ann, [0, ['SYNC, cycle %d: %s'
255 % (self.synccount, self.sync_val)]])
260 self.state = 'GET DATA'
262 def handle_get_data(self, lad, lad_bits):
263 # LAD[3:0]: DATA field (2 clock cycles).
265 # Data is driven LSN-first.
266 if (self.cycle_count == 0):
268 elif (self.cycle_count == 1):
269 self.databyte |= (lad << 4)
271 raise Exception('Invalid cycle_count: %d' % self.cycle_count)
273 if (self.cycle_count != 1):
274 self.cycle_count += 1
277 self.put(0, 0, self.out_ann, [0, ['DATA: 0x%02x' % self.databyte]])
280 self.state = 'GET TAR2'
282 def handle_get_tar2(self, lad, lad_bits):
283 # LAD[3:0]: Second TAR field (2 clock cycles).
285 self.put(0, 0, self.out_ann, [0, ['TAR, cycle %d: %s'
286 % (self.tarcount, lad_bits)]])
288 # On the first TAR clock cycle LAD[3:0] is driven to 1111 by
289 # either the host or peripheral. On the second clock cycle,
290 # the host or peripheral tri-states LAD[3:0], but its value
291 # should still be 1111, due to pull-ups on the LAD lines.
292 if lad_bits != '1111':
293 self.put(0, 0, self.out_ann,
294 [0, ['Warning: TAR, cycle %d: %s (expected 1111)'
295 % (self.tarcount, lad_bits)]])
297 if (self.tarcount != 1):
304 def decode(self, ss, es, data):
305 for (samplenum, pins) in data:
307 # If none of the pins changed, there's nothing to do.
308 if self.oldpins == pins:
311 # Store current pin values for the next round.
314 # Get individual pin values into local variables.
315 # TODO: Handle optional pins.
316 (lframe, lreset, lclk, lad0, lad1, lad2, lad3) = pins
318 # Only look at the signals upon rising LCLK edges. The LPC clock
319 # is the same as the PCI clock (which is sampled at rising edges).
320 if not (self.oldlclk == 0 and lclk == 1):
324 # Store LAD[3:0] bit values (one nibble) in local variables.
325 # Most (but not all) states need this.
326 if self.state != 'IDLE':
327 lad = (lad3 << 3) | (lad2 << 2) | (lad1 << 1) | lad0
328 lad_bits = bin(lad)[2:].zfill(4)
329 # self.put(0, 0, self.out_ann, [0, ['LAD: %s' % lad_bits]])
331 # TODO: Only memory read/write is currently supported/tested.
334 if self.state == 'IDLE':
335 # A valid LPC cycle starts with LFRAME# being asserted (low).
338 self.state = 'GET START'
341 elif self.state == 'GET START':
342 self.handle_get_start(lad, lad_bits, lframe)
343 elif self.state == 'GET CT/DR':
344 self.handle_get_ct_dr(lad, lad_bits)
345 elif self.state == 'GET ADDR':
346 self.handle_get_addr(lad, lad_bits)
347 elif self.state == 'GET TAR':
348 self.handle_get_tar(lad, lad_bits)
349 elif self.state == 'GET SYNC':
350 self.handle_get_sync(lad, lad_bits)
351 elif self.state == 'GET DATA':
352 self.handle_get_data(lad, lad_bits)
353 elif self.state == 'GET TAR2':
354 self.handle_get_tar2(lad, lad_bits)
356 raise Exception('Invalid state: %s' % self.state)