2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2014 Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; either version 2 of the License, or
9 ## (at your option) any later version.
11 ## This program is distributed in the hope that it will be useful,
12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ## GNU General Public License for more details.
16 ## You should have received a copy of the GNU General Public License
17 ## along with this program; if not, see <http://www.gnu.org/licenses/>.
20 import sigrokdecode as srd
22 # Helper dictionary for edge detection.
24 'rising': lambda x, y: bool(not x and y),
25 'falling': lambda x, y: bool(x and not y),
26 'both': lambda x, y: bool(x ^ y),
29 class SamplerateError(Exception):
32 class Decoder(srd.Decoder):
36 longname = 'Timing jitter calculation'
37 desc = 'Retrieves the timing jitter between two digital signals.'
42 {'id': 'clk', 'name': 'Clock', 'desc': 'Clock reference channel'},
43 {'id': 'sig', 'name': 'Resulting signal', 'desc': 'Resulting signal controlled by the clock'},
46 {'id': 'clk_polarity', 'desc': 'Clock edge polarity',
47 'default': 'rising', 'values': ('rising', 'falling', 'both')},
48 {'id': 'sig_polarity', 'desc': 'Resulting signal edge polarity',
49 'default': 'rising', 'values': ('rising', 'falling', 'both')},
52 ('jitter', 'Jitter value'),
53 ('clk_missed', 'Clock missed'),
54 ('sig_missed', 'Signal missed'),
57 ('jitter', 'Jitter values', (0,)),
58 ('clk_missed', 'Clock missed', (1,)),
59 ('sig_missed', 'Signal missed', (2,)),
62 ('ascii-float', 'Jitter values as newline-separated ASCII floats'),
70 self.samplerate = None
71 self.oldclk, self.oldsig = 0, 0
78 self.clk_edge = edge_detector[self.options['clk_polarity']]
79 self.sig_edge = edge_detector[self.options['sig_polarity']]
80 self.out_ann = self.register(srd.OUTPUT_ANN)
81 self.out_binary = self.register(srd.OUTPUT_BINARY)
82 self.out_clk_missed = self.register(srd.OUTPUT_META,
83 meta=(int, 'Clock missed', 'Clock transition missed'))
84 self.out_sig_missed = self.register(srd.OUTPUT_META,
85 meta=(int, 'Signal missed', 'Resulting signal transition missed'))
87 def metadata(self, key, value):
88 if key == srd.SRD_CONF_SAMPLERATE:
89 self.samplerate = value
91 # Helper function for jitter time annotations.
92 def putx(self, delta):
94 if delta == 0 or delta >= 1:
95 delta_s = '%.1fs' % (delta)
97 delta_s = '%.1ffs' % (delta * 1e15)
99 delta_s = '%.1fps' % (delta * 1e12)
101 delta_s = '%.1fns' % (delta * 1e9)
103 delta_s = '%.1fμs' % (delta * 1e6)
105 delta_s = '%.1fms' % (delta * 1e3)
107 self.put(self.clk_start, self.sig_start, self.out_ann, [0, [delta_s]])
109 # Helper function for ASCII float jitter values (one value per line).
110 def putb(self, delta):
113 # Format the delta to an ASCII float value terminated by a newline.
114 x = str(delta) + '\n'
115 self.put(self.clk_start, self.sig_start, self.out_binary,
116 [0, x.encode('UTF-8')])
118 # Helper function for missed clock and signal annotations.
119 def putm(self, data):
120 self.put(self.samplenum, self.samplenum, self.out_ann, data)
122 def handle_clk(self, clk, sig):
123 if self.clk_start == self.samplenum:
124 # Clock transition already treated.
125 # We have done everything we can with this sample.
128 if self.clk_edge(self.oldclk, clk):
130 # We note the sample and move to the next state.
131 self.clk_start = self.samplenum
135 if self.sig_start is not None \
136 and self.sig_start != self.samplenum \
137 and self.sig_edge(self.oldsig, sig):
138 # If any transition in the resulting signal
139 # occurs while we are waiting for a clock,
140 # we increase the missed signal counter.
142 self.put(self.samplenum, self.samplenum, self.out_sig_missed, self.sig_missed)
143 self.putm([2, ['Missed signal', 'MS']])
144 # No clock edge found, we have done everything we
145 # can with this sample.
148 def handle_sig(self, clk, sig):
149 if self.sig_start == self.samplenum:
150 # Signal transition already treated.
151 # We have done everything we can with this sample.
154 if self.sig_edge(self.oldsig, sig):
156 # We note the sample, calculate the jitter
157 # and move to the next state.
158 self.sig_start = self.samplenum
160 # Calculate and report the timing jitter.
161 delta = (self.sig_start - self.clk_start) / self.samplerate
166 if self.clk_start != self.samplenum \
167 and self.clk_edge(self.oldclk, clk):
168 # If any transition in the clock signal
169 # occurs while we are waiting for a resulting
170 # signal, we increase the missed clock counter.
172 self.put(self.samplenum, self.samplenum, self.out_clk_missed, self.clk_missed)
173 self.putm([1, ['Missed clock', 'MC']])
174 # No resulting signal edge found, we have done
175 # everything we can with this sample.
179 if not self.samplerate:
180 raise SamplerateError('Cannot decode without samplerate.')
182 # Wait for a transition on CLK and/or SIG.
183 clk, sig = self.wait([{0: 'e'}, {1: 'e'}])
186 # For each sample we can move 2 steps forward in the state machine.
188 # Clock state has the lead.
189 if self.state == 'CLK':
190 if self.handle_clk(clk, sig):
192 if self.state == 'SIG':
193 if self.handle_sig(clk, sig):
196 # Save current CLK/SIG values for the next round.
197 self.oldclk, self.oldsig = clk, sig