2 ## This file is part of the libsigrokdecode project.
4 ## Copyright (C) 2012-2015 Uwe Hermann <uwe@hermann-uwe.de>
5 ## Copyright (C) 2019 Zhiyuan Wan <dv.xw@qq.com>
6 ## Copyright (C) 2019 Kongou Hikari <hikari@iloli.bid>
8 ## This program is free software; you can redistribute it and/or modify
9 ## it under the terms of the GNU General Public License as published by
10 ## the Free Software Foundation; either version 2 of the License, or
11 ## (at your option) any later version.
13 ## This program is distributed in the hope that it will be useful,
14 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ## GNU General Public License for more details.
18 ## You should have received a copy of the GNU General Public License
19 ## along with this program; if not, see <http://www.gnu.org/licenses/>.
22 import sigrokdecode as srd
31 - 'NEW STATE': <pdata> is the new state of the JTAG state machine.
32 Valid values: 'TEST-LOGIC-RESET', 'RUN-TEST/IDLE', 'SELECT-DR-SCAN',
33 'CAPTURE-DR', 'SHIFT-DR', 'EXIT1-DR', 'PAUSE-DR', 'EXIT2-DR', 'UPDATE-DR',
34 'SELECT-IR-SCAN', 'CAPTURE-IR', 'SHIFT-IR', 'EXIT1-IR', 'PAUSE-IR',
35 'EXIT2-IR', 'UPDATE-IR'.
36 - 'IR TDI': Bitstring that was clocked into the IR register.
37 - 'IR TDO': Bitstring that was clocked out of the IR register.
38 - 'DR TDI': Bitstring that was clocked into the DR register.
39 - 'DR TDO': Bitstring that was clocked out of the DR register.
41 All bitstrings are a list consisting of two items. The first is a sequence
42 of '1' and '0' characters (the right-most character is the LSB. Example:
43 '01110001', where 1 is the LSB). The second item is a list of ss/es values
44 for each bit that is in the bitstring.
49 'TEST-LOGIC-RESET', 'RUN-TEST/IDLE',
51 'SELECT-DR-SCAN', 'CAPTURE-DR', 'UPDATE-DR', 'PAUSE-DR',
52 'SHIFT-DR', 'EXIT1-DR', 'EXIT2-DR',
54 'SELECT-IR-SCAN', 'CAPTURE-IR', 'UPDATE-IR', 'PAUSE-IR',
55 'SHIFT-IR', 'EXIT1-IR', 'EXIT2-IR',
58 class Decoder(srd.Decoder):
62 longname = 'Compact Joint Test Action Group (IEEE 1149.7)'
63 desc = 'Protocol for testing, debugging, and flashing ICs.'
67 tags = ['Debug/trace']
69 {'id': 'tckc', 'name': 'TCKC', 'desc': 'Test clock'},
70 {'id': 'tmsc', 'name': 'TMSC', 'desc': 'Test mode select'},
72 annotations = tuple([tuple([s.lower(), s]) for s in jtag_states]) + ( \
73 ('bit-tdi', 'Bit (TDI)'),
74 ('bit-tdo', 'Bit (TDO)'),
75 ('bitstring-tdi', 'Bitstring (TDI)'),
76 ('bitstring-tdo', 'Bitstring (TDO)'),
77 ('bit-tms', 'Bit (TMS)'),
78 ('state-tapc', 'TAPC state'),
81 ('bits-tdi', 'Bits (TDI)', (16,)),
82 ('bits-tdo', 'Bits (TDO)', (17,)),
83 ('bitstrings-tdi', 'Bitstrings (TDI)', (18,)),
84 ('bitstrings-tdo', 'Bitstrings (TDO)', (19,)),
85 ('bits-tms', 'Bits (TMS)', (20,)),
86 ('states-tapc', 'TAPC states', (21,)),
87 ('states', 'States', tuple(range(15 + 1))),
94 # self.state = 'TEST-LOGIC-RESET'
95 self.state = 'RUN-TEST/IDLE'
96 self.cjtagstate = '4-WIRE'
97 self.oldcjtagstate = None
106 self.bits_samplenums_tdi = []
107 self.bits_samplenums_tdo = []
108 self.ss_item = self.es_item = None
109 self.ss_bitstring = self.es_bitstring = None
110 self.saved_item = None
112 self.first_bit = True
115 self.out_python = self.register(srd.OUTPUT_PYTHON)
116 self.out_ann = self.register(srd.OUTPUT_ANN)
118 def putx(self, data):
119 self.put(self.ss_item, self.es_item, self.out_ann, data)
121 def putp(self, data):
122 self.put(self.ss_item, self.es_item, self.out_python, data)
124 def putx_bs(self, data):
125 self.put(self.ss_bitstring, self.es_bitstring, self.out_ann, data)
127 def putp_bs(self, data):
128 self.put(self.ss_bitstring, self.es_bitstring, self.out_python, data)
130 def advance_state_machine(self, tms):
131 self.oldstate = self.state
133 if self.cjtagstate.startswith('CJTAG-'):
135 if self.oacp > 4 and self.oaclen == 12:
136 self.cjtagstate = 'CJTAG-EC'
138 if self.oacp == 8 and tms == 0:
140 if self.oacp > 8 and self.oaclen == 36:
141 self.cjtagstate = 'CJTAG-SPARE'
142 if self.oacp > 13 and self.oaclen == 36:
143 self.cjtagstate = 'CJTAG-TPDEL'
144 if self.oacp > 16 and self.oaclen == 36:
145 self.cjtagstate = 'CJTAG-TPREV'
146 if self.oacp > 18 and self.oaclen == 36:
147 self.cjtagstate = 'CJTAG-TPST'
148 if self.oacp > 23 and self.oaclen == 36:
149 self.cjtagstate = 'CJTAG-RDYC'
150 if self.oacp > 25 and self.oaclen == 36:
151 self.cjtagstate = 'CJTAG-DLYC'
152 if self.oacp > 27 and self.oaclen == 36:
153 self.cjtagstate = 'CJTAG-SCNFMT'
155 if self.oacp > 8 and self.oaclen == 12:
156 self.cjtagstate = 'CJTAG-CP'
157 if self.oacp > 32 and self.oaclen == 36:
158 self.cjtagstate = 'CJTAG-CP'
160 if self.oacp > self.oaclen:
161 self.cjtagstate = 'OSCAN1'
163 # Because Nuclei cJTAG device asserts a reset during cJTAG
165 self.state = 'TEST-LOGIC-RESET'
169 if self.state == 'TEST-LOGIC-RESET':
170 self.state = 'TEST-LOGIC-RESET' if (tms) else 'RUN-TEST/IDLE'
171 elif self.state == 'RUN-TEST/IDLE':
172 self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
175 elif self.state == 'SELECT-DR-SCAN':
176 self.state = 'SELECT-IR-SCAN' if (tms) else 'CAPTURE-DR'
177 elif self.state == 'CAPTURE-DR':
178 self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR'
179 elif self.state == 'SHIFT-DR':
180 self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR'
181 elif self.state == 'EXIT1-DR':
182 self.state = 'UPDATE-DR' if (tms) else 'PAUSE-DR'
183 elif self.state == 'PAUSE-DR':
184 self.state = 'EXIT2-DR' if (tms) else 'PAUSE-DR'
185 elif self.state == 'EXIT2-DR':
186 self.state = 'UPDATE-DR' if (tms) else 'SHIFT-DR'
187 elif self.state == 'UPDATE-DR':
188 self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
191 elif self.state == 'SELECT-IR-SCAN':
192 self.state = 'TEST-LOGIC-RESET' if (tms) else 'CAPTURE-IR'
193 elif self.state == 'CAPTURE-IR':
194 self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR'
195 elif self.state == 'SHIFT-IR':
196 self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR'
197 elif self.state == 'EXIT1-IR':
198 self.state = 'UPDATE-IR' if (tms) else 'PAUSE-IR'
199 elif self.state == 'PAUSE-IR':
200 self.state = 'EXIT2-IR' if (tms) else 'PAUSE-IR'
201 elif self.state == 'EXIT2-IR':
202 self.state = 'UPDATE-IR' if (tms) else 'SHIFT-IR'
203 elif self.state == 'UPDATE-IR':
204 self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
206 def handle_rising_tckc_edge(self, tdi, tdo, tck, tms):
208 # Rising TCK edges always advance the state machine.
209 self.advance_state_machine(tms)
212 # Save the start sample and item for later (no output yet).
213 self.ss_item = self.samplenum
216 # Output the saved item (from the last CLK edge to the current).
217 self.es_item = self.samplenum
218 # Output the old state (from last rising TCK edge to current one).
219 self.putx([jtag_states.index(self.oldstate), [self.oldstate]])
220 self.putp(['NEW STATE', self.state])
222 self.putx([21, [self.oldcjtagstate]])
223 if (self.oldcjtagstate.startswith('CJTAG-')):
224 self.putx([20, [str(self.oldtms)]])
227 # Upon SHIFT-*/EXIT1-* collect the current TDI/TDO values.
228 if self.oldstate.startswith('SHIFT-') or \
229 self.oldstate.startswith('EXIT1-'):
231 self.ss_bitstring = self.samplenum
232 self.first_bit = False
234 self.putx([16, [str(self.bits_tdi[0])]])
235 self.putx([17, [str(self.bits_tdo[0])]])
236 # Use self.samplenum as ES of the previous bit.
237 self.bits_samplenums_tdi[0][1] = self.samplenum
238 self.bits_samplenums_tdo[0][1] = self.samplenum
240 self.bits_tdi.insert(0, tdi)
241 self.bits_tdo.insert(0, tdo)
243 # Use self.samplenum as SS of the current bit.
244 self.bits_samplenums_tdi.insert(0, [self.samplenum, -1])
245 self.bits_samplenums_tdo.insert(0, [self.samplenum, -1])
247 # Output all TDI/TDO bits if we just switched to UPDATE-*.
248 if self.state.startswith('UPDATE-'):
250 self.es_bitstring = self.samplenum
252 t = self.state[-2:] + ' TDI'
253 b = ''.join(map(str, self.bits_tdi[1:]))
254 h = ' (0x%x' % int('0b0' + b, 2) + ')'
255 s = t + ': ' + b + h + ', ' + str(len(self.bits_tdi[1:])) + ' bits'
256 self.putx_bs([18, [s]])
257 self.putp_bs([t, [b, self.bits_samplenums_tdi[1:]]])
259 self.bits_samplenums_tdi = []
261 t = self.state[-2:] + ' TDO'
262 b = ''.join(map(str, self.bits_tdo[1:]))
263 h = ' (0x%x' % int('0b0' + b, 2) + ')'
264 s = t + ': ' + b + h + ', ' + str(len(self.bits_tdo[1:])) + ' bits'
265 self.putx_bs([19, [s]])
266 self.putp_bs([t, [b, self.bits_samplenums_tdo[1:]]])
268 self.bits_samplenums_tdo = []
270 self.first_bit = True
272 self.ss_bitstring = self.samplenum
274 self.ss_item = self.samplenum
276 def handle_tmsc_edge(self):
277 self.escape_edges += 1
279 def handle_tapc_state(self):
280 self.oldcjtagstate = self.cjtagstate
282 if self.escape_edges >= 8:
283 self.cjtagstate = '4-WIRE'
284 if self.escape_edges == 6:
285 self.cjtagstate = 'CJTAG-OAC'
289 self.escape_edges = 0
297 # Wait for a rising edge on TCKC.
298 tckc, tmsc = self.wait({0: 'r'})
299 self.handle_tapc_state()
301 if self.cjtagstate == 'OSCAN1':
302 if self.oscan1cycle == 0: # nTDI
303 tdi_real = 1 if (tmsc == 0) else 0
305 elif self.oscan1cycle == 1: # TMS
308 elif self.oscan1cycle == 2: # TDO
310 self.handle_rising_tckc_edge(tdi_real, tdo_real, tckc, tms_real)
313 self.handle_rising_tckc_edge(None, None, tckc, tmsc)
316 tckc, tmsc_n = self.wait([{0: 'f'}, {1: 'e'}])
319 self.handle_tmsc_edge()