[libsigrokdecode.git] / decoders / i2c / pd.py

##
## This file is part of the libsigrokdecode project.
##
## Copyright (C) 2010-2013 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

# I²C protocol decoder

# TODO: Look into arbitration, collision detection, clock synchronisation, etc.
# TODO: Implement support for 10bit slave addresses.
# TODO: Implement support for inverting SDA/SCL levels (0->1 and 1->0).
# TODO: Implement support for detecting various bus errors.

import sigrokdecode as srd

'''
Protocol output format:

I²C packet:
[<cmd>, <data>]

<cmd> is one of:
 - 'START' (START condition)
 - 'START REPEAT' (Repeated START condition)
 - 'ADDRESS READ' (Slave address, read)
 - 'ADDRESS WRITE' (Slave address, write)
 - 'DATA READ' (Data, read)
 - 'DATA WRITE' (Data, write)
 - 'STOP' (STOP condition)
 - 'ACK' (ACK bit)
 - 'NACK' (NACK bit)

<data> is the data or address byte associated with the 'ADDRESS*' and 'DATA*'
command. Slave addresses do not include bit 0 (the READ/WRITE indication bit).
For example, a slave address field could be 0x51 (instead of 0xa2).
For 'START', 'START REPEAT', 'STOP', 'ACK', and 'NACK' <data> is None.
'''

# CMD: [annotation-type-index, long annotation, short annotation]
proto = {
    'START':           [0, 'Start',         'S'],
    'START REPEAT':    [1, 'Start repeat',  'Sr'],
    'STOP':            [2, 'Stop',          'P'],
    'ACK':             [3, 'ACK',           'A'],
    'NACK':            [4, 'NACK',          'N'],
    'ADDRESS READ':    [5, 'Address read',  'AR'],
    'ADDRESS WRITE':   [6, 'Address write', 'AW'],
    'DATA READ':       [7, 'Data read',     'DR'],
    'DATA WRITE':      [8, 'Data write',    'DW'],
}

class Decoder(srd.Decoder):
    api_version = 1
    id = 'i2c'
    name = 'I²C'
    longname = 'Inter-Integrated Circuit'
    desc = 'Two-wire, multi-master, serial bus.'
    license = 'gplv2+'
    inputs = ['logic']
    outputs = ['i2c']
    probes = [
        {'id': 'scl', 'name': 'SCL', 'desc': 'Serial clock line'},
        {'id': 'sda', 'name': 'SDA', 'desc': 'Serial data line'},
    ]
    optional_probes = []
    options = {
        'address_format': ['Displayed slave address format', 'shifted'],
    }
    annotations = [
        ['start', 'Start condition'],
        ['repeat-start', 'Repeat start condition'],
        ['stop', 'Stop condition'],
        ['ack', 'ACK'],
        ['nack', 'NACK'],
        ['address-read', 'Address read'],
        ['address-write', 'Address write'],
        ['data-read', 'Data read'],
        ['data-write', 'Data write'],
        ['warnings', 'Human-readable warnings'],
    ]
    binary = (
        ('address-read', 'Address read'),
        ('address-write', 'Address write'),
        ('data-read', 'Data read'),
        ('data-write', 'Data write'),
    )

    def __init__(self, **kwargs):
        self.samplerate = None
        self.startsample = -1
        self.samplenum = None
        self.bitcount = 0
        self.databyte = 0
        self.wr = -1
        self.is_repeat_start = 0
        self.state = 'FIND START'
        self.oldscl = 1
        self.oldsda = 1
        self.oldpins = [1, 1]
        self.pdu_start = None
        self.pdu_bits = 0

    def metadata(self, key, value):
        if key == srd.SRD_CONF_SAMPLERATE:
            self.samplerate = value

    def start(self):
        self.out_proto = self.register(srd.OUTPUT_PYTHON)
        self.out_ann = self.register(srd.OUTPUT_ANN)
        self.out_binary = self.register(srd.OUTPUT_BINARY)
        self.out_bitrate = self.register(srd.OUTPUT_META,
                meta=(int, 'Bitrate', 'Bitrate from Start bit to Stop bit'))

    def putx(self, data):
        self.put(self.startsample, self.samplenum, self.out_ann, data)

    def putp(self, data):
        self.put(self.startsample, self.samplenum, self.out_proto, data)

    def putb(self, data):
        self.put(self.startsample, self.samplenum, self.out_binary, data)

    def is_start_condition(self, scl, sda):
        # START condition (S): SDA = falling, SCL = high
        if (self.oldsda == 1 and sda == 0) and scl == 1:
            return True
        return False

    def is_data_bit(self, scl, sda):
        # Data sampling of receiver: SCL = rising
        if self.oldscl == 0 and scl == 1:
            return True
        return False

    def is_stop_condition(self, scl, sda):
        # STOP condition (P): SDA = rising, SCL = high
        if (self.oldsda == 0 and sda == 1) and scl == 1:
            return True
        return False

    def found_start(self, scl, sda):
        self.startsample = self.samplenum
        self.pdu_start = self.samplenum
        self.pdu_bits = 0
        cmd = 'START REPEAT' if (self.is_repeat_start == 1) else 'START'
        self.putp([cmd, None])
        self.putx([proto[cmd][0], proto[cmd][1:]])
        self.state = 'FIND ADDRESS'
        self.bitcount = self.databyte = 0
        self.is_repeat_start = 1
        self.wr = -1

    # Gather 8 bits of data plus the ACK/NACK bit.
    def found_address_or_data(self, scl, sda):
        # Address and data are transmitted MSB-first.
        self.databyte <<= 1
        self.databyte |= sda

        if self.bitcount == 0:
            self.startsample = self.samplenum

        # Return if we haven't collected all 8 + 1 bits, yet.
        self.bitcount += 1
        if self.bitcount != 8:
            return

        # We triggered on the ACK/NACK bit, but won't report that until later.
        self.startsample -= 1

        d = self.databyte
        if self.state == 'FIND ADDRESS':
            # The READ/WRITE bit is only in address bytes, not data bytes.
            self.wr = 0 if (self.databyte & 1) else 1
            if self.options['address_format'] == 'shifted':
                d = d >> 1

        bin_class = -1
        if self.state == 'FIND ADDRESS' and self.wr == 1:
            cmd = 'ADDRESS WRITE'
            bin_class = 1
        elif self.state == 'FIND ADDRESS' and self.wr == 0:
            cmd = 'ADDRESS READ'
            bin_class = 0
        elif self.state == 'FIND DATA' and self.wr == 1:
            cmd = 'DATA WRITE'
            bin_class = 3
        elif self.state == 'FIND DATA' and self.wr == 0:
            cmd = 'DATA READ'
            bin_class = 2

        self.putp([cmd, d])
        self.putx([proto[cmd][0], ['%s: %02X' % (proto[cmd][1], d),
                  '%s: %02X' % (proto[cmd][2], d), '%02X' % d]])
        self.putb((bin_class, bytes([d])))

        # Done with this packet.
        self.startsample = -1
        self.bitcount = self.databyte = 0
        self.state = 'FIND ACK'

    def get_ack(self, scl, sda):
        self.startsample = self.samplenum
        cmd = 'NACK' if (sda == 1) else 'ACK'
        self.putp([cmd, None])
        self.putx([proto[cmd][0], proto[cmd][1:]])
        # There could be multiple data bytes in a row, so either find
        # another data byte or a STOP condition next.
        self.state = 'FIND DATA'

    def found_stop(self, scl, sda):
        # Meta bitrate
        elapsed = 1 / float(self.samplerate) * (self.samplenum - self.pdu_start + 1)
        bitrate = int(1 / elapsed * self.pdu_bits)
        self.put(self.startsample, self.samplenum, self.out_bitrate, bitrate)

        self.startsample = self.samplenum
        cmd = 'STOP'
        self.putp([cmd, None])
        self.putx([proto[cmd][0], proto[cmd][1:]])
        self.state = 'FIND START'
        self.is_repeat_start = 0
        self.wr = -1

    def decode(self, ss, es, data):
        if self.samplerate is None:
            raise Exception("Cannot decode without samplerate.")
        for (self.samplenum, pins) in data:

            # Ignore identical samples early on (for performance reasons).
            if self.oldpins == pins:
                continue
            self.oldpins, (scl, sda) = pins, pins

            self.pdu_bits += 1

            # TODO: Wait until the bus is idle (SDA = SCL = 1) first?

            # State machine.
            if self.state == 'FIND START':
                if self.is_start_condition(scl, sda):
                    self.found_start(scl, sda)
            elif self.state == 'FIND ADDRESS':
                if self.is_data_bit(scl, sda):
                    self.found_address_or_data(scl, sda)
            elif self.state == 'FIND DATA':
                if self.is_data_bit(scl, sda):
                    self.found_address_or_data(scl, sda)
                elif self.is_start_condition(scl, sda):
                    self.found_start(scl, sda)
                elif self.is_stop_condition(scl, sda):
                    self.found_stop(scl, sda)
            elif self.state == 'FIND ACK':
                if self.is_data_bit(scl, sda):
                    self.get_ack(scl, sda)
            else:
                raise Exception('Invalid state: %s' % self.state)

            # Save current SDA/SCL values for the next round.
            self.oldscl = scl
            self.oldsda = sda
Commit	Line	Data
	1	##
	2	## This file is part of the libsigrokdecode project.
	3	##
	4	## Copyright (C) 2010-2013 Uwe Hermann <uwe@hermann-uwe.de>
	5	##
	6	## This program is free software; you can redistribute it and/or modify
	7	## it under the terms of the GNU General Public License as published by
	8	## the Free Software Foundation; either version 2 of the License, or
	9	## (at your option) any later version.
	10	##
	11	## This program is distributed in the hope that it will be useful,
	12	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	## GNU General Public License for more details.
	15	##
	16	## You should have received a copy of the GNU General Public License
	17	## along with this program; if not, write to the Free Software
	18	## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	19	##
	20
	21	# I²C protocol decoder
	22
	23	# TODO: Look into arbitration, collision detection, clock synchronisation, etc.
	24	# TODO: Implement support for 10bit slave addresses.
	25	# TODO: Implement support for inverting SDA/SCL levels (0->1 and 1->0).
	26	# TODO: Implement support for detecting various bus errors.
	27
	28	import sigrokdecode as srd
	29
	30	'''
	31	Protocol output format:
	32
	33	I²C packet:
	34	[<cmd>, <data>]
	35
	36	<cmd> is one of:
	37	- 'START' (START condition)
	38	- 'START REPEAT' (Repeated START condition)
	39	- 'ADDRESS READ' (Slave address, read)
	40	- 'ADDRESS WRITE' (Slave address, write)
	41	- 'DATA READ' (Data, read)
	42	- 'DATA WRITE' (Data, write)
	43	- 'STOP' (STOP condition)
	44	- 'ACK' (ACK bit)
	45	- 'NACK' (NACK bit)
	46
	47	<data> is the data or address byte associated with the 'ADDRESS' and 'DATA'
	48	command. Slave addresses do not include bit 0 (the READ/WRITE indication bit).
	49	For example, a slave address field could be 0x51 (instead of 0xa2).
	50	For 'START', 'START REPEAT', 'STOP', 'ACK', and 'NACK' <data> is None.
	51	'''
	52
	53	# CMD: [annotation-type-index, long annotation, short annotation]
	54	proto = {
	55	'START': [0, 'Start', 'S'],
	56	'START REPEAT': [1, 'Start repeat', 'Sr'],
	57	'STOP': [2, 'Stop', 'P'],
	58	'ACK': [3, 'ACK', 'A'],
	59	'NACK': [4, 'NACK', 'N'],
	60	'ADDRESS READ': [5, 'Address read', 'AR'],
	61	'ADDRESS WRITE': [6, 'Address write', 'AW'],
	62	'DATA READ': [7, 'Data read', 'DR'],
	63	'DATA WRITE': [8, 'Data write', 'DW'],
	64	}
	65
	66	class Decoder(srd.Decoder):
	67	api_version = 1
	68	id = 'i2c'
	69	name = 'I²C'
	70	longname = 'Inter-Integrated Circuit'
	71	desc = 'Two-wire, multi-master, serial bus.'
	72	license = 'gplv2+'
	73	inputs = ['logic']
	74	outputs = ['i2c']
	75	probes = [
	76	{'id': 'scl', 'name': 'SCL', 'desc': 'Serial clock line'},
	77	{'id': 'sda', 'name': 'SDA', 'desc': 'Serial data line'},
	78	]
	79	optional_probes = []
	80	options = {
	81	'address_format': ['Displayed slave address format', 'shifted'],
	82	}
	83	annotations = [
	84	['start', 'Start condition'],
	85	['repeat-start', 'Repeat start condition'],
	86	['stop', 'Stop condition'],
	87	['ack', 'ACK'],
	88	['nack', 'NACK'],
	89	['address-read', 'Address read'],
	90	['address-write', 'Address write'],
	91	['data-read', 'Data read'],
	92	['data-write', 'Data write'],
	93	['warnings', 'Human-readable warnings'],
	94	]
	95	binary = (
	96	('address-read', 'Address read'),
	97	('address-write', 'Address write'),
	98	('data-read', 'Data read'),
	99	('data-write', 'Data write'),
	100	)
	101
	102	def __init__(self, **kwargs):
	103	self.samplerate = None
	104	self.startsample = -1
	105	self.samplenum = None
	106	self.bitcount = 0
	107	self.databyte = 0
	108	self.wr = -1
	109	self.is_repeat_start = 0
	110	self.state = 'FIND START'
	111	self.oldscl = 1
	112	self.oldsda = 1
	113	self.oldpins = [1, 1]
	114	self.pdu_start = None
	115	self.pdu_bits = 0
	116
	117	def metadata(self, key, value):
	118	if key == srd.SRD_CONF_SAMPLERATE:
	119	self.samplerate = value
	120
	121	def start(self):
	122	self.out_proto = self.register(srd.OUTPUT_PYTHON)
	123	self.out_ann = self.register(srd.OUTPUT_ANN)
	124	self.out_binary = self.register(srd.OUTPUT_BINARY)
	125	self.out_bitrate = self.register(srd.OUTPUT_META,
	126	meta=(int, 'Bitrate', 'Bitrate from Start bit to Stop bit'))
	127
	128	def putx(self, data):
	129	self.put(self.startsample, self.samplenum, self.out_ann, data)
	130
	131	def putp(self, data):
	132	self.put(self.startsample, self.samplenum, self.out_proto, data)
	133
	134	def putb(self, data):
	135	self.put(self.startsample, self.samplenum, self.out_binary, data)
	136
	137	def is_start_condition(self, scl, sda):
	138	# START condition (S): SDA = falling, SCL = high
	139	if (self.oldsda == 1 and sda == 0) and scl == 1:
	140	return True
	141	return False
	142
	143	def is_data_bit(self, scl, sda):
	144	# Data sampling of receiver: SCL = rising
	145	if self.oldscl == 0 and scl == 1:
	146	return True
	147	return False
	148
	149	def is_stop_condition(self, scl, sda):
	150	# STOP condition (P): SDA = rising, SCL = high
	151	if (self.oldsda == 0 and sda == 1) and scl == 1:
	152	return True
	153	return False
	154
	155	def found_start(self, scl, sda):
	156	self.startsample = self.samplenum
	157	self.pdu_start = self.samplenum
	158	self.pdu_bits = 0
	159	cmd = 'START REPEAT' if (self.is_repeat_start == 1) else 'START'
	160	self.putp([cmd, None])
	161	self.putx([proto[cmd][0], proto[cmd][1:]])
	162	self.state = 'FIND ADDRESS'
	163	self.bitcount = self.databyte = 0
	164	self.is_repeat_start = 1
	165	self.wr = -1
	166
	167	# Gather 8 bits of data plus the ACK/NACK bit.
	168	def found_address_or_data(self, scl, sda):
	169	# Address and data are transmitted MSB-first.
	170	self.databyte <<= 1
	171	self.databyte \|= sda
	172
	173	if self.bitcount == 0:
	174	self.startsample = self.samplenum
	175
	176	# Return if we haven't collected all 8 + 1 bits, yet.
	177	self.bitcount += 1
	178	if self.bitcount != 8:
	179	return
	180
	181	# We triggered on the ACK/NACK bit, but won't report that until later.
	182	self.startsample -= 1
	183
	184	d = self.databyte
	185	if self.state == 'FIND ADDRESS':
	186	# The READ/WRITE bit is only in address bytes, not data bytes.
	187	self.wr = 0 if (self.databyte & 1) else 1
	188	if self.options['address_format'] == 'shifted':
	189	d = d >> 1
	190
	191	bin_class = -1
	192	if self.state == 'FIND ADDRESS' and self.wr == 1:
	193	cmd = 'ADDRESS WRITE'
	194	bin_class = 1
	195	elif self.state == 'FIND ADDRESS' and self.wr == 0:
	196	cmd = 'ADDRESS READ'
	197	bin_class = 0
	198	elif self.state == 'FIND DATA' and self.wr == 1:
	199	cmd = 'DATA WRITE'
	200	bin_class = 3
	201	elif self.state == 'FIND DATA' and self.wr == 0:
	202	cmd = 'DATA READ'
	203	bin_class = 2
	204
	205	self.putp([cmd, d])
	206	self.putx([proto[cmd][0], ['%s: %02X' % (proto[cmd][1], d),
	207	'%s: %02X' % (proto[cmd][2], d), '%02X' % d]])
	208	self.putb((bin_class, bytes([d])))
	209
	210	# Done with this packet.
	211	self.startsample = -1
	212	self.bitcount = self.databyte = 0
	213	self.state = 'FIND ACK'
	214
	215	def get_ack(self, scl, sda):
	216	self.startsample = self.samplenum
	217	cmd = 'NACK' if (sda == 1) else 'ACK'
	218	self.putp([cmd, None])
	219	self.putx([proto[cmd][0], proto[cmd][1:]])
	220	# There could be multiple data bytes in a row, so either find
	221	# another data byte or a STOP condition next.
	222	self.state = 'FIND DATA'
	223
	224	def found_stop(self, scl, sda):
	225	# Meta bitrate
	226	elapsed = 1 / float(self.samplerate) * (self.samplenum - self.pdu_start + 1)
	227	bitrate = int(1 / elapsed * self.pdu_bits)
	228	self.put(self.startsample, self.samplenum, self.out_bitrate, bitrate)
	229
	230	self.startsample = self.samplenum
	231	cmd = 'STOP'
	232	self.putp([cmd, None])
	233	self.putx([proto[cmd][0], proto[cmd][1:]])
	234	self.state = 'FIND START'
	235	self.is_repeat_start = 0
	236	self.wr = -1
	237
	238	def decode(self, ss, es, data):
	239	if self.samplerate is None:
	240	raise Exception("Cannot decode without samplerate.")
	241	for (self.samplenum, pins) in data:
	242
	243	# Ignore identical samples early on (for performance reasons).
	244	if self.oldpins == pins:
	245	continue
	246	self.oldpins, (scl, sda) = pins, pins
	247
	248	self.pdu_bits += 1
	249
	250	# TODO: Wait until the bus is idle (SDA = SCL = 1) first?
	251
	252	# State machine.
	253	if self.state == 'FIND START':
	254	if self.is_start_condition(scl, sda):
	255	self.found_start(scl, sda)
	256	elif self.state == 'FIND ADDRESS':
	257	if self.is_data_bit(scl, sda):
	258	self.found_address_or_data(scl, sda)
	259	elif self.state == 'FIND DATA':
	260	if self.is_data_bit(scl, sda):
	261	self.found_address_or_data(scl, sda)
	262	elif self.is_start_condition(scl, sda):
	263	self.found_start(scl, sda)
	264	elif self.is_stop_condition(scl, sda):
	265	self.found_stop(scl, sda)
	266	elif self.state == 'FIND ACK':
	267	if self.is_data_bit(scl, sda):
	268	self.get_ack(scl, sda)
	269	else:
	270	raise Exception('Invalid state: %s' % self.state)
	271
	272	# Save current SDA/SCL values for the next round.
	273	self.oldscl = scl
	274	self.oldsda = sda
	275