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Commit | Line | Data |
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1b1c914f | 1 | ## |
50bd5d25 | 2 | ## This file is part of the libsigrokdecode project. |
1b1c914f | 3 | ## |
1be94d3d | 4 | ## Copyright (C) 2011-2016 Uwe Hermann <uwe@hermann-uwe.de> |
1b1c914f UH |
5 | ## |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
4539e9ca | 17 | ## along with this program; if not, see <http://www.gnu.org/licenses/>. |
1b1c914f UH |
18 | ## |
19 | ||
677d597b | 20 | import sigrokdecode as srd |
c2446117 | 21 | from .lists import * |
1b1c914f | 22 | |
1be94d3d UH |
23 | L = len(cmds) |
24 | ||
25 | # Don't forget to keep this in sync with 'cmds' is lists.py. | |
26 | class Ann: | |
27 | WRSR, PP, READ, WRDI, RDSR, WREN, FAST_READ, SE, RDSCUR, WRSCUR, \ | |
8a73c6c7 AA |
28 | RDSR2, CE, ESRY, DSRY, WRITE1, WRITE2, REMS, RDID, RDP_RES, CP, ENSO, DP, \ |
29 | READ2X, EXSO, CE2, STATUS, BE, REMS2, \ | |
1be94d3d UH |
30 | BIT, FIELD, WARN = range(L + 3) |
31 | ||
9389f2c1 | 32 | def cmd_annotation_classes(): |
da9bcbd9 | 33 | return tuple([tuple([cmd[0].lower(), cmd[1]]) for cmd in cmds.values()]) |
9389f2c1 | 34 | |
10d3c8dc AG |
35 | def decode_dual_bytes(sio0, sio1): |
36 | # Given a byte in SIO0 (MOSI) of even bits and a byte in | |
37 | # SIO1 (MISO) of odd bits, return a tuple of two bytes. | |
38 | def combine_byte(even, odd): | |
39 | result = 0 | |
40 | for bit in range(4): | |
41 | if even & (1 << bit): | |
42 | result |= 1 << (bit*2) | |
43 | if odd & (1 << bit): | |
44 | result |= 1 << ((bit*2) + 1) | |
45 | return result | |
46 | return (combine_byte(sio0 >> 4, sio1 >> 4), combine_byte(sio0, sio1)) | |
47 | ||
7cfbf663 UH |
48 | def decode_status_reg(data): |
49 | # TODO: Additional per-bit(s) self.put() calls with correct start/end. | |
50 | ||
51 | # Bits[0:0]: WIP (write in progress) | |
52 | s = 'W' if (data & (1 << 0)) else 'No w' | |
53 | ret = '%srite operation in progress.\n' % s | |
54 | ||
55 | # Bits[1:1]: WEL (write enable latch) | |
56 | s = '' if (data & (1 << 1)) else 'not ' | |
57 | ret += 'Internal write enable latch is %sset.\n' % s | |
58 | ||
59 | # Bits[5:2]: Block protect bits | |
60 | # TODO: More detailed decoding (chip-dependent). | |
61 | ret += 'Block protection bits (BP3-BP0): 0x%x.\n' % ((data & 0x3c) >> 2) | |
62 | ||
63 | # Bits[6:6]: Continuously program mode (CP mode) | |
64 | s = '' if (data & (1 << 6)) else 'not ' | |
65 | ret += 'Device is %sin continuously program mode (CP mode).\n' % s | |
66 | ||
67 | # Bits[7:7]: SRWD (status register write disable) | |
cd287c56 | 68 | s = 'not ' if (data & (1 << 7)) else '' |
7cfbf663 UH |
69 | ret += 'Status register writes are %sallowed.\n' % s |
70 | ||
71 | return ret | |
72 | ||
677d597b | 73 | class Decoder(srd.Decoder): |
b197383c | 74 | api_version = 3 |
3ca1f1b3 UH |
75 | id = 'spiflash' |
76 | name = 'SPI flash' | |
77 | longname = 'SPI flash chips' | |
78 | desc = 'xx25 series SPI (NOR) flash chip protocol.' | |
1b1c914f | 79 | license = 'gplv2+' |
a1497fa3 | 80 | inputs = ['spi'] |
3ca1f1b3 | 81 | outputs = ['spiflash'] |
da9bcbd9 | 82 | annotations = cmd_annotation_classes() + ( |
1be94d3d UH |
83 | ('bit', 'Bit'), |
84 | ('field', 'Field'), | |
85 | ('warning', 'Warning'), | |
da9bcbd9 | 86 | ) |
9ed42038 | 87 | annotation_rows = ( |
1be94d3d UH |
88 | ('bits', 'Bits', (L + 0,)), |
89 | ('fields', 'Fields', (L + 1,)), | |
90 | ('commands', 'Commands', tuple(range(len(cmds)))), | |
91 | ('warnings', 'Warnings', (L + 2,)), | |
9ed42038 | 92 | ) |
c2446117 UH |
93 | options = ( |
94 | {'id': 'chip', 'desc': 'Chip', 'default': tuple(chips.keys())[0], | |
95 | 'values': tuple(chips.keys())}, | |
b33a73bc UH |
96 | {'id': 'format', 'desc': 'Data format', 'default': 'hex', |
97 | 'values': ('hex', 'ascii')}, | |
c2446117 | 98 | ) |
1b1c914f | 99 | |
92b7b49f | 100 | def __init__(self): |
10aeb8ea GS |
101 | self.reset() |
102 | ||
103 | def reset(self): | |
db188228 | 104 | self.device_id = -1 |
2c920167 AG |
105 | self.on_end_transaction = None |
106 | self.end_current_transaction() | |
539e6daf | 107 | self.writestate = 0 |
2c920167 | 108 | |
1ec9c5e2 AG |
109 | # Build dict mapping command keys to handler functions. Each |
110 | # command in 'cmds' (defined in lists.py) has a matching | |
111 | # handler self.handle_<shortname>. | |
112 | def get_handler(cmd): | |
113 | s = 'handle_%s' % cmds[cmd][0].lower().replace('/', '_') | |
114 | return getattr(self, s) | |
115 | self.cmd_handlers = dict((cmd, get_handler(cmd)) for cmd in cmds.keys()) | |
116 | ||
2c920167 AG |
117 | def end_current_transaction(self): |
118 | if self.on_end_transaction is not None: # Callback for CS# transition. | |
119 | self.on_end_transaction() | |
120 | self.on_end_transaction = None | |
4772a846 | 121 | self.state = None |
781ef945 | 122 | self.cmdstate = 1 |
e4022299 UH |
123 | self.addr = 0 |
124 | self.data = [] | |
1b1c914f | 125 | |
8915b346 | 126 | def start(self): |
be465111 | 127 | self.out_ann = self.register(srd.OUTPUT_ANN) |
c2446117 | 128 | self.chip = chips[self.options['chip']] |
db188228 | 129 | self.vendor = self.options['chip'].split('_')[0] |
1b1c914f | 130 | |
385508e9 | 131 | def putx(self, data): |
ee3e279c | 132 | # Simplification, most annotations span exactly one SPI byte/packet. |
9b4d8a57 UH |
133 | self.put(self.ss, self.es, self.out_ann, data) |
134 | ||
de22de7f UH |
135 | def putf(self, data): |
136 | self.put(self.ss_field, self.es_field, self.out_ann, data) | |
137 | ||
138 | def putc(self, data): | |
139 | self.put(self.ss_cmd, self.es_cmd, self.out_ann, data) | |
140 | ||
141 | def device(self): | |
142 | return device_name[self.vendor].get(self.device_id, 'Unknown') | |
7c139a54 | 143 | |
db188228 | 144 | def vendor_device(self): |
de22de7f UH |
145 | return '%s %s' % (self.chip['vendor'], self.device()) |
146 | ||
147 | def cmd_ann_list(self): | |
148 | x, s = cmds[self.state][0], cmds[self.state][1] | |
149 | return ['Command: %s (%s)' % (s, x), 'Command: %s' % s, | |
150 | 'Cmd: %s' % s, 'Cmd: %s' % x, x] | |
151 | ||
152 | def cmd_vendor_dev_list(self): | |
153 | c, d = cmds[self.state], 'Device = %s' % self.vendor_device() | |
154 | return ['%s (%s): %s' % (c[1], c[0], d), '%s: %s' % (c[1], d), | |
155 | '%s: %s' % (c[0], d), d, self.vendor_device()] | |
156 | ||
157 | def emit_cmd_byte(self): | |
158 | self.ss_cmd = self.ss | |
159 | self.putx([Ann.FIELD, self.cmd_ann_list()]) | |
160 | self.addr = 0 | |
161 | ||
162 | def emit_addr_bytes(self, mosi): | |
163 | self.addr |= (mosi << ((4 - self.cmdstate) * 8)) | |
164 | b = ((3 - (self.cmdstate - 2)) * 8) - 1 | |
165 | self.putx([Ann.BIT, | |
166 | ['Address bits %d..%d: 0x%02x' % (b, b - 7, mosi), | |
167 | 'Addr bits %d..%d: 0x%02x' % (b, b - 7, mosi), | |
168 | 'Addr bits %d..%d' % (b, b - 7), 'A%d..A%d' % (b, b - 7)]]) | |
169 | if self.cmdstate == 2: | |
170 | self.ss_field = self.ss | |
171 | if self.cmdstate == 4: | |
172 | self.es_field = self.es | |
173 | self.putf([Ann.FIELD, ['Address: 0x%06x' % self.addr, | |
174 | 'Addr: 0x%06x' % self.addr, '0x%06x' % self.addr]]) | |
db188228 | 175 | |
9b4d8a57 | 176 | def handle_wren(self, mosi, miso): |
de22de7f | 177 | self.putx([Ann.WREN, self.cmd_ann_list()]) |
539e6daf | 178 | self.writestate = 1 |
1b1c914f | 179 | |
b54936a9 | 180 | def handle_wrdi(self, mosi, miso): |
539e6daf VPP |
181 | self.putx([Ann.WRDI, self.cmd_ann_list()]) |
182 | self.writestate = 0 | |
b54936a9 | 183 | |
9b4d8a57 | 184 | def handle_rdid(self, mosi, miso): |
1b1c914f UH |
185 | if self.cmdstate == 1: |
186 | # Byte 1: Master sends command ID. | |
de22de7f | 187 | self.emit_cmd_byte() |
1b1c914f UH |
188 | elif self.cmdstate == 2: |
189 | # Byte 2: Slave sends the JEDEC manufacturer ID. | |
de22de7f | 190 | self.putx([Ann.FIELD, ['Manufacturer ID: 0x%02x' % miso]]) |
1b1c914f | 191 | elif self.cmdstate == 3: |
de22de7f UH |
192 | # Byte 3: Slave sends the memory type. |
193 | self.putx([Ann.FIELD, ['Memory type: 0x%02x' % miso]]) | |
1b1c914f UH |
194 | elif self.cmdstate == 4: |
195 | # Byte 4: Slave sends the device ID. | |
9b4d8a57 | 196 | self.device_id = miso |
de22de7f | 197 | self.putx([Ann.FIELD, ['Device ID: 0x%02x' % miso]]) |
1b1c914f UH |
198 | |
199 | if self.cmdstate == 4: | |
de22de7f UH |
200 | self.es_cmd = self.es |
201 | self.putc([Ann.RDID, self.cmd_vendor_dev_list()]) | |
4772a846 | 202 | self.state = None |
1b1c914f UH |
203 | else: |
204 | self.cmdstate += 1 | |
205 | ||
b54936a9 UH |
206 | def handle_rdsr(self, mosi, miso): |
207 | # Read status register: Master asserts CS#, sends RDSR command, | |
208 | # reads status register byte. If CS# is kept asserted, the status | |
209 | # register can be read continuously / multiple times in a row. | |
210 | # When done, the master de-asserts CS# again. | |
211 | if self.cmdstate == 1: | |
212 | # Byte 1: Master sends command ID. | |
de22de7f | 213 | self.emit_cmd_byte() |
b54936a9 UH |
214 | elif self.cmdstate >= 2: |
215 | # Bytes 2-x: Slave sends status register as long as master clocks. | |
de22de7f UH |
216 | self.es_cmd = self.es |
217 | self.putx([Ann.BIT, [decode_status_reg(miso)]]) | |
218 | self.putx([Ann.FIELD, ['Status register']]) | |
219 | self.putc([Ann.RDSR, self.cmd_ann_list()]) | |
bb2cda30 VPP |
220 | # Set write latch state. |
221 | self.writestate = 1 if (miso & (1 << 1)) else 0 | |
b54936a9 UH |
222 | self.cmdstate += 1 |
223 | ||
6ccb64fe UH |
224 | def handle_rdsr2(self, mosi, miso): |
225 | # Read status register 2: Master asserts CS#, sends RDSR2 command, | |
226 | # reads status register 2 byte. If CS# is kept asserted, the status | |
227 | # register 2 can be read continuously / multiple times in a row. | |
228 | # When done, the master de-asserts CS# again. | |
229 | if self.cmdstate == 1: | |
230 | # Byte 1: Master sends command ID. | |
de22de7f | 231 | self.emit_cmd_byte() |
6ccb64fe UH |
232 | elif self.cmdstate >= 2: |
233 | # Bytes 2-x: Slave sends status register 2 as long as master clocks. | |
de22de7f UH |
234 | self.es_cmd = self.es |
235 | # TODO: Decode status register 2 correctly. | |
236 | self.putx([Ann.BIT, [decode_status_reg(miso)]]) | |
237 | self.putx([Ann.FIELD, ['Status register 2']]) | |
238 | self.putc([Ann.RDSR2, self.cmd_ann_list()]) | |
6ccb64fe UH |
239 | self.cmdstate += 1 |
240 | ||
b54936a9 | 241 | def handle_wrsr(self, mosi, miso): |
0a89f2ae UH |
242 | # Write status register: Master asserts CS#, sends WRSR command, |
243 | # writes 1 or 2 status register byte(s). | |
244 | # When done, the master de-asserts CS# again. If this doesn't happen | |
245 | # the WRSR command will not be executed. | |
246 | if self.cmdstate == 1: | |
247 | # Byte 1: Master sends command ID. | |
de22de7f UH |
248 | self.emit_cmd_byte() |
249 | elif self.cmdstate == 2: | |
250 | # Byte 2: Master sends status register 1. | |
2e3e0840 | 251 | self.putx([Ann.BIT, [decode_status_reg(mosi)]]) |
de22de7f | 252 | self.putx([Ann.FIELD, ['Status register 1']]) |
bb2cda30 VPP |
253 | # Set write latch state. |
254 | self.writestate = 1 if (miso & (1 << 1)) else 0 | |
de22de7f UH |
255 | elif self.cmdstate == 3: |
256 | # Byte 3: Master sends status register 2. | |
257 | # TODO: Decode status register 2 correctly. | |
2e3e0840 | 258 | self.putx([Ann.BIT, [decode_status_reg(mosi)]]) |
de22de7f UH |
259 | self.putx([Ann.FIELD, ['Status register 2']]) |
260 | self.es_cmd = self.es | |
261 | self.putc([Ann.WRSR, self.cmd_ann_list()]) | |
0a89f2ae | 262 | self.cmdstate += 1 |
b54936a9 UH |
263 | |
264 | def handle_read(self, mosi, miso): | |
265 | # Read data bytes: Master asserts CS#, sends READ command, sends | |
266 | # 3-byte address, reads >= 1 data bytes, de-asserts CS#. | |
267 | if self.cmdstate == 1: | |
268 | # Byte 1: Master sends command ID. | |
de22de7f | 269 | self.emit_cmd_byte() |
b54936a9 UH |
270 | elif self.cmdstate in (2, 3, 4): |
271 | # Bytes 2/3/4: Master sends read address (24bits, MSB-first). | |
de22de7f | 272 | self.emit_addr_bytes(mosi) |
b54936a9 UH |
273 | elif self.cmdstate >= 5: |
274 | # Bytes 5-x: Master reads data bytes (until CS# de-asserted). | |
de22de7f | 275 | self.es_field = self.es # Will be overwritten for each byte. |
2c920167 | 276 | if self.cmdstate == 5: |
de22de7f UH |
277 | self.ss_field = self.ss |
278 | self.on_end_transaction = lambda: self.output_data_block('Data', Ann.READ) | |
2c920167 | 279 | self.data.append(miso) |
b54936a9 UH |
280 | self.cmdstate += 1 |
281 | ||
8a73c6c7 AA |
282 | def handle_write_common(self, mosi, miso, ann): |
283 | # Write data bytes: Master asserts CS#, sends WRITE command, sends | |
284 | # 3-byte address, writes >= 1 data bytes, de-asserts CS#. | |
285 | if self.cmdstate == 1: | |
286 | # Byte 1: Master sends command ID. | |
287 | self.emit_cmd_byte() | |
539e6daf VPP |
288 | if self.writestate == 0: |
289 | self.putc([Ann.WARN, ['Warning: WREN might be missing']]) | |
8a73c6c7 AA |
290 | elif self.cmdstate in (2, 3, 4): |
291 | # Bytes 2/3/4: Master sends write address (24bits, MSB-first). | |
292 | self.emit_addr_bytes(mosi) | |
293 | elif self.cmdstate >= 5: | |
294 | # Bytes 5-x: Master writes data bytes (until CS# de-asserted). | |
295 | self.es_field = self.es # Will be overwritten for each byte. | |
296 | if self.cmdstate == 5: | |
297 | self.ss_field = self.ss | |
298 | self.on_end_transaction = lambda: self.output_data_block('Data', ann) | |
299 | self.data.append(mosi) | |
300 | self.cmdstate += 1 | |
301 | ||
302 | def handle_write1(self, mosi, miso): | |
303 | self.handle_write_common(mosi, miso, Ann.WRITE1) | |
304 | ||
305 | def handle_write2(self, mosi, miso): | |
306 | self.handle_write_common(mosi, miso, Ann.WRITE2) | |
307 | ||
b54936a9 | 308 | def handle_fast_read(self, mosi, miso): |
7c139a54 UH |
309 | # Fast read: Master asserts CS#, sends FAST READ command, sends |
310 | # 3-byte address + 1 dummy byte, reads >= 1 data bytes, de-asserts CS#. | |
311 | if self.cmdstate == 1: | |
312 | # Byte 1: Master sends command ID. | |
de22de7f | 313 | self.emit_cmd_byte() |
7c139a54 | 314 | elif self.cmdstate in (2, 3, 4): |
de22de7f UH |
315 | # Bytes 2/3/4: Master sends read address (24bits, MSB-first). |
316 | self.emit_addr_bytes(mosi) | |
7c139a54 | 317 | elif self.cmdstate == 5: |
1be94d3d | 318 | self.putx([Ann.BIT, ['Dummy byte: 0x%02x' % mosi]]) |
7c139a54 UH |
319 | elif self.cmdstate >= 6: |
320 | # Bytes 6-x: Master reads data bytes (until CS# de-asserted). | |
de22de7f | 321 | self.es_field = self.es # Will be overwritten for each byte. |
7c139a54 | 322 | if self.cmdstate == 6: |
de22de7f UH |
323 | self.ss_field = self.ss |
324 | self.on_end_transaction = lambda: self.output_data_block('Data', Ann.FAST_READ) | |
2c920167 | 325 | self.data.append(miso) |
7c139a54 | 326 | self.cmdstate += 1 |
b54936a9 UH |
327 | |
328 | def handle_2read(self, mosi, miso): | |
de22de7f UH |
329 | # 2x I/O read (fast read dual I/O): Master asserts CS#, sends 2READ |
330 | # command, sends 3-byte address + 1 dummy byte, reads >= 1 data bytes, | |
331 | # de-asserts CS#. All data after the command is sent via two I/O pins. | |
10d3c8dc | 332 | # MOSI = SIO0 = even bits, MISO = SIO1 = odd bits. |
de22de7f UH |
333 | if self.cmdstate != 1: |
334 | b1, b2 = decode_dual_bytes(mosi, miso) | |
10d3c8dc AG |
335 | if self.cmdstate == 1: |
336 | # Byte 1: Master sends command ID. | |
de22de7f UH |
337 | self.emit_cmd_byte() |
338 | elif self.cmdstate == 2: | |
339 | # Bytes 2/3(/4): Master sends read address (24bits, MSB-first). | |
340 | # Handle bytes 2 and 3 here. | |
341 | self.emit_addr_bytes(b1) | |
342 | self.cmdstate = 3 | |
343 | self.emit_addr_bytes(b2) | |
344 | elif self.cmdstate == 4: | |
345 | # Byte 5: Dummy byte. Also handle byte 4 (address LSB) here. | |
346 | self.emit_addr_bytes(b1) | |
347 | self.cmdstate = 5 | |
348 | self.putx([Ann.BIT, ['Dummy byte: 0x%02x' % b2]]) | |
349 | elif self.cmdstate >= 6: | |
350 | # Bytes 6-x: Master reads data bytes (until CS# de-asserted). | |
351 | self.es_field = self.es # Will be overwritten for each byte. | |
352 | if self.cmdstate == 6: | |
353 | self.ss_field = self.ss | |
354 | self.on_end_transaction = lambda: self.output_data_block('Data', Ann.READ2X) | |
355 | self.data.append(b1) | |
356 | self.data.append(b2) | |
357 | self.cmdstate += 1 | |
b54936a9 | 358 | |
8a73c6c7 AA |
359 | def handle_status(self, mosi, miso): |
360 | if self.cmdstate == 1: | |
361 | # Byte 1: Master sends command ID. | |
362 | self.emit_cmd_byte() | |
363 | self.on_end_transaction = lambda: self.putc([Ann.STATUS, [cmds[self.state][1]]]) | |
364 | else: | |
365 | # Will be overwritten for each byte. | |
366 | self.es_cmd = self.es | |
367 | self.es_field = self.es | |
368 | if self.cmdstate == 2: | |
369 | self.ss_field = self.ss | |
370 | self.putx([Ann.BIT, ['Status register byte %d: 0x%02x' % ((self.cmdstate % 2) + 1, miso)]]) | |
371 | self.cmdstate += 1 | |
372 | ||
1b1c914f | 373 | # TODO: Warn/abort if we don't see the necessary amount of bytes. |
9b4d8a57 | 374 | def handle_se(self, mosi, miso): |
1b1c914f UH |
375 | if self.cmdstate == 1: |
376 | # Byte 1: Master sends command ID. | |
de22de7f | 377 | self.emit_cmd_byte() |
539e6daf VPP |
378 | if self.writestate == 0: |
379 | self.putx([Ann.WARN, ['Warning: WREN might be missing']]) | |
1b1c914f | 380 | elif self.cmdstate in (2, 3, 4): |
868fd207 | 381 | # Bytes 2/3/4: Master sends sector address (24bits, MSB-first). |
de22de7f | 382 | self.emit_addr_bytes(mosi) |
1b1c914f UH |
383 | |
384 | if self.cmdstate == 4: | |
de22de7f | 385 | self.es_cmd = self.es |
87e574b7 | 386 | d = 'Erase sector %d (0x%06x)' % (self.addr, self.addr) |
de22de7f | 387 | self.putc([Ann.SE, [d]]) |
1b1c914f UH |
388 | # TODO: Max. size depends on chip, check that too if possible. |
389 | if self.addr % 4096 != 0: | |
390 | # Sector addresses must be 4K-aligned (same for all 3 chips). | |
de22de7f | 391 | self.putc([Ann.WARN, ['Warning: Invalid sector address!']]) |
4772a846 | 392 | self.state = None |
1b1c914f UH |
393 | else: |
394 | self.cmdstate += 1 | |
395 | ||
b54936a9 UH |
396 | def handle_be(self, mosi, miso): |
397 | pass # TODO | |
398 | ||
399 | def handle_ce(self, mosi, miso): | |
51a91ed0 | 400 | self.putx([Ann.CE, self.cmd_ann_list()]) |
539e6daf VPP |
401 | if self.writestate == 0: |
402 | self.putx([Ann.WARN, ['Warning: WREN might be missing']]) | |
b54936a9 UH |
403 | |
404 | def handle_ce2(self, mosi, miso): | |
51a91ed0 | 405 | self.putx([Ann.CE2, self.cmd_ann_list()]) |
539e6daf VPP |
406 | if self.writestate == 0: |
407 | self.putx([Ann.WARN, ['Warning: WREN might be missing']]) | |
b54936a9 UH |
408 | |
409 | def handle_pp(self, mosi, miso): | |
410 | # Page program: Master asserts CS#, sends PP command, sends 3-byte | |
411 | # page address, sends >= 1 data bytes, de-asserts CS#. | |
412 | if self.cmdstate == 1: | |
413 | # Byte 1: Master sends command ID. | |
de22de7f | 414 | self.emit_cmd_byte() |
b54936a9 UH |
415 | elif self.cmdstate in (2, 3, 4): |
416 | # Bytes 2/3/4: Master sends page address (24bits, MSB-first). | |
de22de7f | 417 | self.emit_addr_bytes(mosi) |
b54936a9 UH |
418 | elif self.cmdstate >= 5: |
419 | # Bytes 5-x: Master sends data bytes (until CS# de-asserted). | |
de22de7f | 420 | self.es_field = self.es # Will be overwritten for each byte. |
2c920167 | 421 | if self.cmdstate == 5: |
de22de7f UH |
422 | self.ss_field = self.ss |
423 | self.on_end_transaction = lambda: self.output_data_block('Data', Ann.PP) | |
2c920167 | 424 | self.data.append(mosi) |
b54936a9 UH |
425 | self.cmdstate += 1 |
426 | ||
427 | def handle_cp(self, mosi, miso): | |
428 | pass # TODO | |
429 | ||
430 | def handle_dp(self, mosi, miso): | |
431 | pass # TODO | |
432 | ||
433 | def handle_rdp_res(self, mosi, miso): | |
e33410d3 UH |
434 | if self.cmdstate == 1: |
435 | # Byte 1: Master sends command ID. | |
de22de7f | 436 | self.emit_cmd_byte() |
e33410d3 UH |
437 | elif self.cmdstate in (2, 3, 4): |
438 | # Bytes 2/3/4: Master sends three dummy bytes. | |
de22de7f | 439 | self.putx([Ann.FIELD, ['Dummy byte: %02x' % mosi]]) |
e33410d3 UH |
440 | elif self.cmdstate == 5: |
441 | # Byte 5: Slave sends device ID. | |
de22de7f | 442 | self.es_cmd = self.es |
db188228 | 443 | self.device_id = miso |
de22de7f UH |
444 | self.putx([Ann.FIELD, ['Device ID: %s' % self.device()]]) |
445 | d = 'Device = %s' % self.vendor_device() | |
446 | self.putc([Ann.RDP_RES, self.cmd_vendor_dev_list()]) | |
e33410d3 | 447 | self.state = None |
e33410d3 | 448 | self.cmdstate += 1 |
b54936a9 | 449 | |
9b4d8a57 | 450 | def handle_rems(self, mosi, miso): |
1b1c914f UH |
451 | if self.cmdstate == 1: |
452 | # Byte 1: Master sends command ID. | |
de22de7f | 453 | self.emit_cmd_byte() |
1b1c914f UH |
454 | elif self.cmdstate in (2, 3): |
455 | # Bytes 2/3: Master sends two dummy bytes. | |
de22de7f | 456 | self.putx([Ann.FIELD, ['Dummy byte: 0x%02x' % mosi]]) |
1b1c914f UH |
457 | elif self.cmdstate == 4: |
458 | # Byte 4: Master sends 0x00 or 0x01. | |
459 | # 0x00: Master wants manufacturer ID as first reply byte. | |
460 | # 0x01: Master wants device ID as first reply byte. | |
9b4d8a57 UH |
461 | self.manufacturer_id_first = True if (mosi == 0x00) else False |
462 | d = 'manufacturer' if (mosi == 0x00) else 'device' | |
de22de7f | 463 | self.putx([Ann.FIELD, ['Master wants %s ID first' % d]]) |
1b1c914f UH |
464 | elif self.cmdstate == 5: |
465 | # Byte 5: Slave sends manufacturer ID (or device ID). | |
9b4d8a57 UH |
466 | self.ids = [miso] |
467 | d = 'Manufacturer' if self.manufacturer_id_first else 'Device' | |
de22de7f | 468 | self.putx([Ann.FIELD, ['%s ID: 0x%02x' % (d, miso)]]) |
9b4d8a57 | 469 | elif self.cmdstate == 6: |
1b1c914f | 470 | # Byte 6: Slave sends device ID (or manufacturer ID). |
7f7ea759 | 471 | self.ids.append(miso) |
de22de7f UH |
472 | d = 'Device' if self.manufacturer_id_first else 'Manufacturer' |
473 | self.putx([Ann.FIELD, ['%s ID: 0x%02x' % (d, miso)]]) | |
1b1c914f UH |
474 | |
475 | if self.cmdstate == 6: | |
16d2031b RJ |
476 | id_ = self.ids[1] if self.manufacturer_id_first else self.ids[0] |
477 | self.device_id = id_ | |
de22de7f UH |
478 | self.es_cmd = self.es |
479 | self.putc([Ann.REMS, self.cmd_vendor_dev_list()]) | |
4772a846 | 480 | self.state = None |
1b1c914f UH |
481 | else: |
482 | self.cmdstate += 1 | |
483 | ||
b54936a9 UH |
484 | def handle_rems2(self, mosi, miso): |
485 | pass # TODO | |
e4022299 | 486 | |
b54936a9 UH |
487 | def handle_enso(self, mosi, miso): |
488 | pass # TODO | |
e4022299 | 489 | |
b54936a9 UH |
490 | def handle_exso(self, mosi, miso): |
491 | pass # TODO | |
e4022299 | 492 | |
b54936a9 UH |
493 | def handle_rdscur(self, mosi, miso): |
494 | pass # TODO | |
e4022299 | 495 | |
b54936a9 UH |
496 | def handle_wrscur(self, mosi, miso): |
497 | pass # TODO | |
e4022299 | 498 | |
b54936a9 UH |
499 | def handle_esry(self, mosi, miso): |
500 | pass # TODO | |
1b1c914f | 501 | |
b54936a9 UH |
502 | def handle_dsry(self, mosi, miso): |
503 | pass # TODO | |
5ebb76fe | 504 | |
de22de7f | 505 | def output_data_block(self, label, idx): |
2c920167 AG |
506 | # Print accumulated block of data |
507 | # (called on CS# de-assert via self.on_end_transaction callback). | |
de22de7f | 508 | self.es_cmd = self.es # End on the CS# de-assert sample. |
b33a73bc UH |
509 | if self.options['format'] == 'hex': |
510 | s = ' '.join([('%02x' % b) for b in self.data]) | |
511 | else: | |
512 | s = ''.join(map(chr, self.data)) | |
de22de7f UH |
513 | self.putf([Ann.FIELD, ['%s (%d bytes)' % (label, len(self.data))]]) |
514 | self.putc([idx, ['%s (addr 0x%06x, %d bytes): %s' % \ | |
515 | (cmds[self.state][1], self.addr, len(self.data), s)]]) | |
1b1c914f | 516 | |
2c920167 | 517 | def decode(self, ss, es, data): |
9b4d8a57 | 518 | ptype, mosi, miso = data |
1b1c914f | 519 | |
2c920167 | 520 | self.ss, self.es = ss, es |
e4022299 | 521 | |
2c920167 AG |
522 | if ptype == 'CS-CHANGE': |
523 | self.end_current_transaction() | |
e4022299 | 524 | |
3e3c0330 | 525 | if ptype != 'DATA': |
9b4d8a57 | 526 | return |
1b1c914f | 527 | |
9b4d8a57 | 528 | # If we encountered a known chip command, enter the resp. state. |
35b380b1 | 529 | if self.state is None: |
781ef945 UH |
530 | self.state = mosi |
531 | self.cmdstate = 1 | |
1b1c914f | 532 | |
9b4d8a57 | 533 | # Handle commands. |
1ec9c5e2 AG |
534 | try: |
535 | self.cmd_handlers[self.state](mosi, miso) | |
536 | except KeyError: | |
1be94d3d | 537 | self.putx([Ann.BIT, ['Unknown command: 0x%02x' % mosi]]) |
4772a846 | 538 | self.state = None |