]>
Commit | Line | Data |
---|---|---|
1b1c914f | 1 | ## |
50bd5d25 | 2 | ## This file is part of the libsigrokdecode project. |
1b1c914f | 3 | ## |
1be94d3d | 4 | ## Copyright (C) 2011-2016 Uwe Hermann <uwe@hermann-uwe.de> |
1b1c914f UH |
5 | ## |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
4539e9ca | 17 | ## along with this program; if not, see <http://www.gnu.org/licenses/>. |
1b1c914f UH |
18 | ## |
19 | ||
677d597b | 20 | import sigrokdecode as srd |
c2446117 | 21 | from .lists import * |
1b1c914f | 22 | |
1be94d3d UH |
23 | L = len(cmds) |
24 | ||
25 | # Don't forget to keep this in sync with 'cmds' is lists.py. | |
26 | class Ann: | |
27 | WRSR, PP, READ, WRDI, RDSR, WREN, FAST_READ, SE, RDSCUR, WRSCUR, \ | |
8a73c6c7 AA |
28 | RDSR2, CE, ESRY, DSRY, WRITE1, WRITE2, REMS, RDID, RDP_RES, CP, ENSO, DP, \ |
29 | READ2X, EXSO, CE2, STATUS, BE, REMS2, \ | |
1be94d3d UH |
30 | BIT, FIELD, WARN = range(L + 3) |
31 | ||
9389f2c1 | 32 | def cmd_annotation_classes(): |
da9bcbd9 | 33 | return tuple([tuple([cmd[0].lower(), cmd[1]]) for cmd in cmds.values()]) |
9389f2c1 | 34 | |
10d3c8dc AG |
35 | def decode_dual_bytes(sio0, sio1): |
36 | # Given a byte in SIO0 (MOSI) of even bits and a byte in | |
37 | # SIO1 (MISO) of odd bits, return a tuple of two bytes. | |
38 | def combine_byte(even, odd): | |
39 | result = 0 | |
40 | for bit in range(4): | |
41 | if even & (1 << bit): | |
42 | result |= 1 << (bit*2) | |
43 | if odd & (1 << bit): | |
44 | result |= 1 << ((bit*2) + 1) | |
45 | return result | |
46 | return (combine_byte(sio0 >> 4, sio1 >> 4), combine_byte(sio0, sio1)) | |
47 | ||
7cfbf663 UH |
48 | def decode_status_reg(data): |
49 | # TODO: Additional per-bit(s) self.put() calls with correct start/end. | |
50 | ||
51 | # Bits[0:0]: WIP (write in progress) | |
52 | s = 'W' if (data & (1 << 0)) else 'No w' | |
53 | ret = '%srite operation in progress.\n' % s | |
54 | ||
55 | # Bits[1:1]: WEL (write enable latch) | |
56 | s = '' if (data & (1 << 1)) else 'not ' | |
57 | ret += 'Internal write enable latch is %sset.\n' % s | |
58 | ||
59 | # Bits[5:2]: Block protect bits | |
60 | # TODO: More detailed decoding (chip-dependent). | |
61 | ret += 'Block protection bits (BP3-BP0): 0x%x.\n' % ((data & 0x3c) >> 2) | |
62 | ||
63 | # Bits[6:6]: Continuously program mode (CP mode) | |
64 | s = '' if (data & (1 << 6)) else 'not ' | |
65 | ret += 'Device is %sin continuously program mode (CP mode).\n' % s | |
66 | ||
67 | # Bits[7:7]: SRWD (status register write disable) | |
cd287c56 | 68 | s = 'not ' if (data & (1 << 7)) else '' |
7cfbf663 UH |
69 | ret += 'Status register writes are %sallowed.\n' % s |
70 | ||
71 | return ret | |
72 | ||
677d597b | 73 | class Decoder(srd.Decoder): |
b197383c | 74 | api_version = 3 |
3ca1f1b3 UH |
75 | id = 'spiflash' |
76 | name = 'SPI flash' | |
77 | longname = 'SPI flash chips' | |
78 | desc = 'xx25 series SPI (NOR) flash chip protocol.' | |
1b1c914f | 79 | license = 'gplv2+' |
a1497fa3 | 80 | inputs = ['spi'] |
3ca1f1b3 | 81 | outputs = ['spiflash'] |
da9bcbd9 | 82 | annotations = cmd_annotation_classes() + ( |
1be94d3d UH |
83 | ('bit', 'Bit'), |
84 | ('field', 'Field'), | |
85 | ('warning', 'Warning'), | |
da9bcbd9 | 86 | ) |
9ed42038 | 87 | annotation_rows = ( |
1be94d3d UH |
88 | ('bits', 'Bits', (L + 0,)), |
89 | ('fields', 'Fields', (L + 1,)), | |
90 | ('commands', 'Commands', tuple(range(len(cmds)))), | |
91 | ('warnings', 'Warnings', (L + 2,)), | |
9ed42038 | 92 | ) |
c2446117 UH |
93 | options = ( |
94 | {'id': 'chip', 'desc': 'Chip', 'default': tuple(chips.keys())[0], | |
95 | 'values': tuple(chips.keys())}, | |
b33a73bc UH |
96 | {'id': 'format', 'desc': 'Data format', 'default': 'hex', |
97 | 'values': ('hex', 'ascii')}, | |
c2446117 | 98 | ) |
1b1c914f | 99 | |
92b7b49f | 100 | def __init__(self): |
10aeb8ea GS |
101 | self.reset() |
102 | ||
103 | def reset(self): | |
db188228 | 104 | self.device_id = -1 |
2c920167 AG |
105 | self.on_end_transaction = None |
106 | self.end_current_transaction() | |
539e6daf | 107 | self.writestate = 0 |
2c920167 | 108 | |
1ec9c5e2 AG |
109 | # Build dict mapping command keys to handler functions. Each |
110 | # command in 'cmds' (defined in lists.py) has a matching | |
111 | # handler self.handle_<shortname>. | |
112 | def get_handler(cmd): | |
113 | s = 'handle_%s' % cmds[cmd][0].lower().replace('/', '_') | |
114 | return getattr(self, s) | |
115 | self.cmd_handlers = dict((cmd, get_handler(cmd)) for cmd in cmds.keys()) | |
116 | ||
2c920167 AG |
117 | def end_current_transaction(self): |
118 | if self.on_end_transaction is not None: # Callback for CS# transition. | |
119 | self.on_end_transaction() | |
120 | self.on_end_transaction = None | |
4772a846 | 121 | self.state = None |
781ef945 | 122 | self.cmdstate = 1 |
e4022299 UH |
123 | self.addr = 0 |
124 | self.data = [] | |
1b1c914f | 125 | |
8915b346 | 126 | def start(self): |
be465111 | 127 | self.out_ann = self.register(srd.OUTPUT_ANN) |
c2446117 | 128 | self.chip = chips[self.options['chip']] |
db188228 | 129 | self.vendor = self.options['chip'].split('_')[0] |
1b1c914f | 130 | |
385508e9 | 131 | def putx(self, data): |
ee3e279c | 132 | # Simplification, most annotations span exactly one SPI byte/packet. |
9b4d8a57 UH |
133 | self.put(self.ss, self.es, self.out_ann, data) |
134 | ||
de22de7f UH |
135 | def putf(self, data): |
136 | self.put(self.ss_field, self.es_field, self.out_ann, data) | |
137 | ||
138 | def putc(self, data): | |
139 | self.put(self.ss_cmd, self.es_cmd, self.out_ann, data) | |
140 | ||
141 | def device(self): | |
142 | return device_name[self.vendor].get(self.device_id, 'Unknown') | |
7c139a54 | 143 | |
db188228 | 144 | def vendor_device(self): |
de22de7f UH |
145 | return '%s %s' % (self.chip['vendor'], self.device()) |
146 | ||
147 | def cmd_ann_list(self): | |
148 | x, s = cmds[self.state][0], cmds[self.state][1] | |
149 | return ['Command: %s (%s)' % (s, x), 'Command: %s' % s, | |
150 | 'Cmd: %s' % s, 'Cmd: %s' % x, x] | |
151 | ||
152 | def cmd_vendor_dev_list(self): | |
153 | c, d = cmds[self.state], 'Device = %s' % self.vendor_device() | |
154 | return ['%s (%s): %s' % (c[1], c[0], d), '%s: %s' % (c[1], d), | |
155 | '%s: %s' % (c[0], d), d, self.vendor_device()] | |
156 | ||
157 | def emit_cmd_byte(self): | |
158 | self.ss_cmd = self.ss | |
159 | self.putx([Ann.FIELD, self.cmd_ann_list()]) | |
160 | self.addr = 0 | |
161 | ||
162 | def emit_addr_bytes(self, mosi): | |
163 | self.addr |= (mosi << ((4 - self.cmdstate) * 8)) | |
164 | b = ((3 - (self.cmdstate - 2)) * 8) - 1 | |
165 | self.putx([Ann.BIT, | |
166 | ['Address bits %d..%d: 0x%02x' % (b, b - 7, mosi), | |
167 | 'Addr bits %d..%d: 0x%02x' % (b, b - 7, mosi), | |
168 | 'Addr bits %d..%d' % (b, b - 7), 'A%d..A%d' % (b, b - 7)]]) | |
169 | if self.cmdstate == 2: | |
170 | self.ss_field = self.ss | |
171 | if self.cmdstate == 4: | |
172 | self.es_field = self.es | |
173 | self.putf([Ann.FIELD, ['Address: 0x%06x' % self.addr, | |
174 | 'Addr: 0x%06x' % self.addr, '0x%06x' % self.addr]]) | |
db188228 | 175 | |
9b4d8a57 | 176 | def handle_wren(self, mosi, miso): |
de22de7f | 177 | self.putx([Ann.WREN, self.cmd_ann_list()]) |
539e6daf | 178 | self.writestate = 1 |
1b1c914f | 179 | |
b54936a9 | 180 | def handle_wrdi(self, mosi, miso): |
539e6daf VPP |
181 | self.putx([Ann.WRDI, self.cmd_ann_list()]) |
182 | self.writestate = 0 | |
b54936a9 | 183 | |
9b4d8a57 | 184 | def handle_rdid(self, mosi, miso): |
1b1c914f UH |
185 | if self.cmdstate == 1: |
186 | # Byte 1: Master sends command ID. | |
de22de7f | 187 | self.emit_cmd_byte() |
1b1c914f UH |
188 | elif self.cmdstate == 2: |
189 | # Byte 2: Slave sends the JEDEC manufacturer ID. | |
de22de7f | 190 | self.putx([Ann.FIELD, ['Manufacturer ID: 0x%02x' % miso]]) |
1b1c914f | 191 | elif self.cmdstate == 3: |
de22de7f UH |
192 | # Byte 3: Slave sends the memory type. |
193 | self.putx([Ann.FIELD, ['Memory type: 0x%02x' % miso]]) | |
1b1c914f UH |
194 | elif self.cmdstate == 4: |
195 | # Byte 4: Slave sends the device ID. | |
9b4d8a57 | 196 | self.device_id = miso |
de22de7f | 197 | self.putx([Ann.FIELD, ['Device ID: 0x%02x' % miso]]) |
1b1c914f UH |
198 | |
199 | if self.cmdstate == 4: | |
de22de7f UH |
200 | self.es_cmd = self.es |
201 | self.putc([Ann.RDID, self.cmd_vendor_dev_list()]) | |
4772a846 | 202 | self.state = None |
1b1c914f UH |
203 | else: |
204 | self.cmdstate += 1 | |
205 | ||
b54936a9 UH |
206 | def handle_rdsr(self, mosi, miso): |
207 | # Read status register: Master asserts CS#, sends RDSR command, | |
208 | # reads status register byte. If CS# is kept asserted, the status | |
209 | # register can be read continuously / multiple times in a row. | |
210 | # When done, the master de-asserts CS# again. | |
211 | if self.cmdstate == 1: | |
212 | # Byte 1: Master sends command ID. | |
de22de7f | 213 | self.emit_cmd_byte() |
b54936a9 UH |
214 | elif self.cmdstate >= 2: |
215 | # Bytes 2-x: Slave sends status register as long as master clocks. | |
de22de7f UH |
216 | self.es_cmd = self.es |
217 | self.putx([Ann.BIT, [decode_status_reg(miso)]]) | |
218 | self.putx([Ann.FIELD, ['Status register']]) | |
219 | self.putc([Ann.RDSR, self.cmd_ann_list()]) | |
b54936a9 UH |
220 | self.cmdstate += 1 |
221 | ||
6ccb64fe UH |
222 | def handle_rdsr2(self, mosi, miso): |
223 | # Read status register 2: Master asserts CS#, sends RDSR2 command, | |
224 | # reads status register 2 byte. If CS# is kept asserted, the status | |
225 | # register 2 can be read continuously / multiple times in a row. | |
226 | # When done, the master de-asserts CS# again. | |
227 | if self.cmdstate == 1: | |
228 | # Byte 1: Master sends command ID. | |
de22de7f | 229 | self.emit_cmd_byte() |
6ccb64fe UH |
230 | elif self.cmdstate >= 2: |
231 | # Bytes 2-x: Slave sends status register 2 as long as master clocks. | |
de22de7f UH |
232 | self.es_cmd = self.es |
233 | # TODO: Decode status register 2 correctly. | |
234 | self.putx([Ann.BIT, [decode_status_reg(miso)]]) | |
235 | self.putx([Ann.FIELD, ['Status register 2']]) | |
236 | self.putc([Ann.RDSR2, self.cmd_ann_list()]) | |
6ccb64fe UH |
237 | self.cmdstate += 1 |
238 | ||
b54936a9 | 239 | def handle_wrsr(self, mosi, miso): |
0a89f2ae UH |
240 | # Write status register: Master asserts CS#, sends WRSR command, |
241 | # writes 1 or 2 status register byte(s). | |
242 | # When done, the master de-asserts CS# again. If this doesn't happen | |
243 | # the WRSR command will not be executed. | |
244 | if self.cmdstate == 1: | |
245 | # Byte 1: Master sends command ID. | |
de22de7f UH |
246 | self.emit_cmd_byte() |
247 | elif self.cmdstate == 2: | |
248 | # Byte 2: Master sends status register 1. | |
249 | self.putx([Ann.BIT, [decode_status_reg(miso)]]) | |
250 | self.putx([Ann.FIELD, ['Status register 1']]) | |
251 | elif self.cmdstate == 3: | |
252 | # Byte 3: Master sends status register 2. | |
253 | # TODO: Decode status register 2 correctly. | |
254 | self.putx([Ann.BIT, [decode_status_reg(miso)]]) | |
255 | self.putx([Ann.FIELD, ['Status register 2']]) | |
256 | self.es_cmd = self.es | |
257 | self.putc([Ann.WRSR, self.cmd_ann_list()]) | |
0a89f2ae | 258 | self.cmdstate += 1 |
b54936a9 UH |
259 | |
260 | def handle_read(self, mosi, miso): | |
261 | # Read data bytes: Master asserts CS#, sends READ command, sends | |
262 | # 3-byte address, reads >= 1 data bytes, de-asserts CS#. | |
263 | if self.cmdstate == 1: | |
264 | # Byte 1: Master sends command ID. | |
de22de7f | 265 | self.emit_cmd_byte() |
b54936a9 UH |
266 | elif self.cmdstate in (2, 3, 4): |
267 | # Bytes 2/3/4: Master sends read address (24bits, MSB-first). | |
de22de7f | 268 | self.emit_addr_bytes(mosi) |
b54936a9 UH |
269 | elif self.cmdstate >= 5: |
270 | # Bytes 5-x: Master reads data bytes (until CS# de-asserted). | |
de22de7f | 271 | self.es_field = self.es # Will be overwritten for each byte. |
2c920167 | 272 | if self.cmdstate == 5: |
de22de7f UH |
273 | self.ss_field = self.ss |
274 | self.on_end_transaction = lambda: self.output_data_block('Data', Ann.READ) | |
2c920167 | 275 | self.data.append(miso) |
b54936a9 UH |
276 | self.cmdstate += 1 |
277 | ||
8a73c6c7 AA |
278 | def handle_write_common(self, mosi, miso, ann): |
279 | # Write data bytes: Master asserts CS#, sends WRITE command, sends | |
280 | # 3-byte address, writes >= 1 data bytes, de-asserts CS#. | |
281 | if self.cmdstate == 1: | |
282 | # Byte 1: Master sends command ID. | |
283 | self.emit_cmd_byte() | |
539e6daf VPP |
284 | if self.writestate == 0: |
285 | self.putc([Ann.WARN, ['Warning: WREN might be missing']]) | |
8a73c6c7 AA |
286 | elif self.cmdstate in (2, 3, 4): |
287 | # Bytes 2/3/4: Master sends write address (24bits, MSB-first). | |
288 | self.emit_addr_bytes(mosi) | |
289 | elif self.cmdstate >= 5: | |
290 | # Bytes 5-x: Master writes data bytes (until CS# de-asserted). | |
291 | self.es_field = self.es # Will be overwritten for each byte. | |
292 | if self.cmdstate == 5: | |
293 | self.ss_field = self.ss | |
294 | self.on_end_transaction = lambda: self.output_data_block('Data', ann) | |
295 | self.data.append(mosi) | |
296 | self.cmdstate += 1 | |
297 | ||
298 | def handle_write1(self, mosi, miso): | |
299 | self.handle_write_common(mosi, miso, Ann.WRITE1) | |
300 | ||
301 | def handle_write2(self, mosi, miso): | |
302 | self.handle_write_common(mosi, miso, Ann.WRITE2) | |
303 | ||
b54936a9 | 304 | def handle_fast_read(self, mosi, miso): |
7c139a54 UH |
305 | # Fast read: Master asserts CS#, sends FAST READ command, sends |
306 | # 3-byte address + 1 dummy byte, reads >= 1 data bytes, de-asserts CS#. | |
307 | if self.cmdstate == 1: | |
308 | # Byte 1: Master sends command ID. | |
de22de7f | 309 | self.emit_cmd_byte() |
7c139a54 | 310 | elif self.cmdstate in (2, 3, 4): |
de22de7f UH |
311 | # Bytes 2/3/4: Master sends read address (24bits, MSB-first). |
312 | self.emit_addr_bytes(mosi) | |
7c139a54 | 313 | elif self.cmdstate == 5: |
1be94d3d | 314 | self.putx([Ann.BIT, ['Dummy byte: 0x%02x' % mosi]]) |
7c139a54 UH |
315 | elif self.cmdstate >= 6: |
316 | # Bytes 6-x: Master reads data bytes (until CS# de-asserted). | |
de22de7f | 317 | self.es_field = self.es # Will be overwritten for each byte. |
7c139a54 | 318 | if self.cmdstate == 6: |
de22de7f UH |
319 | self.ss_field = self.ss |
320 | self.on_end_transaction = lambda: self.output_data_block('Data', Ann.FAST_READ) | |
2c920167 | 321 | self.data.append(miso) |
7c139a54 | 322 | self.cmdstate += 1 |
b54936a9 UH |
323 | |
324 | def handle_2read(self, mosi, miso): | |
de22de7f UH |
325 | # 2x I/O read (fast read dual I/O): Master asserts CS#, sends 2READ |
326 | # command, sends 3-byte address + 1 dummy byte, reads >= 1 data bytes, | |
327 | # de-asserts CS#. All data after the command is sent via two I/O pins. | |
10d3c8dc | 328 | # MOSI = SIO0 = even bits, MISO = SIO1 = odd bits. |
de22de7f UH |
329 | if self.cmdstate != 1: |
330 | b1, b2 = decode_dual_bytes(mosi, miso) | |
10d3c8dc AG |
331 | if self.cmdstate == 1: |
332 | # Byte 1: Master sends command ID. | |
de22de7f UH |
333 | self.emit_cmd_byte() |
334 | elif self.cmdstate == 2: | |
335 | # Bytes 2/3(/4): Master sends read address (24bits, MSB-first). | |
336 | # Handle bytes 2 and 3 here. | |
337 | self.emit_addr_bytes(b1) | |
338 | self.cmdstate = 3 | |
339 | self.emit_addr_bytes(b2) | |
340 | elif self.cmdstate == 4: | |
341 | # Byte 5: Dummy byte. Also handle byte 4 (address LSB) here. | |
342 | self.emit_addr_bytes(b1) | |
343 | self.cmdstate = 5 | |
344 | self.putx([Ann.BIT, ['Dummy byte: 0x%02x' % b2]]) | |
345 | elif self.cmdstate >= 6: | |
346 | # Bytes 6-x: Master reads data bytes (until CS# de-asserted). | |
347 | self.es_field = self.es # Will be overwritten for each byte. | |
348 | if self.cmdstate == 6: | |
349 | self.ss_field = self.ss | |
350 | self.on_end_transaction = lambda: self.output_data_block('Data', Ann.READ2X) | |
351 | self.data.append(b1) | |
352 | self.data.append(b2) | |
353 | self.cmdstate += 1 | |
b54936a9 | 354 | |
8a73c6c7 AA |
355 | def handle_status(self, mosi, miso): |
356 | if self.cmdstate == 1: | |
357 | # Byte 1: Master sends command ID. | |
358 | self.emit_cmd_byte() | |
359 | self.on_end_transaction = lambda: self.putc([Ann.STATUS, [cmds[self.state][1]]]) | |
360 | else: | |
361 | # Will be overwritten for each byte. | |
362 | self.es_cmd = self.es | |
363 | self.es_field = self.es | |
364 | if self.cmdstate == 2: | |
365 | self.ss_field = self.ss | |
366 | self.putx([Ann.BIT, ['Status register byte %d: 0x%02x' % ((self.cmdstate % 2) + 1, miso)]]) | |
367 | self.cmdstate += 1 | |
368 | ||
1b1c914f | 369 | # TODO: Warn/abort if we don't see the necessary amount of bytes. |
9b4d8a57 | 370 | def handle_se(self, mosi, miso): |
1b1c914f UH |
371 | if self.cmdstate == 1: |
372 | # Byte 1: Master sends command ID. | |
de22de7f | 373 | self.emit_cmd_byte() |
539e6daf VPP |
374 | if self.writestate == 0: |
375 | self.putx([Ann.WARN, ['Warning: WREN might be missing']]) | |
1b1c914f | 376 | elif self.cmdstate in (2, 3, 4): |
868fd207 | 377 | # Bytes 2/3/4: Master sends sector address (24bits, MSB-first). |
de22de7f | 378 | self.emit_addr_bytes(mosi) |
1b1c914f UH |
379 | |
380 | if self.cmdstate == 4: | |
de22de7f | 381 | self.es_cmd = self.es |
87e574b7 | 382 | d = 'Erase sector %d (0x%06x)' % (self.addr, self.addr) |
de22de7f | 383 | self.putc([Ann.SE, [d]]) |
1b1c914f UH |
384 | # TODO: Max. size depends on chip, check that too if possible. |
385 | if self.addr % 4096 != 0: | |
386 | # Sector addresses must be 4K-aligned (same for all 3 chips). | |
de22de7f | 387 | self.putc([Ann.WARN, ['Warning: Invalid sector address!']]) |
4772a846 | 388 | self.state = None |
1b1c914f UH |
389 | else: |
390 | self.cmdstate += 1 | |
391 | ||
b54936a9 UH |
392 | def handle_be(self, mosi, miso): |
393 | pass # TODO | |
394 | ||
395 | def handle_ce(self, mosi, miso): | |
51a91ed0 | 396 | self.putx([Ann.CE, self.cmd_ann_list()]) |
539e6daf VPP |
397 | if self.writestate == 0: |
398 | self.putx([Ann.WARN, ['Warning: WREN might be missing']]) | |
b54936a9 UH |
399 | |
400 | def handle_ce2(self, mosi, miso): | |
51a91ed0 | 401 | self.putx([Ann.CE2, self.cmd_ann_list()]) |
539e6daf VPP |
402 | if self.writestate == 0: |
403 | self.putx([Ann.WARN, ['Warning: WREN might be missing']]) | |
b54936a9 UH |
404 | |
405 | def handle_pp(self, mosi, miso): | |
406 | # Page program: Master asserts CS#, sends PP command, sends 3-byte | |
407 | # page address, sends >= 1 data bytes, de-asserts CS#. | |
408 | if self.cmdstate == 1: | |
409 | # Byte 1: Master sends command ID. | |
de22de7f | 410 | self.emit_cmd_byte() |
b54936a9 UH |
411 | elif self.cmdstate in (2, 3, 4): |
412 | # Bytes 2/3/4: Master sends page address (24bits, MSB-first). | |
de22de7f | 413 | self.emit_addr_bytes(mosi) |
b54936a9 UH |
414 | elif self.cmdstate >= 5: |
415 | # Bytes 5-x: Master sends data bytes (until CS# de-asserted). | |
de22de7f | 416 | self.es_field = self.es # Will be overwritten for each byte. |
2c920167 | 417 | if self.cmdstate == 5: |
de22de7f UH |
418 | self.ss_field = self.ss |
419 | self.on_end_transaction = lambda: self.output_data_block('Data', Ann.PP) | |
2c920167 | 420 | self.data.append(mosi) |
b54936a9 UH |
421 | self.cmdstate += 1 |
422 | ||
423 | def handle_cp(self, mosi, miso): | |
424 | pass # TODO | |
425 | ||
426 | def handle_dp(self, mosi, miso): | |
427 | pass # TODO | |
428 | ||
429 | def handle_rdp_res(self, mosi, miso): | |
e33410d3 UH |
430 | if self.cmdstate == 1: |
431 | # Byte 1: Master sends command ID. | |
de22de7f | 432 | self.emit_cmd_byte() |
e33410d3 UH |
433 | elif self.cmdstate in (2, 3, 4): |
434 | # Bytes 2/3/4: Master sends three dummy bytes. | |
de22de7f | 435 | self.putx([Ann.FIELD, ['Dummy byte: %02x' % mosi]]) |
e33410d3 UH |
436 | elif self.cmdstate == 5: |
437 | # Byte 5: Slave sends device ID. | |
de22de7f | 438 | self.es_cmd = self.es |
db188228 | 439 | self.device_id = miso |
de22de7f UH |
440 | self.putx([Ann.FIELD, ['Device ID: %s' % self.device()]]) |
441 | d = 'Device = %s' % self.vendor_device() | |
442 | self.putc([Ann.RDP_RES, self.cmd_vendor_dev_list()]) | |
e33410d3 | 443 | self.state = None |
e33410d3 | 444 | self.cmdstate += 1 |
b54936a9 | 445 | |
9b4d8a57 | 446 | def handle_rems(self, mosi, miso): |
1b1c914f UH |
447 | if self.cmdstate == 1: |
448 | # Byte 1: Master sends command ID. | |
de22de7f | 449 | self.emit_cmd_byte() |
1b1c914f UH |
450 | elif self.cmdstate in (2, 3): |
451 | # Bytes 2/3: Master sends two dummy bytes. | |
de22de7f | 452 | self.putx([Ann.FIELD, ['Dummy byte: 0x%02x' % mosi]]) |
1b1c914f UH |
453 | elif self.cmdstate == 4: |
454 | # Byte 4: Master sends 0x00 or 0x01. | |
455 | # 0x00: Master wants manufacturer ID as first reply byte. | |
456 | # 0x01: Master wants device ID as first reply byte. | |
9b4d8a57 UH |
457 | self.manufacturer_id_first = True if (mosi == 0x00) else False |
458 | d = 'manufacturer' if (mosi == 0x00) else 'device' | |
de22de7f | 459 | self.putx([Ann.FIELD, ['Master wants %s ID first' % d]]) |
1b1c914f UH |
460 | elif self.cmdstate == 5: |
461 | # Byte 5: Slave sends manufacturer ID (or device ID). | |
9b4d8a57 UH |
462 | self.ids = [miso] |
463 | d = 'Manufacturer' if self.manufacturer_id_first else 'Device' | |
de22de7f | 464 | self.putx([Ann.FIELD, ['%s ID: 0x%02x' % (d, miso)]]) |
9b4d8a57 | 465 | elif self.cmdstate == 6: |
1b1c914f | 466 | # Byte 6: Slave sends device ID (or manufacturer ID). |
7f7ea759 | 467 | self.ids.append(miso) |
de22de7f UH |
468 | d = 'Device' if self.manufacturer_id_first else 'Manufacturer' |
469 | self.putx([Ann.FIELD, ['%s ID: 0x%02x' % (d, miso)]]) | |
1b1c914f UH |
470 | |
471 | if self.cmdstate == 6: | |
1b1c914f | 472 | id = self.ids[1] if self.manufacturer_id_first else self.ids[0] |
db188228 | 473 | self.device_id = id |
de22de7f UH |
474 | self.es_cmd = self.es |
475 | self.putc([Ann.REMS, self.cmd_vendor_dev_list()]) | |
4772a846 | 476 | self.state = None |
1b1c914f UH |
477 | else: |
478 | self.cmdstate += 1 | |
479 | ||
b54936a9 UH |
480 | def handle_rems2(self, mosi, miso): |
481 | pass # TODO | |
e4022299 | 482 | |
b54936a9 UH |
483 | def handle_enso(self, mosi, miso): |
484 | pass # TODO | |
e4022299 | 485 | |
b54936a9 UH |
486 | def handle_exso(self, mosi, miso): |
487 | pass # TODO | |
e4022299 | 488 | |
b54936a9 UH |
489 | def handle_rdscur(self, mosi, miso): |
490 | pass # TODO | |
e4022299 | 491 | |
b54936a9 UH |
492 | def handle_wrscur(self, mosi, miso): |
493 | pass # TODO | |
e4022299 | 494 | |
b54936a9 UH |
495 | def handle_esry(self, mosi, miso): |
496 | pass # TODO | |
1b1c914f | 497 | |
b54936a9 UH |
498 | def handle_dsry(self, mosi, miso): |
499 | pass # TODO | |
5ebb76fe | 500 | |
de22de7f | 501 | def output_data_block(self, label, idx): |
2c920167 AG |
502 | # Print accumulated block of data |
503 | # (called on CS# de-assert via self.on_end_transaction callback). | |
de22de7f | 504 | self.es_cmd = self.es # End on the CS# de-assert sample. |
b33a73bc UH |
505 | if self.options['format'] == 'hex': |
506 | s = ' '.join([('%02x' % b) for b in self.data]) | |
507 | else: | |
508 | s = ''.join(map(chr, self.data)) | |
de22de7f UH |
509 | self.putf([Ann.FIELD, ['%s (%d bytes)' % (label, len(self.data))]]) |
510 | self.putc([idx, ['%s (addr 0x%06x, %d bytes): %s' % \ | |
511 | (cmds[self.state][1], self.addr, len(self.data), s)]]) | |
1b1c914f | 512 | |
2c920167 | 513 | def decode(self, ss, es, data): |
9b4d8a57 | 514 | ptype, mosi, miso = data |
1b1c914f | 515 | |
2c920167 | 516 | self.ss, self.es = ss, es |
e4022299 | 517 | |
2c920167 AG |
518 | if ptype == 'CS-CHANGE': |
519 | self.end_current_transaction() | |
e4022299 | 520 | |
3e3c0330 | 521 | if ptype != 'DATA': |
9b4d8a57 | 522 | return |
1b1c914f | 523 | |
9b4d8a57 | 524 | # If we encountered a known chip command, enter the resp. state. |
35b380b1 | 525 | if self.state is None: |
781ef945 UH |
526 | self.state = mosi |
527 | self.cmdstate = 1 | |
1b1c914f | 528 | |
9b4d8a57 | 529 | # Handle commands. |
1ec9c5e2 AG |
530 | try: |
531 | self.cmd_handlers[self.state](mosi, miso) | |
532 | except KeyError: | |
1be94d3d | 533 | self.putx([Ann.BIT, ['Unknown command: 0x%02x' % mosi]]) |
4772a846 | 534 | self.state = None |