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1##
2## This file is part of the sigrok project.
3##
4## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
d6bace96 5## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
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6##
7## This program is free software; you can redistribute it and/or modify
8## it under the terms of the GNU General Public License as published by
9## the Free Software Foundation; either version 2 of the License, or
10## (at your option) any later version.
11##
12## This program is distributed in the hope that it will be useful,
13## but WITHOUT ANY WARRANTY; without even the implied warranty of
14## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15## GNU General Public License for more details.
16##
17## You should have received a copy of the GNU General Public License
18## along with this program; if not, write to the Free Software
19## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20##
ad2dc0de 21
677d597b 22import sigrokdecode as srd
67e847fd 23
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24# Chip-select options
25ACTIVE_LOW = 0
26ACTIVE_HIGH = 1
27
28# Clock polarity options
29CPOL_0 = 0 # Clock is low when inactive
30CPOL_1 = 1 # Clock is high when inactive
31
32# Clock phase options
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33CPHA_0 = 0 # Data is valid on the leading clock edge
34CPHA_1 = 1 # Data is valid on the trailing clock edge
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35
36# Bit order options
37MSB_FIRST = 0
0c3089c1 38LSB_FIRST = 1
238b4080 39
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40spi_mode = {
41 (0, 0): 0, # Mode 0
42 (0, 1): 1, # Mode 1
43 (1, 0): 2, # Mode 2
44 (1, 1): 3, # Mode 3
45}
46
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47# Annotation formats
48ANN_HEX = 0
49
677d597b 50class Decoder(srd.Decoder):
67e847fd 51 id = 'spi'
2b7d0e2b 52 name = 'SPI'
3d3da57d 53 longname = 'Serial Peripheral Interface'
9a12a6e7 54 desc = '...desc...'
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55 longdesc = '...longdesc...'
56 author = 'Gareth McMullin'
57 email = 'gareth@blacksphere.co.nz'
58 license = 'gplv2+'
59 inputs = ['logic']
60 outputs = ['spi']
6b5b91d2 61 probes = [
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62 {'id': 'mosi', 'name': 'MOSI',
63 'desc': 'SPI MOSI line (Master out, slave in)'},
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64 {'id': 'miso', 'name': 'MISO',
65 'desc': 'SPI MISO line (Master in, slave out)'},
6b5b91d2 66 {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'},
4e570fa9 67 {'id': 'cs', 'name': 'CS#', 'desc': 'SPI CS (chip select) line'},
6b5b91d2 68 ]
238b4080 69 options = {
acba4869 70 'cs_polarity': ['CS# polarity', ACTIVE_LOW],
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71 'cpol': ['Clock polarity', CPOL_0],
72 'cpha': ['Clock phase', CPHA_0],
73 'bitorder': ['Bit order within the SPI data', MSB_FIRST],
74 'wordsize': ['Word size of SPI data', 8], # 1-64?
238b4080 75 }
b1bb5eed 76 annotations = [
d6bace96 77 ['Hex', 'SPI data bytes in hex format'],
b1bb5eed 78 ]
6eb87578 79
3643fc3f 80 def __init__(self):
c66baa8c 81 self.oldsck = 1
a10bfc48 82 self.bitcount = 0
4917bb31 83 self.mosidata = 0
d6bace96 84 self.misodata = 0
6eb87578 85 self.bytesreceived = 0
d6bace96 86 self.samplenum = -1
01329e88 87 self.cs_was_deasserted_during_data_word = 0
6eb87578 88
0db89774 89 # Set protocol decoder option defaults.
acba4869 90 self.cs_polarity = Decoder.options['cs_polarity'][1]
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91 self.cpol = Decoder.options['cpol'][1]
92 self.cpha = Decoder.options['cpha'][1]
93 self.bitorder = Decoder.options['bitorder'][1]
94 self.wordsize = Decoder.options['wordsize'][1]
0db89774 95
3643fc3f 96 def start(self, metadata):
d6bace96 97 self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi')
56202222 98 self.out_ann = self.add(srd.OUTPUT_ANN, 'spi')
3643fc3f 99
6eb87578 100 def report(self):
e100d51e 101 return 'SPI: %d bytes received' % self.bytesreceived
6eb87578 102
2b9837d9 103 def decode(self, ss, es, data):
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104 # HACK! At the moment the number of probes is not handled correctly.
105 # E.g. if an input file (-i foo.sr) has more than two probes enabled.
de9cee24 106 # for (samplenum, (mosi, sck, x, y, z, a)) in data:
b1bb5eed 107 # for (samplenum, (cs, miso, sck, mosi, wp, hold)) in data:
de9cee24 108 for (samplenum, (cs, miso, sck, mosi, wp, hold)) in data:
6eb87578 109
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110 self.samplenum += 1 # FIXME
111
c94c8c91 112 # Ignore sample if the clock pin hasn't changed.
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113 if sck == self.oldsck:
114 continue
c94c8c91 115
6eb87578 116 self.oldsck = sck
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117
118 # Sample data on rising/falling clock edge (depends on mode).
119 mode = spi_mode[self.cpol, self.cpha]
120 if mode == 0 and sck == 0: # Sample on rising clock edge
121 continue
122 elif mode == 1 and sck == 1: # Sample on falling clock edge
123 continue
124 elif mode == 2 and sck == 1: # Sample on falling clock edge
125 continue
126 elif mode == 3 and sck == 0: # Sample on rising clock edge
127 continue
6eb87578 128
d6bace96 129 # If this is the first bit, save its sample number.
a10bfc48 130 if self.bitcount == 0:
d6bace96 131 self.start_sample = samplenum
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132 deasserted = cs if (self.cs_polarity == ACTIVE_LOW) else not c
133 if deasserted:
01329e88 134 self.cs_was_deasserted_during_data_word = 1
b1bb5eed 135
1ea831e9 136 # Receive MOSI bit into our shift register.
c94c8c91 137 if self.bitorder == MSB_FIRST:
cc204746 138 self.mosidata |= mosi << (self.wordsize - 1 - self.bitcount)
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139 else:
140 self.mosidata |= mosi << self.bitcount
141
142 # Receive MISO bit into our shift register.
c94c8c91 143 if self.bitorder == MSB_FIRST:
cc204746 144 self.misodata |= miso << (self.wordsize - 1 - self.bitcount)
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145 else:
146 self.misodata |= miso << self.bitcount
b1bb5eed 147
a10bfc48 148 self.bitcount += 1
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149
150 # Continue to receive if not a byte yet.
cc204746 151 if self.bitcount != self.wordsize:
6eb87578 152 continue
b1bb5eed 153
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154 self.put(self.start_sample, self.samplenum, self.out_proto,
155 ['data', self.mosidata, self.misodata])
156 self.put(self.start_sample, self.samplenum, self.out_ann,
157 [ANN_HEX, ['MOSI: 0x%02x, MISO: 0x%02x' % (self.mosidata,
158 self.misodata)]])
b1bb5eed 159
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160 if self.cs_was_deasserted_during_data_word:
161 self.put(self.start_sample, self.samplenum, self.out_ann,
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162 [ANN_HEX, ['WARNING: CS# was deasserted during this '
163 'SPI data byte!']])
01329e88 164
b1bb5eed 165 # Reset decoder state.
4917bb31 166 self.mosidata = 0
d6bace96 167 self.misodata = 0
a10bfc48 168 self.bitcount = 0
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169
170 # Keep stats for summary.
6eb87578 171 self.bytesreceived += 1
ad2dc0de 172