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srd: SPI: probes[]: Add missing MISO and CS lines.
[libsigrokdecode.git] / decoders / spi.py
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1##
2## This file is part of the sigrok project.
3##
4## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz>
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; either version 2 of the License, or
9## (at your option) any later version.
10##
11## This program is distributed in the hope that it will be useful,
12## but WITHOUT ANY WARRANTY; without even the implied warranty of
13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14## GNU General Public License for more details.
15##
16## You should have received a copy of the GNU General Public License
17## along with this program; if not, write to the Free Software
18## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19##
ad2dc0de 20
677d597b 21import sigrokdecode as srd
67e847fd 22
677d597b 23class Decoder(srd.Decoder):
67e847fd 24 id = 'spi'
2b7d0e2b 25 name = 'SPI'
2b7d0e2b 26 longname = 'Serial Peripheral Interface (SPI) bus'
9a12a6e7 27 desc = '...desc...'
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28 longdesc = '...longdesc...'
29 author = 'Gareth McMullin'
30 email = 'gareth@blacksphere.co.nz'
31 license = 'gplv2+'
32 inputs = ['logic']
33 outputs = ['spi']
6b5b91d2 34 probes = [
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35 {'id': 'mosi', 'name': 'MOSI',
36 'desc': 'SPI MOSI line (Master out, slave in)'},
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37 {'id': 'miso', 'name': 'MISO',
38 'desc': 'SPI MISO line (Master in, slave out)'},
6b5b91d2 39 {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'},
4e570fa9 40 {'id': 'cs', 'name': 'CS#', 'desc': 'SPI CS (chip select) line'},
6b5b91d2 41 ]
6eb87578 42 options = {}
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43 annotations = [
44 ['TODO', 'TODO'],
45 ]
6eb87578 46
3643fc3f 47 def __init__(self):
c66baa8c 48 self.oldsck = 1
a10bfc48 49 self.bitcount = 0
4917bb31 50 self.mosidata = 0
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51 self.bytesreceived = 0
52
3643fc3f 53 def start(self, metadata):
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54 # self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi')
55 self.out_ann = self.add(srd.OUTPUT_ANN, 'spi')
3643fc3f 56
6eb87578 57 def report(self):
e100d51e 58 return 'SPI: %d bytes received' % self.bytesreceived
6eb87578 59
2b9837d9 60 def decode(self, ss, es, data):
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61 # HACK! At the moment the number of probes is not handled correctly.
62 # E.g. if an input file (-i foo.sr) has more than two probes enabled.
de9cee24 63 # for (samplenum, (mosi, sck, x, y, z, a)) in data:
b1bb5eed 64 # for (samplenum, (cs, miso, sck, mosi, wp, hold)) in data:
de9cee24 65 for (samplenum, (cs, miso, sck, mosi, wp, hold)) in data:
6eb87578 66
de9cee24 67 # Sample data on rising SCK edges.
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68 if sck == self.oldsck:
69 continue
70 self.oldsck = sck
b1bb5eed 71 if sck == 0:
ad2dc0de 72 continue
6eb87578 73
b1bb5eed 74 # If this is the first bit, save timestamp.
a10bfc48 75 if self.bitcount == 0:
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76 self.time = samplenum
77
78 # Receive bit into our shift register.
de9cee24 79 if mosi == 1:
4917bb31 80 self.mosidata |= 1 << (7 - self.bitcount)
b1bb5eed 81
a10bfc48 82 self.bitcount += 1
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83
84 # Continue to receive if not a byte yet.
a10bfc48 85 if self.bitcount != 8:
6eb87578 86 continue
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87
88 # self.put(0, 0, self.out_proto, out_proto) # TODO
4917bb31 89 self.put(0, 0, self.out_ann, [0, ['0x%02x' % self.mosidata]])
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90
91 # Reset decoder state.
4917bb31 92 self.mosidata = 0
a10bfc48 93 self.bitcount = 0
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94
95 # Keep stats for summary.
6eb87578 96 self.bytesreceived += 1
ad2dc0de 97