]>
Commit | Line | Data |
---|---|---|
6eb87578 GM |
1 | ## |
2 | ## This file is part of the sigrok project. | |
3 | ## | |
4 | ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz> | |
d6bace96 | 5 | ## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de> |
6eb87578 GM |
6 | ## |
7 | ## This program is free software; you can redistribute it and/or modify | |
8 | ## it under the terms of the GNU General Public License as published by | |
9 | ## the Free Software Foundation; either version 2 of the License, or | |
10 | ## (at your option) any later version. | |
11 | ## | |
12 | ## This program is distributed in the hope that it will be useful, | |
13 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | ## GNU General Public License for more details. | |
16 | ## | |
17 | ## You should have received a copy of the GNU General Public License | |
18 | ## along with this program; if not, write to the Free Software | |
19 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
20 | ## | |
ad2dc0de | 21 | |
677d597b | 22 | import sigrokdecode as srd |
67e847fd | 23 | |
238b4080 UH |
24 | # Chip-select options |
25 | ACTIVE_LOW = 0 | |
26 | ACTIVE_HIGH = 1 | |
27 | ||
28 | # Clock polarity options | |
29 | CPOL_0 = 0 # Clock is low when inactive | |
30 | CPOL_1 = 1 # Clock is high when inactive | |
31 | ||
32 | # Clock phase options | |
33 | CPHA_0 = 0 # Data is valid on the rising clock edge | |
34 | CPHA_1 = 1 # Data is valid on the falling clock edge | |
35 | ||
36 | # Bit order options | |
37 | MSB_FIRST = 0 | |
38 | LSB_FIRST = 0 | |
39 | ||
d6bace96 UH |
40 | # Annotation formats |
41 | ANN_HEX = 0 | |
42 | ||
677d597b | 43 | class Decoder(srd.Decoder): |
67e847fd | 44 | id = 'spi' |
2b7d0e2b | 45 | name = 'SPI' |
2b7d0e2b | 46 | longname = 'Serial Peripheral Interface (SPI) bus' |
9a12a6e7 | 47 | desc = '...desc...' |
6eb87578 GM |
48 | longdesc = '...longdesc...' |
49 | author = 'Gareth McMullin' | |
50 | email = 'gareth@blacksphere.co.nz' | |
51 | license = 'gplv2+' | |
52 | inputs = ['logic'] | |
53 | outputs = ['spi'] | |
6b5b91d2 | 54 | probes = [ |
de9cee24 UH |
55 | {'id': 'mosi', 'name': 'MOSI', |
56 | 'desc': 'SPI MOSI line (Master out, slave in)'}, | |
4e570fa9 UH |
57 | {'id': 'miso', 'name': 'MISO', |
58 | 'desc': 'SPI MISO line (Master in, slave out)'}, | |
6b5b91d2 | 59 | {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'}, |
4e570fa9 | 60 | {'id': 'cs', 'name': 'CS#', 'desc': 'SPI CS (chip select) line'}, |
6b5b91d2 | 61 | ] |
238b4080 UH |
62 | options = { |
63 | 'cs_active_low': ['CS# active low', ACTIVE_LOW], | |
64 | 'clock_polarity': ['Clock polarity', CPOL_0], | |
65 | 'clock_phase': ['Clock phase', CPHA_0], | |
66 | 'bit_order': ['Bit order within the SPI data', MSB_FIRST], | |
67 | 'word_size': ['Word size of SPI data', 8], # 1-64? | |
68 | } | |
b1bb5eed | 69 | annotations = [ |
d6bace96 | 70 | ['Hex', 'SPI data bytes in hex format'], |
b1bb5eed | 71 | ] |
6eb87578 | 72 | |
3643fc3f | 73 | def __init__(self): |
c66baa8c | 74 | self.oldsck = 1 |
a10bfc48 | 75 | self.bitcount = 0 |
4917bb31 | 76 | self.mosidata = 0 |
d6bace96 | 77 | self.misodata = 0 |
6eb87578 | 78 | self.bytesreceived = 0 |
d6bace96 | 79 | self.samplenum = -1 |
6eb87578 | 80 | |
3643fc3f | 81 | def start(self, metadata): |
d6bace96 | 82 | self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi') |
56202222 | 83 | self.out_ann = self.add(srd.OUTPUT_ANN, 'spi') |
3643fc3f | 84 | |
6eb87578 | 85 | def report(self): |
e100d51e | 86 | return 'SPI: %d bytes received' % self.bytesreceived |
6eb87578 | 87 | |
2b9837d9 | 88 | def decode(self, ss, es, data): |
6b5b91d2 UH |
89 | # HACK! At the moment the number of probes is not handled correctly. |
90 | # E.g. if an input file (-i foo.sr) has more than two probes enabled. | |
de9cee24 | 91 | # for (samplenum, (mosi, sck, x, y, z, a)) in data: |
b1bb5eed | 92 | # for (samplenum, (cs, miso, sck, mosi, wp, hold)) in data: |
de9cee24 | 93 | for (samplenum, (cs, miso, sck, mosi, wp, hold)) in data: |
6eb87578 | 94 | |
d6bace96 UH |
95 | self.samplenum += 1 # FIXME |
96 | ||
de9cee24 | 97 | # Sample data on rising SCK edges. |
6eb87578 GM |
98 | if sck == self.oldsck: |
99 | continue | |
100 | self.oldsck = sck | |
b1bb5eed | 101 | if sck == 0: |
ad2dc0de | 102 | continue |
6eb87578 | 103 | |
d6bace96 | 104 | # If this is the first bit, save its sample number. |
a10bfc48 | 105 | if self.bitcount == 0: |
d6bace96 | 106 | self.start_sample = samplenum |
b1bb5eed UH |
107 | |
108 | # Receive bit into our shift register. | |
de9cee24 | 109 | if mosi == 1: |
4917bb31 | 110 | self.mosidata |= 1 << (7 - self.bitcount) |
d6bace96 UH |
111 | if miso == 1: |
112 | self.misodata |= 1 << (7 - self.bitcount) | |
b1bb5eed | 113 | |
a10bfc48 | 114 | self.bitcount += 1 |
b1bb5eed UH |
115 | |
116 | # Continue to receive if not a byte yet. | |
a10bfc48 | 117 | if self.bitcount != 8: |
6eb87578 | 118 | continue |
b1bb5eed | 119 | |
d6bace96 UH |
120 | self.put(self.start_sample, self.samplenum, self.out_proto, |
121 | ['data', self.mosidata, self.misodata]) | |
122 | self.put(self.start_sample, self.samplenum, self.out_ann, | |
123 | [ANN_HEX, ['MOSI: 0x%02x, MISO: 0x%02x' % (self.mosidata, | |
124 | self.misodata)]]) | |
b1bb5eed UH |
125 | |
126 | # Reset decoder state. | |
4917bb31 | 127 | self.mosidata = 0 |
d6bace96 | 128 | self.misodata = 0 |
a10bfc48 | 129 | self.bitcount = 0 |
b1bb5eed UH |
130 | |
131 | # Keep stats for summary. | |
6eb87578 | 132 | self.bytesreceived += 1 |
ad2dc0de | 133 |