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parallel: add support for optional reset/enable/select signal
[libsigrokdecode.git] / decoders / parallel / pd.py
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1##
2## This file is part of the libsigrokdecode project.
3##
8eb06a59 4## Copyright (C) 2013-2016 Uwe Hermann <uwe@hermann-uwe.de>
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5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; either version 2 of the License, or
9## (at your option) any later version.
10##
11## This program is distributed in the hope that it will be useful,
12## but WITHOUT ANY WARRANTY; without even the implied warranty of
13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14## GNU General Public License for more details.
15##
16## You should have received a copy of the GNU General Public License
4539e9ca 17## along with this program; if not, see <http://www.gnu.org/licenses/>.
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18##
19
25e1418a 20import sigrokdecode as srd
a0b7e07f 21from common.srdhelper import bitpack
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22
23'''
c515eed7 24OUTPUT_PYTHON format:
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25
26Packet:
27[<ptype>, <pdata>]
28
29<ptype>, <pdata>
30 - 'ITEM', [<item>, <itembitsize>]
31 - 'WORD', [<word>, <wordbitsize>, <worditemcount>]
32
33<item>:
34 - A single item (a number). It can be of arbitrary size. The max. number
35 of bits in this item is specified in <itembitsize>.
36
37<itembitsize>:
38 - The size of an item (in bits). For a 4-bit parallel bus this is 4,
39 for a 16-bit parallel bus this is 16, and so on.
40
41<word>:
42 - A single word (a number). It can be of arbitrary size. The max. number
43 of bits in this word is specified in <wordbitsize>. The (exact) number
44 of items in this word is specified in <worditemcount>.
45
46<wordbitsize>:
47 - The size of a word (in bits). For a 2-item word with 8-bit items
48 <wordbitsize> is 16, for a 3-item word with 4-bit items <wordbitsize>
49 is 12, and so on.
50
51<worditemcount>:
52 - The size of a word (in number of items). For a 4-item word (no matter
53 how many bits each item consists of) <worditemcount> is 4, for a 7-item
54 word <worditemcount> is 7, and so on.
55'''
56
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57NUM_CHANNELS = 8
58
59class Pin:
60 CLOCK = 0
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61 DATA_0 = CLOCK + 1
62 DATA_N = DATA_0 + NUM_CHANNELS
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63 # BEWARE! DATA_N points _beyond_ the data partition (Python range(3)
64 # semantics, useful to have to simplify other code locations).
65 RESET = DATA_N
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66
67class Ann:
68 ITEM, WORD = range(2)
69
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70class ChannelError(Exception):
71 pass
72
25e1418a 73class Decoder(srd.Decoder):
8eb06a59 74 api_version = 3
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75 id = 'parallel'
76 name = 'Parallel'
77 longname = 'Parallel sync bus'
78 desc = 'Generic parallel synchronous bus.'
79 license = 'gplv2+'
80 inputs = ['logic']
81 outputs = ['parallel']
d6d8a8a4 82 tags = ['Util']
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83 optional_channels = tuple(
84 [{'id': 'clk', 'name': 'CLK', 'desc': 'Clock line'}] +
85 [
86 {'id': 'd%d' % i, 'name': 'D%d' % i, 'desc': 'Data line %d' % i}
87 for i in range(NUM_CHANNELS)
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88 ] +
89 [{'id': 'rst', 'name': 'RST', 'desc': 'RESET line'}]
615f86f6 90 )
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91 options = (
92 {'id': 'clock_edge', 'desc': 'Clock edge to sample on',
e2317ec4 93 'default': 'rising', 'values': ('rising', 'falling', 'either')},
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94 {'id': 'reset_polarity', 'desc': 'Reset line polarity',
95 'default': 'low-active', 'values': ('low-active', 'high-active')},
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96 {'id': 'wordsize', 'desc': 'Data wordsize (# bus cycles)',
97 'default': 0},
b0918d40 98 {'id': 'endianness', 'desc': 'Data endianness',
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99 'default': 'little', 'values': ('little', 'big')},
100 )
da9bcbd9 101 annotations = (
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102 ('item', 'Item'),
103 ('word', 'Word'),
da9bcbd9 104 )
ca24954f 105 annotation_rows = (
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106 ('items', 'Items', (Ann.ITEM,)),
107 ('words', 'Words', (Ann.WORD,)),
ca24954f 108 )
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109
110 def __init__(self):
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111 self.reset()
112
113 def reset(self):
25e1418a 114 self.items = []
25e1418a 115 self.saved_item = None
25e1418a 116 self.ss_item = self.es_item = None
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117 self.saved_word = None
118 self.ss_word = self.es_word = None
25e1418a 119 self.first = True
25e1418a 120
b098b820 121 def start(self):
c515eed7 122 self.out_python = self.register(srd.OUTPUT_PYTHON)
be465111 123 self.out_ann = self.register(srd.OUTPUT_ANN)
25e1418a 124
25e1418a 125 def putpb(self, data):
c515eed7 126 self.put(self.ss_item, self.es_item, self.out_python, data)
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127
128 def putb(self, data):
129 self.put(self.ss_item, self.es_item, self.out_ann, data)
130
131 def putpw(self, data):
c515eed7 132 self.put(self.ss_word, self.es_word, self.out_python, data)
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133
134 def putw(self, data):
135 self.put(self.ss_word, self.es_word, self.out_ann, data)
136
a0b7e07f 137 def handle_bits(self, item, used_pins):
25e1418a 138
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139 # If a word was previously accumulated, then emit its annotation
140 # now after its end samplenumber became available.
141 if self.saved_word is not None:
142 if self.options['wordsize'] > 0:
143 self.es_word = self.samplenum
9a41127e 144 self.putw([Ann.WORD, [self.fmt_word.format(self.saved_word)]])
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145 self.putpw(['WORD', self.saved_word])
146 self.saved_word = None
147
148 # Defer annotations for individual items until the next sample
149 # is taken, and the previous sample's end samplenumber has
150 # become available.
35b380b1 151 if self.first:
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152 # Save the start sample and item for later (no output yet).
153 self.ss_item = self.samplenum
154 self.first = False
155 self.saved_item = item
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156 elif self.saved_item is None:
157 pass
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158 else:
159 # Output the saved item (from the last CLK edge to the current).
160 self.es_item = self.samplenum
161 self.putpb(['ITEM', self.saved_item])
9a41127e 162 self.putb([Ann.ITEM, [self.fmt_item.format(self.saved_item)]])
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163 self.ss_item = self.samplenum
164 self.saved_item = item
165
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166 # Get as many items as the configured wordsize specifies.
167 if not self.items:
168 self.ss_word = self.samplenum
169 self.items.append(item)
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170 ws = self.options['wordsize']
171 if len(self.items) < ws:
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172 return
173
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174 # Collect words and prepare annotation details, but defer emission
175 # until the end samplenumber becomes available.
6f7dd46d 176 endian = self.options['endianness']
ca24954f 177 if endian == 'big':
6f7dd46d 178 self.items.reverse()
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179 word = sum([self.items[i] << (i * used_pins) for i in range(ws)])
180 self.saved_word = word
6f7dd46d 181 self.items = []
25e1418a 182
8eb06a59 183 def decode(self):
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184 # Determine which (optional) channels have input data. Insist in
185 # a non-empty input data set. Cope with sparse connection maps.
186 # Store enough state to later "compress" sampled input data.
615f86f6 187 data_indices = [
a0b7e07f 188 idx if self.has_channel(idx) else None
615f86f6 189 for idx in range(Pin.DATA_0, Pin.DATA_N)
a0b7e07f 190 ]
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191 has_data = [idx for idx in data_indices if idx is not None]
192 if not has_data:
193 raise ChannelError('Need at least one data channel.')
194 max_connected = max(has_data)
195
196 # Pre-determine which input data to strip off, the width of
197 # individual items and multiplexed words, as well as format
198 # strings here. This simplifies call sites which run in tight
199 # loops later.
200 upper_data_bound = max_connected + 1
201 num_item_bits = upper_data_bound - Pin.DATA_0
202 num_word_items = self.options['wordsize']
203 num_word_bits = num_item_bits * num_word_items
204 num_digits = (num_item_bits + 4 - 1) // 4
205 self.fmt_item = "{{:0{}x}}".format(num_digits)
206 num_digits = (num_word_bits + 4 - 1) // 4
207 self.fmt_word = "{{:0{}x}}".format(num_digits)
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208
209 # Determine .wait() conditions, depending on the presence of a
210 # clock signal. Either inspect samples on the configured edge of
211 # the clock, or inspect samples upon ANY edge of ANY of the pins
212 # which provide input data.
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213 conds = []
214 cond_idx_clock = None
215 cond_idx_data_0 = None
216 cond_idx_data_N = None
217 cond_idx_reset = None
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218 has_clock = self.has_channel(Pin.CLOCK)
219 if has_clock:
76b64d3a 220 cond_idx_clock = len(conds)
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221 edge = {
222 'rising': 'r',
223 'falling': 'f',
224 'either': 'e',
225 }.get(self.options['clock_edge'])
76b64d3a 226 conds.append({Pin.CLOCK: edge})
a0b7e07f 227 else:
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228 cond_idx_data_0 = len(conds)
229 conds.extend([{idx: 'e'} for idx in has_data])
230 cond_idx_data_N = len(conds)
231 has_reset = self.has_channel(Pin.RESET)
232 if has_reset:
233 cond_idx_reset = len(conds)
234 conds.append({Pin.RESET: 'e'})
235 reset_active = {
236 'low-active': 0,
237 'high-active': 1,
238 }.get(self.options['reset_polarity'])
fcdd8c68 239
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240 # Keep processing the input stream. Assume "always zero" for
241 # not-connected input lines. Pass data bits (all inputs except
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242 # clock and reset) to the handle_bits() method. Handle reset
243 # edges first and data changes then, within the same iteration.
244 # This results in robust operation for low-oversampled input.
245 in_reset = False
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246 while True:
247 pins = self.wait(conds)
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248 clock_edge = cond_idx_clock is not None and self.matched[cond_idx_clock]
249 data_edge = cond_idx_data_0 is not None and [idx for idx in range(cond_idx_data_0, cond_idx_data_N) if self.matched[idx]]
250 reset_edge = cond_idx_reset is not None and self.matched[cond_idx_reset]
251
252 if reset_edge:
253 in_reset = pins[Pin.RESET] == reset_active
254 if in_reset:
255 self.handle_bits(None, num_item_bits)
256 self.saved_item = None
257 self.saved_word = None
258 self.first = True
259 if in_reset:
260 continue
261
262 if clock_edge or data_edge:
263 data_bits = [0 if idx is None else pins[idx] for idx in data_indices]
264 data_bits = data_bits[:num_item_bits]
265 item = bitpack(data_bits)
266 self.handle_bits(item, num_item_bits)