]> sigrok.org Git - libsigrokdecode.git/blame - decoders/jtag/pd.py
jtag: Refactor and simplify some code.
[libsigrokdecode.git] / decoders / jtag / pd.py
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557a143d 1##
50bd5d25 2## This file is part of the libsigrokdecode project.
557a143d 3##
6b32f928 4## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de>
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5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; either version 2 of the License, or
9## (at your option) any later version.
10##
11## This program is distributed in the hope that it will be useful,
12## but WITHOUT ANY WARRANTY; without even the implied warranty of
13## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14## GNU General Public License for more details.
15##
16## You should have received a copy of the GNU General Public License
17## along with this program; if not, write to the Free Software
18## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19##
20
21# JTAG protocol decoder
22
23import sigrokdecode as srd
24
25class Decoder(srd.Decoder):
26 api_version = 1
27 id = 'jtag'
28 name = 'JTAG'
b7a7e6f5 29 longname = 'Joint Test Action Group (IEEE 1149.1)'
6e7a0087 30 desc = 'Protocol for testing, debugging, and flashing ICs.'
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31 license = 'gplv2+'
32 inputs = ['logic']
33 outputs = ['jtag']
34 probes = [
35 {'id': 'tdi', 'name': 'TDI', 'desc': 'Test data input'},
36 {'id': 'tdo', 'name': 'TDO', 'desc': 'Test data output'},
37 {'id': 'tck', 'name': 'TCK', 'desc': 'Test clock'},
38 {'id': 'tms', 'name': 'TMS', 'desc': 'Test mode select'},
557a143d 39 ]
6d990fe1 40 optional_probes = [
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41 {'id': 'trst', 'name': 'TRST#', 'desc': 'Test reset'},
42 {'id': 'srst', 'name': 'SRST#', 'desc': 'System reset'},
43 {'id': 'rtck', 'name': 'RTCK', 'desc': 'Return clock signal'},
6d990fe1 44 ]
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45 options = {}
46 annotations = [
ee3e279c 47 ['Text', 'Human-readable text'],
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48 ]
49
50 def __init__(self, **kwargs):
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51 # self.state = 'TEST-LOGIC-RESET'
52 self.state = 'RUN-TEST/IDLE'
53 self.oldstate = None
6d990fe1 54 self.oldpins = (-1, -1, -1, -1)
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55 self.oldtck = -1
56 self.bits_tdi = []
57 self.bits_tdo = []
6b32f928 58 self.samplenum = 0
557a143d 59
8915b346 60 def start(self):
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61 self.out_proto = self.register(srd.OUTPUT_PYTHON)
62 self.out_ann = self.register(srd.OUTPUT_ANN)
557a143d 63
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64 def putx(self, data):
65 self.put(self.samplenum, self.samplenum, self.out_ann, data)
66
67 def putp(self, data):
68 self.put(self.samplenum, self.samplenum, self.out_proto, data)
69
557a143d 70 def advance_state_machine(self, tms):
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71 self.oldstate = self.state
72
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73 # Intro "tree"
74 if self.state == 'TEST-LOGIC-RESET':
75 self.state = 'TEST-LOGIC-RESET' if (tms) else 'RUN-TEST/IDLE'
76 elif self.state == 'RUN-TEST/IDLE':
77 self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
78
79 # DR "tree"
80 elif self.state == 'SELECT-DR-SCAN':
81 self.state = 'SELECT-IR-SCAN' if (tms) else 'CAPTURE-DR'
82 elif self.state == 'CAPTURE-DR':
83 self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR'
84 elif self.state == 'SHIFT-DR':
85 self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR'
86 elif self.state == 'EXIT1-DR':
87 self.state = 'UPDATE-DR' if (tms) else 'PAUSE-DR'
88 elif self.state == 'PAUSE-DR':
89 self.state = 'EXIT2-DR' if (tms) else 'PAUSE-DR'
90 elif self.state == 'EXIT2-DR':
91 self.state = 'UPDATE-DR' if (tms) else 'SHIFT-DR'
92 elif self.state == 'UPDATE-DR':
93 self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
94
95 # IR "tree"
96 elif self.state == 'SELECT-IR-SCAN':
97 self.state = 'TEST-LOGIC-RESET' if (tms) else 'CAPTURE-IR'
98 elif self.state == 'CAPTURE-IR':
99 self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR'
100 elif self.state == 'SHIFT-IR':
101 self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR'
102 elif self.state == 'EXIT1-IR':
103 self.state = 'UPDATE-IR' if (tms) else 'PAUSE-IR'
104 elif self.state == 'PAUSE-IR':
105 self.state = 'EXIT2-IR' if (tms) else 'PAUSE-IR'
106 elif self.state == 'EXIT2-IR':
107 self.state = 'UPDATE-IR' if (tms) else 'SHIFT-IR'
108 elif self.state == 'UPDATE-IR':
109 self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
110
111 else:
112 raise Exception('Invalid state: %s' % self.state)
113
6d990fe1 114 def handle_rising_tck_edge(self, tdi, tdo, tck, tms):
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115 # Rising TCK edges always advance the state machine.
116 self.advance_state_machine(tms)
117
118 # Output the state we just switched to.
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119 self.putx([0, ['New state: %s' % self.state]])
120 self.putp(['NEW STATE', self.state])
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121
122 # If we went from SHIFT-IR to SHIFT-IR, or SHIFT-DR to SHIFT-DR,
123 # collect the current TDI/TDO values (upon rising TCK edge).
124 if self.state.startswith('SHIFT-') and self.oldstate == self.state:
125 self.bits_tdi.insert(0, tdi)
126 self.bits_tdo.insert(0, tdo)
127 # TODO: ANN/PROTO output.
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128 # self.putx([0, ['TDI add: ' + str(tdi)]])
129 # self.putp([0, ['TDO add: ' + str(tdo)]])
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130
131 # Output all TDI/TDO bits if we just switched from SHIFT-* to EXIT1-*.
132 if self.oldstate.startswith('SHIFT-') and \
133 self.state.startswith('EXIT1-'):
134
135 t = self.state[-2:] + ' TDI'
136 b = ''.join(map(str, self.bits_tdi))
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137 h = ' (0x%x' % int('0b' + b, 2) + ')'
138 s = t + ': ' + b + h + ', ' + str(len(self.bits_tdi)) + ' bits'
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139 # self.putx([0, [s]])
140 # self.putp([t, b])
e5edf39f 141 self.bits_tdi = []
557a143d 142
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143 t = self.state[-2:] + ' TDO'
144 b = ''.join(map(str, self.bits_tdo))
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145 h = ' (0x%x' % int('0b' + b, 2) + ')'
146 s = t + ': ' + b + h + ', ' + str(len(self.bits_tdo)) + ' bits'
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147 # self.putx([0, [s]])
148 # self.putp([t, b])
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149 self.bits_tdo = []
150
151 def decode(self, ss, es, data):
6b32f928 152 for (self.samplenum, pins) in data:
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153
154 # If none of the pins changed, there's nothing to do.
155 if self.oldpins == pins:
156 continue
157
158 # Store current pin values for the next round.
159 self.oldpins = pins
160
161 # Get individual pin values into local variables.
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162 # Unused probes will have a value of > 1.
163 (tdi, tdo, tck, tms, trst, srst, rtck) = pins
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164
165 # We only care about TCK edges (either rising or falling).
166 if (self.oldtck == tck):
167 continue
168
169 # Store start/end sample for later usage.
170 self.ss, self.es = ss, es
171
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172 # self.putx([0, ['tdi:%s, tdo:%s, tck:%s, tms:%s' \
173 # % (tdi, tdo, tck, tms)]])
e5edf39f 174
557a143d 175 if (self.oldtck == 0 and tck == 1):
6d990fe1 176 self.handle_rising_tck_edge(tdi, tdo, tck, tms)
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177
178 self.oldtck = tck
179