[libsigrokdecode.git] / decoders / jtag / jtag.py

##
## This file is part of the sigrok project.
##
## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

# JTAG protocol decoder

import sigrokdecode as srd

class Decoder(srd.Decoder):
    api_version = 1
    id = 'jtag'
    name = 'JTAG'
    longname = 'Joint Test Action Group'
    desc = 'TODO.'
    license = 'gplv2+'
    inputs = ['logic']
    outputs = ['jtag']
    probes = [
        {'id': 'tdi',  'name': 'TDI',  'desc': 'Test data input'},
        {'id': 'tdo',  'name': 'TDO',  'desc': 'Test data output'},
        {'id': 'tck',  'name': 'TCK',  'desc': 'Test clock'},
        {'id': 'tms',  'name': 'TMS',  'desc': 'Test mode select'},
    ]
    optional_probes = [
        # {'id': 'trst', 'name': 'TRST#', 'desc': 'Test reset'},
        # {'id': 'srst', 'name': 'SRST#', 'desc': 'System reset'},
    ]
    options = {}
    annotations = [
        ['ASCII', 'TODO: description'],
    ]

    def __init__(self, **kwargs):
        # self.state = 'TEST-LOGIC-RESET'
        self.state = 'RUN-TEST/IDLE'
        self.oldstate = None
        self.oldpins = (-1, -1, -1, -1)
        self.oldtck = -1
        self.bits_tdi = []
        self.bits_tdo = []

    def start(self, metadata):
        self.out_proto = self.add(srd.OUTPUT_PROTO, 'jtag')
        self.out_ann = self.add(srd.OUTPUT_ANN, 'jtag')

    def report(self):
        pass

    def advance_state_machine(self, tms):
        self.oldstate = self.state

        # Intro "tree"
        if self.state == 'TEST-LOGIC-RESET':
            self.state = 'TEST-LOGIC-RESET' if (tms) else 'RUN-TEST/IDLE'
        elif self.state == 'RUN-TEST/IDLE':
            self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'

        # DR "tree"
        elif self.state == 'SELECT-DR-SCAN':
            self.state = 'SELECT-IR-SCAN' if (tms) else 'CAPTURE-DR'
        elif self.state == 'CAPTURE-DR':
            self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR'
        elif self.state == 'SHIFT-DR':
            self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR'
        elif self.state == 'EXIT1-DR':
            self.state = 'UPDATE-DR' if (tms) else 'PAUSE-DR'
        elif self.state == 'PAUSE-DR':
            self.state = 'EXIT2-DR' if (tms) else 'PAUSE-DR'
        elif self.state == 'EXIT2-DR':
            self.state = 'UPDATE-DR' if (tms) else 'SHIFT-DR'
        elif self.state == 'UPDATE-DR':
            self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'

        # IR "tree"
        elif self.state == 'SELECT-IR-SCAN':
            self.state = 'TEST-LOGIC-RESET' if (tms) else 'CAPTURE-IR'
        elif self.state == 'CAPTURE-IR':
            self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR'
        elif self.state == 'SHIFT-IR':
            self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR'
        elif self.state == 'EXIT1-IR':
            self.state = 'UPDATE-IR' if (tms) else 'PAUSE-IR'
        elif self.state == 'PAUSE-IR':
            self.state = 'EXIT2-IR' if (tms) else 'PAUSE-IR'
        elif self.state == 'EXIT2-IR':
            self.state = 'UPDATE-IR' if (tms) else 'SHIFT-IR'
        elif self.state == 'UPDATE-IR':
            self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'

        else:
            raise Exception('Invalid state: %s' % self.state)

    def handle_rising_tck_edge(self, tdi, tdo, tck, tms):
        # Rising TCK edges always advance the state machine.
        self.advance_state_machine(tms)

        # Output the state we just switched to.
        self.put(self.ss, self.es, self.out_ann,
                 [0, ['New state: %s' % self.state]])
        self.put(self.ss, self.es, self.out_proto,
                 ['NEW STATE', self.state])

        # If we went from SHIFT-IR to SHIFT-IR, or SHIFT-DR to SHIFT-DR,
        # collect the current TDI/TDO values (upon rising TCK edge).
        if self.state.startswith('SHIFT-') and self.oldstate == self.state:
            self.bits_tdi.insert(0, tdi)
            self.bits_tdo.insert(0, tdo)
            # TODO: ANN/PROTO output.
            # self.put(self.ss, self.es, self.out_ann,
            #          [0, ['TDI add: ' + str(tdi)]])
            # self.put(self.ss, self.es, self.out_ann,
            #          [0, ['TDO add: ' + str(tdo)]])

        # Output all TDI/TDO bits if we just switched from SHIFT-* to EXIT1-*.
        if self.oldstate.startswith('SHIFT-') and \
           self.state.startswith('EXIT1-'):

            t = self.state[-2:] + ' TDI'
            b = ''.join(map(str, self.bits_tdi))
            s = t + ': ' + b + ', ' + str(len(self.bits_tdi)) + ' bits'
            self.put(self.ss, self.es, self.out_ann, [0, [s]])
            self.put(self.ss, self.es, self.out_proto, [t, b])
            self.bits_tdi = []

            t = self.state[-2:] + ' TDO'
            b = ''.join(map(str, self.bits_tdo))
            s = t + ': ' + b + ', ' + str(len(self.bits_tdo)) + ' bits'
            self.put(self.ss, self.es, self.out_ann, [0, [s]])
            self.put(self.ss, self.es, self.out_proto, [t, b])
            self.bits_tdo = []

    def decode(self, ss, es, data):
        for (samplenum, pins) in data:

            # If none of the pins changed, there's nothing to do.
            if self.oldpins == pins:
                continue

            # Store current pin values for the next round.
            self.oldpins = pins

            # Get individual pin values into local variables.
            # TODO: Handle optional pins (TRST, SRST).
            (tdi, tdo, tck, tms) = pins

            # We only care about TCK edges (either rising or falling).
            if (self.oldtck == tck):
                continue

            # Store start/end sample for later usage.
            self.ss, self.es = ss, es

            # self.put(self.ss, self.es, self.out_ann,
            #     [0, ['tdi:%s, tdo:%s, tck:%s, tms:%s' \
            #          % (tdi, tdo, tck, tms)]])

            if (self.oldtck == 0 and tck == 1):
                self.handle_rising_tck_edge(tdi, tdo, tck, tms)

            self.oldtck = tck
Commit	Line	Data
557a143d UH	1	##
	2	## This file is part of the sigrok project.
	3	##
	4	## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de>
	5	##
	6	## This program is free software; you can redistribute it and/or modify
	7	## it under the terms of the GNU General Public License as published by
	8	## the Free Software Foundation; either version 2 of the License, or
	9	## (at your option) any later version.
	10	##
	11	## This program is distributed in the hope that it will be useful,
	12	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	## GNU General Public License for more details.
	15	##
	16	## You should have received a copy of the GNU General Public License
	17	## along with this program; if not, write to the Free Software
	18	## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	19	##
	20
	21	# JTAG protocol decoder
	22
	23	import sigrokdecode as srd
	24
	25	class Decoder(srd.Decoder):
	26	api_version = 1
	27	id = 'jtag'
	28	name = 'JTAG'
	29	longname = 'Joint Test Action Group'
	30	desc = 'TODO.'
	31	license = 'gplv2+'
	32	inputs = ['logic']
	33	outputs = ['jtag']
	34	probes = [
	35	{'id': 'tdi', 'name': 'TDI', 'desc': 'Test data input'},
	36	{'id': 'tdo', 'name': 'TDO', 'desc': 'Test data output'},
	37	{'id': 'tck', 'name': 'TCK', 'desc': 'Test clock'},
	38	{'id': 'tms', 'name': 'TMS', 'desc': 'Test mode select'},
557a143d	39	]
6d990fe1 UH	40	optional_probes = [
	41	# {'id': 'trst', 'name': 'TRST#', 'desc': 'Test reset'},
	42	# {'id': 'srst', 'name': 'SRST#', 'desc': 'System reset'},
	43	]
557a143d UH	44	options = {}
	45	annotations = [
	46	['ASCII', 'TODO: description'],
	47	]
	48
	49	def __init__(self, **kwargs):
e5edf39f UH	50	# self.state = 'TEST-LOGIC-RESET'
	51	self.state = 'RUN-TEST/IDLE'
	52	self.oldstate = None
6d990fe1	53	self.oldpins = (-1, -1, -1, -1)
557a143d UH	54	self.oldtck = -1
	55	self.bits_tdi = []
	56	self.bits_tdo = []
	57
	58	def start(self, metadata):
	59	self.out_proto = self.add(srd.OUTPUT_PROTO, 'jtag')
	60	self.out_ann = self.add(srd.OUTPUT_ANN, 'jtag')
	61
	62	def report(self):
	63	pass
	64
	65	def advance_state_machine(self, tms):
e5edf39f UH	66	self.oldstate = self.state
e5edf39f UH	67
557a143d UH	68	# Intro "tree"
	69	if self.state == 'TEST-LOGIC-RESET':
	70	self.state = 'TEST-LOGIC-RESET' if (tms) else 'RUN-TEST/IDLE'
	71	elif self.state == 'RUN-TEST/IDLE':
	72	self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
	73
	74	# DR "tree"
	75	elif self.state == 'SELECT-DR-SCAN':
	76	self.state = 'SELECT-IR-SCAN' if (tms) else 'CAPTURE-DR'
	77	elif self.state == 'CAPTURE-DR':
	78	self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR'
	79	elif self.state == 'SHIFT-DR':
	80	self.state = 'EXIT1-DR' if (tms) else 'SHIFT-DR'
	81	elif self.state == 'EXIT1-DR':
	82	self.state = 'UPDATE-DR' if (tms) else 'PAUSE-DR'
	83	elif self.state == 'PAUSE-DR':
	84	self.state = 'EXIT2-DR' if (tms) else 'PAUSE-DR'
	85	elif self.state == 'EXIT2-DR':
	86	self.state = 'UPDATE-DR' if (tms) else 'SHIFT-DR'
	87	elif self.state == 'UPDATE-DR':
	88	self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
	89
	90	# IR "tree"
	91	elif self.state == 'SELECT-IR-SCAN':
	92	self.state = 'TEST-LOGIC-RESET' if (tms) else 'CAPTURE-IR'
	93	elif self.state == 'CAPTURE-IR':
	94	self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR'
	95	elif self.state == 'SHIFT-IR':
	96	self.state = 'EXIT1-IR' if (tms) else 'SHIFT-IR'
	97	elif self.state == 'EXIT1-IR':
	98	self.state = 'UPDATE-IR' if (tms) else 'PAUSE-IR'
	99	elif self.state == 'PAUSE-IR':
	100	self.state = 'EXIT2-IR' if (tms) else 'PAUSE-IR'
	101	elif self.state == 'EXIT2-IR':
	102	self.state = 'UPDATE-IR' if (tms) else 'SHIFT-IR'
	103	elif self.state == 'UPDATE-IR':
	104	self.state = 'SELECT-DR-SCAN' if (tms) else 'RUN-TEST/IDLE'
	105
	106	else:
	107	raise Exception('Invalid state: %s' % self.state)
	108
6d990fe1	109	def handle_rising_tck_edge(self, tdi, tdo, tck, tms):
557a143d UH	110	# Rising TCK edges always advance the state machine.
	111	self.advance_state_machine(tms)
	112
	113	# Output the state we just switched to.
	114	self.put(self.ss, self.es, self.out_ann,
	115	[0, ['New state: %s' % self.state]])
e5edf39f UH	116	self.put(self.ss, self.es, self.out_proto,
	117	['NEW STATE', self.state])
	118
	119	# If we went from SHIFT-IR to SHIFT-IR, or SHIFT-DR to SHIFT-DR,
	120	# collect the current TDI/TDO values (upon rising TCK edge).
	121	if self.state.startswith('SHIFT-') and self.oldstate == self.state:
	122	self.bits_tdi.insert(0, tdi)
	123	self.bits_tdo.insert(0, tdo)
	124	# TODO: ANN/PROTO output.
	125	# self.put(self.ss, self.es, self.out_ann,
	126	# [0, ['TDI add: ' + str(tdi)]])
	127	# self.put(self.ss, self.es, self.out_ann,
	128	# [0, ['TDO add: ' + str(tdo)]])
	129
	130	# Output all TDI/TDO bits if we just switched from SHIFT-* to EXIT1-*.
	131	if self.oldstate.startswith('SHIFT-') and \
	132	self.state.startswith('EXIT1-'):
	133
	134	t = self.state[-2:] + ' TDI'
	135	b = ''.join(map(str, self.bits_tdi))
	136	s = t + ': ' + b + ', ' + str(len(self.bits_tdi)) + ' bits'
	137	self.put(self.ss, self.es, self.out_ann, [0, [s]])
	138	self.put(self.ss, self.es, self.out_proto, [t, b])
	139	self.bits_tdi = []
557a143d	140
e5edf39f UH	141	t = self.state[-2:] + ' TDO'
	142	b = ''.join(map(str, self.bits_tdo))
	143	s = t + ': ' + b + ', ' + str(len(self.bits_tdo)) + ' bits'
557a143d	144	self.put(self.ss, self.es, self.out_ann, [0, [s]])
e5edf39f	145	self.put(self.ss, self.es, self.out_proto, [t, b])
557a143d UH	146	self.bits_tdo = []
	147
	148	def decode(self, ss, es, data):
	149	for (samplenum, pins) in data:
	150
	151	# If none of the pins changed, there's nothing to do.
	152	if self.oldpins == pins:
	153	continue
	154
	155	# Store current pin values for the next round.
	156	self.oldpins = pins
	157
	158	# Get individual pin values into local variables.
6d990fe1 UH	159	# TODO: Handle optional pins (TRST, SRST).
6d990fe1 UH	160	(tdi, tdo, tck, tms) = pins
557a143d UH	161
	162	# We only care about TCK edges (either rising or falling).
	163	if (self.oldtck == tck):
	164	continue
	165
	166	# Store start/end sample for later usage.
	167	self.ss, self.es = ss, es
	168
e5edf39f	169	# self.put(self.ss, self.es, self.out_ann,
6d990fe1 UH	170	# [0, ['tdi:%s, tdo:%s, tck:%s, tms:%s' \
6d990fe1 UH	171	# % (tdi, tdo, tck, tms)]])
e5edf39f	172
557a143d	173	if (self.oldtck == 0 and tck == 1):
6d990fe1	174	self.handle_rising_tck_edge(tdi, tdo, tck, tms)
557a143d UH	175
	176	self.oldtck = tck
	177