[libsigrokdecode.git] / decoders / ds1307 / pd.py

##
## This file is part of the libsigrokdecode project.
##
## Copyright (C) 2012-2014 Uwe Hermann <uwe@hermann-uwe.de>
## Copyright (C) 2013 Matt Ranostay <mranostay@gmail.com>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, see <http://www.gnu.org/licenses/>.
##

import re
import sigrokdecode as srd
from common.srdhelper import bcd2int

days_of_week = (
    'Sunday', 'Monday', 'Tuesday', 'Wednesday',
    'Thursday', 'Friday', 'Saturday',
)

regs = (
    'Seconds', 'Minutes', 'Hours', 'Day', 'Date', 'Month', 'Year',
    'Control', 'RAM',
)

bits = (
    'Clock halt', 'Seconds', 'Reserved', 'Minutes', '12/24 hours', 'AM/PM',
    'Hours', 'Day', 'Date', 'Month', 'Year', 'OUT', 'SQWE', 'RS', 'RAM',
)

rates = {
    0b00: '1Hz',
    0b01: '4096kHz',
    0b10: '8192kHz',
    0b11: '32768kHz',
}

DS1307_I2C_ADDRESS = 0x68

def regs_and_bits():
    l = [('reg-' + r.lower(), r + ' register') for r in regs]
    l += [('bit-' + re.sub('\/| ', '-', b).lower(), b + ' bit') for b in bits]
    return tuple(l)

class Decoder(srd.Decoder):
    api_version = 3
    id = 'ds1307'
    name = 'DS1307'
    longname = 'Dallas DS1307'
    desc = 'Realtime clock module protocol.'
    license = 'gplv2+'
    inputs = ['i2c']
    outputs = ['ds1307']
    annotations =  regs_and_bits() + (
        ('read-datetime', 'Read date/time'),
        ('write-datetime', 'Write date/time'),
        ('reg-read', 'Register read'),
        ('reg-write', 'Register write'),
        ('warnings', 'Warnings'),
    )
    annotation_rows = (
        ('bits', 'Bits', tuple(range(9, 24))),
        ('regs', 'Registers', tuple(range(9))),
        ('date-time', 'Date/time', (24, 25, 26, 27)),
        ('warnings', 'Warnings', (28,)),
    )

    def __init__(self):
        self.state = 'IDLE'
        self.hours = -1
        self.minutes = -1
        self.seconds = -1
        self.days = -1
        self.date = -1
        self.months = -1
        self.years = -1
        self.bits = []

    def start(self):
        self.out_ann = self.register(srd.OUTPUT_ANN)

    def putx(self, data):
        self.put(self.ss, self.es, self.out_ann, data)

    def putd(self, bit1, bit2, data):
        self.put(self.bits[bit1][1], self.bits[bit2][2], self.out_ann, data)

    def putr(self, bit):
        self.put(self.bits[bit][1], self.bits[bit][2], self.out_ann,
                 [11, ['Reserved bit', 'Reserved', 'Rsvd', 'R']])

    def handle_reg_0x00(self, b): # Seconds (0-59) / Clock halt bit
        self.putd(7, 0, [0, ['Seconds', 'Sec', 'S']])
        ch = 1 if (b & (1 << 7)) else 0
        self.putd(7, 7, [9, ['Clock halt: %d' % ch, 'Clk hlt: %d' % ch,
                        'CH: %d' % ch, 'CH']])
        s = self.seconds = bcd2int(b & 0x7f)
        self.putd(6, 0, [10, ['Second: %d' % s, 'Sec: %d' % s, 'S: %d' % s, 'S']])

    def handle_reg_0x01(self, b): # Minutes (0-59)
        self.putd(7, 0, [1, ['Minutes', 'Min', 'M']])
        self.putr(7)
        m = self.minutes = bcd2int(b & 0x7f)
        self.putd(6, 0, [12, ['Minute: %d' % m, 'Min: %d' % m, 'M: %d' % m, 'M']])

    def handle_reg_0x02(self, b): # Hours (1-12+AM/PM or 0-23)
        self.putd(7, 0, [2, ['Hours', 'H']])
        self.putr(7)
        ampm_mode = True if (b & (1 << 6)) else False
        if ampm_mode:
            self.putd(6, 6, [13, ['12-hour mode', '12h mode', '12h']])
            a = 'AM' if (b & (1 << 6)) else 'PM'
            self.putd(5, 5, [14, [a, a[0]]])
            h = self.hours = bcd2int(b & 0x1f)
            self.putd(4, 0, [15, ['Hour: %d' % h, 'H: %d' % h, 'H']])
        else:
            self.putd(6, 6, [13, ['24-hour mode', '24h mode', '24h']])
            h = self.hours = bcd2int(b & 0x3f)
            self.putd(5, 0, [15, ['Hour: %d' % h, 'H: %d' % h, 'H']])

    def handle_reg_0x03(self, b): # Day / day of week (1-7)
        self.putd(7, 0, [3, ['Day of week', 'Day', 'D']])
        for i in (7, 6, 5, 4, 3):
            self.putr(i)
        w = self.days = bcd2int(b & 0x07)
        ws = days_of_week[self.days - 1]
        self.putd(2, 0, [16, ['Weekday: %s' % ws, 'WD: %s' % ws, 'WD', 'W']])

    def handle_reg_0x04(self, b): # Date (1-31)
        self.putd(7, 0, [4, ['Date', 'D']])
        for i in (7, 6):
            self.putr(i)
        d = self.date = bcd2int(b & 0x3f)
        self.putd(5, 0, [17, ['Date: %d' % d, 'D: %d' % d, 'D']])

    def handle_reg_0x05(self, b): # Month (1-12)
        self.putd(7, 0, [5, ['Month', 'Mon', 'M']])
        for i in (7, 6, 5):
            self.putr(i)
        m = self.months = bcd2int(b & 0x1f)
        self.putd(4, 0, [18, ['Month: %d' % m, 'Mon: %d' % m, 'M: %d' % m, 'M']])

    def handle_reg_0x06(self, b): # Year (0-99)
        self.putd(7, 0, [6, ['Year', 'Y']])
        y = self.years = bcd2int(b & 0xff)
        self.years += 2000
        self.putd(7, 0, [19, ['Year: %d' % y, 'Y: %d' % y, 'Y']])

    def handle_reg_0x07(self, b): # Control Register
        self.putd(7, 0, [7, ['Control', 'Ctrl', 'C']])
        for i in (6, 5, 3, 2):
            self.putr(i)
        o = 1 if (b & (1 << 7)) else 0
        s = 1 if (b & (1 << 4)) else 0
        s2 = 'en' if (b & (1 << 4)) else 'dis'
        r = rates[b & 0x03]
        self.putd(7, 7, [20, ['Output control: %d' % o,
            'OUT: %d' % o, 'O: %d' % o, 'O']])
        self.putd(4, 4, [21, ['Square wave output: %sabled' % s2,
            'SQWE: %sabled' % s2, 'SQWE: %d' % s, 'S: %d' % s, 'S']])
        self.putd(1, 0, [22, ['Square wave output rate: %s' % r,
            'Square wave rate: %s' % r, 'SQW rate: %s' % r, 'Rate: %s' % r,
            'RS: %s' % s, 'RS', 'R']])

    def handle_reg_0x3f(self, b): # RAM (bytes 0x08-0x3f)
        self.putd(7, 0, [8, ['RAM', 'R']])
        self.putd(7, 0, [23, ['SRAM: 0x%02X' % b, '0x%02X' % b]])

    def output_datetime(self, cls, rw):
        # TODO: Handle read/write of only parts of these items.
        d = '%s, %02d.%02d.%4d %02d:%02d:%02d' % (
            days_of_week[self.days - 1], self.date, self.months,
            self.years, self.hours, self.minutes, self.seconds)
        self.put(self.ss_block, self.es, self.out_ann,
                 [cls, ['%s date/time: %s' % (rw, d)]])

    def handle_reg(self, b):
        r = self.reg if self.reg < 8 else 0x3f
        fn = getattr(self, 'handle_reg_0x%02x' % r)
        fn(b)
        # Honor address auto-increment feature of the DS1307. When the
        # address reaches 0x3f, it will wrap around to address 0.
        self.reg += 1
        if self.reg > 0x3f:
            self.reg = 0

    def is_correct_chip(self, addr):
        if addr == DS1307_I2C_ADDRESS:
            return True
        self.put(self.ss_block, self.es, self.out_ann,
                 [28, ['Ignoring non-DS1307 data (slave 0x%02X)' % addr]])
        return False

    def decode(self, ss, es, data):
        cmd, databyte = data

        # Collect the 'BITS' packet, then return. The next packet is
        # guaranteed to belong to these bits we just stored.
        if cmd == 'BITS':
            self.bits = databyte
            return

        # Store the start/end samples of this I²C packet.
        self.ss, self.es = ss, es

        # State machine.
        if self.state == 'IDLE':
            # Wait for an I²C START condition.
            if cmd != 'START':
                return
            self.state = 'GET SLAVE ADDR'
            self.ss_block = ss
        elif self.state == 'GET SLAVE ADDR':
            # Wait for an address write operation.
            if cmd != 'ADDRESS WRITE':
                return
            if not self.is_correct_chip(databyte):
                self.state = 'IDLE'
                return
            self.state = 'GET REG ADDR'
        elif self.state == 'GET REG ADDR':
            # Wait for a data write (master selects the slave register).
            if cmd != 'DATA WRITE':
                return
            self.reg = databyte
            self.state = 'WRITE RTC REGS'
        elif self.state == 'WRITE RTC REGS':
            # If we see a Repeated Start here, it's an RTC read.
            if cmd == 'START REPEAT':
                self.state = 'READ RTC REGS'
                return
            # Otherwise: Get data bytes until a STOP condition occurs.
            if cmd == 'DATA WRITE':
                self.handle_reg(databyte)
            elif cmd == 'STOP':
                self.output_datetime(25, 'Written')
                self.state = 'IDLE'
        elif self.state == 'READ RTC REGS':
            # Wait for an address read operation.
            if cmd != 'ADDRESS READ':
                return
            if not self.is_correct_chip(databyte):
                self.state = 'IDLE'
                return
            self.state = 'READ RTC REGS2'
        elif self.state == 'READ RTC REGS2':
            if cmd == 'DATA READ':
                self.handle_reg(databyte)
            elif cmd == 'STOP':
                self.output_datetime(24, 'Read')
                self.state = 'IDLE'
Commit	Line	Data
3bf68998	1	##
50bd5d25	2	## This file is part of the libsigrokdecode project.
35b380b1	3	##
5188abb9	4	## Copyright (C) 2012-2014 Uwe Hermann <uwe@hermann-uwe.de>
3bf68998 MR	5	## Copyright (C) 2013 Matt Ranostay <mranostay@gmail.com>
	6	##
	7	## This program is free software; you can redistribute it and/or modify
	8	## it under the terms of the GNU General Public License as published by
	9	## the Free Software Foundation; either version 2 of the License, or
	10	## (at your option) any later version.
	11	##
	12	## This program is distributed in the hope that it will be useful,
	13	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	## GNU General Public License for more details.
	16	##
	17	## You should have received a copy of the GNU General Public License
4539e9ca	18	## along with this program; if not, see <http://www.gnu.org/licenses/>.
3bf68998 MR	19	##
3bf68998 MR	20
5188abb9	21	import re
3bf68998	22	import sigrokdecode as srd
135b790c	23	from common.srdhelper import bcd2int
3bf68998	24
5188abb9 UH	25	days_of_week = (
	26	'Sunday', 'Monday', 'Tuesday', 'Wednesday',
	27	'Thursday', 'Friday', 'Saturday',
	28	)
	29
	30	regs = (
	31	'Seconds', 'Minutes', 'Hours', 'Day', 'Date', 'Month', 'Year',
	32	'Control', 'RAM',
	33	)
	34
	35	bits = (
	36	'Clock halt', 'Seconds', 'Reserved', 'Minutes', '12/24 hours', 'AM/PM',
	37	'Hours', 'Day', 'Date', 'Month', 'Year', 'OUT', 'SQWE', 'RS', 'RAM',
	38	)
	39
37834eed UH	40	rates = {
	41	0b00: '1Hz',
	42	0b01: '4096kHz',
	43	0b10: '8192kHz',
	44	0b11: '32768kHz',
	45	}
	46
00bdc23e UH	47	DS1307_I2C_ADDRESS = 0x68
00bdc23e UH	48
5188abb9 UH	49	def regs_and_bits():
	50	l = [('reg-' + r.lower(), r + ' register') for r in regs]
	51	l += [('bit-' + re.sub('\/\| ', '-', b).lower(), b + ' bit') for b in bits]
	52	return tuple(l)
3bf68998	53
3bf68998	54	class Decoder(srd.Decoder):
b197383c	55	api_version = 3
3bf68998 MR	56	id = 'ds1307'
	57	name = 'DS1307'
	58	longname = 'Dallas DS1307'
	59	desc = 'Realtime clock module protocol.'
	60	license = 'gplv2+'
	61	inputs = ['i2c']
	62	outputs = ['ds1307']
5188abb9 UH	63	annotations = regs_and_bits() + (
	64	('read-datetime', 'Read date/time'),
	65	('write-datetime', 'Write date/time'),
	66	('reg-read', 'Register read'),
	67	('reg-write', 'Register write'),
00bdc23e	68	('warnings', 'Warnings'),
5188abb9 UH	69	)
	70	annotation_rows = (
	71	('bits', 'Bits', tuple(range(9, 24))),
	72	('regs', 'Registers', tuple(range(9))),
	73	('date-time', 'Date/time', (24, 25, 26, 27)),
00bdc23e	74	('warnings', 'Warnings', (28,)),
da9bcbd9	75	)
3bf68998	76
92b7b49f	77	def __init__(self):
3bf68998 MR	78	self.state = 'IDLE'
	79	self.hours = -1
	80	self.minutes = -1
	81	self.seconds = -1
	82	self.days = -1
	83	self.date = -1
	84	self.months = -1
	85	self.years = -1
5188abb9	86	self.bits = []
3bf68998	87
8915b346	88	def start(self):
be465111	89	self.out_ann = self.register(srd.OUTPUT_ANN)
3bf68998	90
3bf68998 MR	91	def putx(self, data):
	92	self.put(self.ss, self.es, self.out_ann, data)
	93
5188abb9 UH	94	def putd(self, bit1, bit2, data):
	95	self.put(self.bits[bit1][1], self.bits[bit2][2], self.out_ann, data)
	96
	97	def putr(self, bit):
	98	self.put(self.bits[bit][1], self.bits[bit][2], self.out_ann,
	99	[11, ['Reserved bit', 'Reserved', 'Rsvd', 'R']])
	100
	101	def handle_reg_0x00(self, b): # Seconds (0-59) / Clock halt bit
	102	self.putd(7, 0, [0, ['Seconds', 'Sec', 'S']])
	103	ch = 1 if (b & (1 << 7)) else 0
	104	self.putd(7, 7, [9, ['Clock halt: %d' % ch, 'Clk hlt: %d' % ch,
	105	'CH: %d' % ch, 'CH']])
	106	s = self.seconds = bcd2int(b & 0x7f)
	107	self.putd(6, 0, [10, ['Second: %d' % s, 'Sec: %d' % s, 'S: %d' % s, 'S']])
	108
	109	def handle_reg_0x01(self, b): # Minutes (0-59)
	110	self.putd(7, 0, [1, ['Minutes', 'Min', 'M']])
	111	self.putr(7)
	112	m = self.minutes = bcd2int(b & 0x7f)
	113	self.putd(6, 0, [12, ['Minute: %d' % m, 'Min: %d' % m, 'M: %d' % m, 'M']])
	114
	115	def handle_reg_0x02(self, b): # Hours (1-12+AM/PM or 0-23)
	116	self.putd(7, 0, [2, ['Hours', 'H']])
	117	self.putr(7)
	118	ampm_mode = True if (b & (1 << 6)) else False
	119	if ampm_mode:
	120	self.putd(6, 6, [13, ['12-hour mode', '12h mode', '12h']])
	121	a = 'AM' if (b & (1 << 6)) else 'PM'
	122	self.putd(5, 5, [14, [a, a[0]]])
	123	h = self.hours = bcd2int(b & 0x1f)
	124	self.putd(4, 0, [15, ['Hour: %d' % h, 'H: %d' % h, 'H']])
	125	else:
	126	self.putd(6, 6, [13, ['24-hour mode', '24h mode', '24h']])
	127	h = self.hours = bcd2int(b & 0x3f)
	128	self.putd(5, 0, [15, ['Hour: %d' % h, 'H: %d' % h, 'H']])
	129
	130	def handle_reg_0x03(self, b): # Day / day of week (1-7)
	131	self.putd(7, 0, [3, ['Day of week', 'Day', 'D']])
	132	for i in (7, 6, 5, 4, 3):
	133	self.putr(i)
	134	w = self.days = bcd2int(b & 0x07)
	135	ws = days_of_week[self.days - 1]
	136	self.putd(2, 0, [16, ['Weekday: %s' % ws, 'WD: %s' % ws, 'WD', 'W']])
	137
	138	def handle_reg_0x04(self, b): # Date (1-31)
	139	self.putd(7, 0, [4, ['Date', 'D']])
	140	for i in (7, 6):
	141	self.putr(i)
	142	d = self.date = bcd2int(b & 0x3f)
	143	self.putd(5, 0, [17, ['Date: %d' % d, 'D: %d' % d, 'D']])
	144
	145	def handle_reg_0x05(self, b): # Month (1-12)
	146	self.putd(7, 0, [5, ['Month', 'Mon', 'M']])
	147	for i in (7, 6, 5):
	148	self.putr(i)
	149	m = self.months = bcd2int(b & 0x1f)
	150	self.putd(4, 0, [18, ['Month: %d' % m, 'Mon: %d' % m, 'M: %d' % m, 'M']])
	151
	152	def handle_reg_0x06(self, b): # Year (0-99)
	153	self.putd(7, 0, [6, ['Year', 'Y']])
	154	y = self.years = bcd2int(b & 0xff)
	155	self.years += 2000
	156	self.putd(7, 0, [19, ['Year: %d' % y, 'Y: %d' % y, 'Y']])
3bf68998 MR	157
3bf68998 MR	158	def handle_reg_0x07(self, b): # Control Register
37834eed UH	159	self.putd(7, 0, [7, ['Control', 'Ctrl', 'C']])
	160	for i in (6, 5, 3, 2):
	161	self.putr(i)
	162	o = 1 if (b & (1 << 7)) else 0
	163	s = 1 if (b & (1 << 4)) else 0
	164	s2 = 'en' if (b & (1 << 4)) else 'dis'
	165	r = rates[b & 0x03]
	166	self.putd(7, 7, [20, ['Output control: %d' % o,
	167	'OUT: %d' % o, 'O: %d' % o, 'O']])
	168	self.putd(4, 4, [21, ['Square wave output: %sabled' % s2,
	169	'SQWE: %sabled' % s2, 'SQWE: %d' % s, 'S: %d' % s, 'S']])
	170	self.putd(1, 0, [22, ['Square wave output rate: %s' % r,
	171	'Square wave rate: %s' % r, 'SQW rate: %s' % r, 'Rate: %s' % r,
	172	'RS: %s' % s, 'RS', 'R']])
3bf68998	173
903e9b14 UH	174	def handle_reg_0x3f(self, b): # RAM (bytes 0x08-0x3f)
	175	self.putd(7, 0, [8, ['RAM', 'R']])
	176	self.putd(7, 0, [23, ['SRAM: 0x%02X' % b, '0x%02X' % b]])
	177
53908ef1 UH	178	def output_datetime(self, cls, rw):
	179	# TODO: Handle read/write of only parts of these items.
	180	d = '%s, %02d.%02d.%4d %02d:%02d:%02d' % (
	181	days_of_week[self.days - 1], self.date, self.months,
	182	self.years, self.hours, self.minutes, self.seconds)
486b19ce	183	self.put(self.ss_block, self.es, self.out_ann,
53908ef1 UH	184	[cls, ['%s date/time: %s' % (rw, d)]])
	185
	186	def handle_reg(self, b):
	187	r = self.reg if self.reg < 8 else 0x3f
	188	fn = getattr(self, 'handle_reg_0x%02x' % r)
	189	fn(b)
7d747990 UH	190	# Honor address auto-increment feature of the DS1307. When the
7d747990 UH	191	# address reaches 0x3f, it will wrap around to address 0.
53908ef1	192	self.reg += 1
7d747990 UH	193	if self.reg > 0x3f:
7d747990 UH	194	self.reg = 0
53908ef1	195
00bdc23e UH	196	def is_correct_chip(self, addr):
	197	if addr == DS1307_I2C_ADDRESS:
	198	return True
486b19ce	199	self.put(self.ss_block, self.es, self.out_ann,
00bdc23e UH	200	[28, ['Ignoring non-DS1307 data (slave 0x%02X)' % addr]])
	201	return False
	202
3bf68998 MR	203	def decode(self, ss, es, data):
	204	cmd, databyte = data
	205
5188abb9 UH	206	# Collect the 'BITS' packet, then return. The next packet is
	207	# guaranteed to belong to these bits we just stored.
	208	if cmd == 'BITS':
	209	self.bits = databyte
	210	return
	211
00197484	212	# Store the start/end samples of this I²C packet.
3bf68998 MR	213	self.ss, self.es = ss, es
	214
	215	# State machine.
	216	if self.state == 'IDLE':
00197484	217	# Wait for an I²C START condition.
3bf68998 MR	218	if cmd != 'START':
	219	return
	220	self.state = 'GET SLAVE ADDR'
486b19ce	221	self.ss_block = ss
3bf68998 MR	222	elif self.state == 'GET SLAVE ADDR':
3bf68998 MR	223	# Wait for an address write operation.
3bf68998 MR	224	if cmd != 'ADDRESS WRITE':
3bf68998 MR	225	return
00bdc23e UH	226	if not self.is_correct_chip(databyte):
	227	self.state = 'IDLE'
	228	return
3bf68998 MR	229	self.state = 'GET REG ADDR'
	230	elif self.state == 'GET REG ADDR':
	231	# Wait for a data write (master selects the slave register).
	232	if cmd != 'DATA WRITE':
	233	return
	234	self.reg = databyte
	235	self.state = 'WRITE RTC REGS'
	236	elif self.state == 'WRITE RTC REGS':
53908ef1	237	# If we see a Repeated Start here, it's an RTC read.
3bf68998 MR	238	if cmd == 'START REPEAT':
	239	self.state = 'READ RTC REGS'
	240	return
	241	# Otherwise: Get data bytes until a STOP condition occurs.
	242	if cmd == 'DATA WRITE':
53908ef1	243	self.handle_reg(databyte)
3bf68998	244	elif cmd == 'STOP':
53908ef1	245	self.output_datetime(25, 'Written')
3bf68998	246	self.state = 'IDLE'
3bf68998 MR	247	elif self.state == 'READ RTC REGS':
3bf68998 MR	248	# Wait for an address read operation.
00bdc23e UH	249	if cmd != 'ADDRESS READ':
	250	return
	251	if not self.is_correct_chip(databyte):
	252	self.state = 'IDLE'
3bf68998	253	return
00bdc23e	254	self.state = 'READ RTC REGS2'
3bf68998 MR	255	elif self.state == 'READ RTC REGS2':
3bf68998 MR	256	if cmd == 'DATA READ':
53908ef1	257	self.handle_reg(databyte)
3bf68998	258	elif cmd == 'STOP':
53908ef1	259	self.output_datetime(24, 'Read')
3bf68998	260	self.state = 'IDLE'