[libsigrokdecode.git] / decoders / ds1307 / pd.py

##
## This file is part of the libsigrokdecode project.
##
## Copyright (C) 2012-2014 Uwe Hermann <uwe@hermann-uwe.de>
## Copyright (C) 2013 Matt Ranostay <mranostay@gmail.com>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
##

import re
import sigrokdecode as srd

days_of_week = (
    'Sunday', 'Monday', 'Tuesday', 'Wednesday',
    'Thursday', 'Friday', 'Saturday',
)

regs = (
    'Seconds', 'Minutes', 'Hours', 'Day', 'Date', 'Month', 'Year',
    'Control', 'RAM',
)

bits = (
    'Clock halt', 'Seconds', 'Reserved', 'Minutes', '12/24 hours', 'AM/PM',
    'Hours', 'Day', 'Date', 'Month', 'Year', 'OUT', 'SQWE', 'RS', 'RAM',
)

def regs_and_bits():
    l = [('reg-' + r.lower(), r + ' register') for r in regs]
    l += [('bit-' + re.sub('\/| ', '-', b).lower(), b + ' bit') for b in bits]
    return tuple(l)

# Return the specified BCD number (max. 8 bits) as integer.
def bcd2int(b):
    return (b & 0x0f) + ((b >> 4) * 10)

class Decoder(srd.Decoder):
    api_version = 2
    id = 'ds1307'
    name = 'DS1307'
    longname = 'Dallas DS1307'
    desc = 'Realtime clock module protocol.'
    license = 'gplv2+'
    inputs = ['i2c']
    outputs = ['ds1307']
    annotations =  regs_and_bits() + (
        ('read-datetime', 'Read date/time'),
        ('write-datetime', 'Write date/time'),
        ('reg-read', 'Register read'),
        ('reg-write', 'Register write'),
    )
    annotation_rows = (
        ('bits', 'Bits', tuple(range(9, 24))),
        ('regs', 'Registers', tuple(range(9))),
        ('date-time', 'Date/time', (24, 25, 26, 27)),
    )

    def __init__(self, **kwargs):
        self.state = 'IDLE'
        self.hours = -1
        self.minutes = -1
        self.seconds = -1
        self.days = -1
        self.date = -1
        self.months = -1
        self.years = -1
        self.bits = []

    def start(self):
        self.out_ann = self.register(srd.OUTPUT_ANN)

    def putx(self, data):
        self.put(self.ss, self.es, self.out_ann, data)

    def putd(self, bit1, bit2, data):
        self.put(self.bits[bit1][1], self.bits[bit2][2], self.out_ann, data)

    def putr(self, bit):
        self.put(self.bits[bit][1], self.bits[bit][2], self.out_ann,
                 [11, ['Reserved bit', 'Reserved', 'Rsvd', 'R']])

    def handle_reg_0x00(self, b): # Seconds (0-59) / Clock halt bit
        self.putd(7, 0, [0, ['Seconds', 'Sec', 'S']])
        ch = 1 if (b & (1 << 7)) else 0
        self.putd(7, 7, [9, ['Clock halt: %d' % ch, 'Clk hlt: %d' % ch,
                        'CH: %d' % ch, 'CH']])
        s = self.seconds = bcd2int(b & 0x7f)
        self.putd(6, 0, [10, ['Second: %d' % s, 'Sec: %d' % s, 'S: %d' % s, 'S']])

    def handle_reg_0x01(self, b): # Minutes (0-59)
        self.putd(7, 0, [1, ['Minutes', 'Min', 'M']])
        self.putr(7)
        m = self.minutes = bcd2int(b & 0x7f)
        self.putd(6, 0, [12, ['Minute: %d' % m, 'Min: %d' % m, 'M: %d' % m, 'M']])

    def handle_reg_0x02(self, b): # Hours (1-12+AM/PM or 0-23)
        self.putd(7, 0, [2, ['Hours', 'H']])
        self.putr(7)
        ampm_mode = True if (b & (1 << 6)) else False
        if ampm_mode:
            self.putd(6, 6, [13, ['12-hour mode', '12h mode', '12h']])
            a = 'AM' if (b & (1 << 6)) else 'PM'
            self.putd(5, 5, [14, [a, a[0]]])
            h = self.hours = bcd2int(b & 0x1f)
            self.putd(4, 0, [15, ['Hour: %d' % h, 'H: %d' % h, 'H']])
        else:
            self.putd(6, 6, [13, ['24-hour mode', '24h mode', '24h']])
            h = self.hours = bcd2int(b & 0x3f)
            self.putd(5, 0, [15, ['Hour: %d' % h, 'H: %d' % h, 'H']])

    def handle_reg_0x03(self, b): # Day / day of week (1-7)
        self.putd(7, 0, [3, ['Day of week', 'Day', 'D']])
        for i in (7, 6, 5, 4, 3):
            self.putr(i)
        w = self.days = bcd2int(b & 0x07)
        ws = days_of_week[self.days - 1]
        self.putd(2, 0, [16, ['Weekday: %s' % ws, 'WD: %s' % ws, 'WD', 'W']])

    def handle_reg_0x04(self, b): # Date (1-31)
        self.putd(7, 0, [4, ['Date', 'D']])
        for i in (7, 6):
            self.putr(i)
        d = self.date = bcd2int(b & 0x3f)
        self.putd(5, 0, [17, ['Date: %d' % d, 'D: %d' % d, 'D']])

    def handle_reg_0x05(self, b): # Month (1-12)
        self.putd(7, 0, [5, ['Month', 'Mon', 'M']])
        for i in (7, 6, 5):
            self.putr(i)
        m = self.months = bcd2int(b & 0x1f)
        self.putd(4, 0, [18, ['Month: %d' % m, 'Mon: %d' % m, 'M: %d' % m, 'M']])

    def handle_reg_0x06(self, b): # Year (0-99)
        self.putd(7, 0, [6, ['Year', 'Y']])
        y = self.years = bcd2int(b & 0xff)
        self.years += 2000
        self.putd(7, 0, [19, ['Year: %d' % y, 'Y: %d' % y, 'Y']])

    def handle_reg_0x07(self, b): # Control Register
        pass

    def decode(self, ss, es, data):
        cmd, databyte = data

        # Collect the 'BITS' packet, then return. The next packet is
        # guaranteed to belong to these bits we just stored.
        if cmd == 'BITS':
            self.bits = databyte
            return

        # Store the start/end samples of this I²C packet.
        self.ss, self.es = ss, es

        # State machine.
        if self.state == 'IDLE':
            # Wait for an I²C START condition.
            if cmd != 'START':
                return
            self.state = 'GET SLAVE ADDR'
            self.block_start_sample = ss
        elif self.state == 'GET SLAVE ADDR':
            # Wait for an address write operation.
            # TODO: We should only handle packets to the RTC slave (0x68).
            if cmd != 'ADDRESS WRITE':
                return
            self.state = 'GET REG ADDR'
        elif self.state == 'GET REG ADDR':
            # Wait for a data write (master selects the slave register).
            if cmd != 'DATA WRITE':
                return
            self.reg = databyte
            self.state = 'WRITE RTC REGS'
        elif self.state == 'WRITE RTC REGS':
            # If we see a Repeated Start here, it's probably an RTC read.
            if cmd == 'START REPEAT':
                self.state = 'READ RTC REGS'
                return
            # Otherwise: Get data bytes until a STOP condition occurs.
            if cmd == 'DATA WRITE':
                handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
                handle_reg(databyte)
                self.reg += 1
                # TODO: Check for NACK!
            elif cmd == 'STOP':
                # TODO: Handle read/write of only parts of these items.
                d = '%s, %02d.%02d.%4d %02d:%02d:%02d' % (
                    days_of_week[self.days - 1], self.date, self.months,
                    self.years, self.hours, self.minutes, self.seconds)
                self.put(self.block_start_sample, es, self.out_ann,
                         [25, ['Written date/time: %s' % d]])
                self.state = 'IDLE'
            else:
                pass # TODO
        elif self.state == 'READ RTC REGS':
            # Wait for an address read operation.
            # TODO: We should only handle packets to the RTC slave (0x68).
            if cmd == 'ADDRESS READ':
                self.state = 'READ RTC REGS2'
                return
            else:
                pass # TODO
        elif self.state == 'READ RTC REGS2':
            if cmd == 'DATA READ':
                handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
                handle_reg(databyte)
                self.reg += 1
                # TODO: Check for NACK!
            elif cmd == 'STOP':
                d = '%s, %02d.%02d.%4d %02d:%02d:%02d' % (
                    days_of_week[self.days - 1], self.date, self.months,
                    self.years, self.hours, self.minutes, self.seconds)
                self.put(self.block_start_sample, es, self.out_ann,
                         [24, ['Read date/time: %s' % d]])
                self.state = 'IDLE'
            else:
                pass # TODO?
Commit	Line	Data
3bf68998	1	##
50bd5d25	2	## This file is part of the libsigrokdecode project.
35b380b1	3	##
5188abb9	4	## Copyright (C) 2012-2014 Uwe Hermann <uwe@hermann-uwe.de>
3bf68998 MR	5	## Copyright (C) 2013 Matt Ranostay <mranostay@gmail.com>
	6	##
	7	## This program is free software; you can redistribute it and/or modify
	8	## it under the terms of the GNU General Public License as published by
	9	## the Free Software Foundation; either version 2 of the License, or
	10	## (at your option) any later version.
	11	##
	12	## This program is distributed in the hope that it will be useful,
	13	## but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	## GNU General Public License for more details.
	16	##
	17	## You should have received a copy of the GNU General Public License
	18	## along with this program; if not, write to the Free Software
	19	## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
	20	##
	21
5188abb9	22	import re
3bf68998 MR	23	import sigrokdecode as srd
3bf68998 MR	24
5188abb9 UH	25	days_of_week = (
	26	'Sunday', 'Monday', 'Tuesday', 'Wednesday',
	27	'Thursday', 'Friday', 'Saturday',
	28	)
	29
	30	regs = (
	31	'Seconds', 'Minutes', 'Hours', 'Day', 'Date', 'Month', 'Year',
	32	'Control', 'RAM',
	33	)
	34
	35	bits = (
	36	'Clock halt', 'Seconds', 'Reserved', 'Minutes', '12/24 hours', 'AM/PM',
	37	'Hours', 'Day', 'Date', 'Month', 'Year', 'OUT', 'SQWE', 'RS', 'RAM',
	38	)
	39
	40	def regs_and_bits():
	41	l = [('reg-' + r.lower(), r + ' register') for r in regs]
	42	l += [('bit-' + re.sub('\/\| ', '-', b).lower(), b + ' bit') for b in bits]
	43	return tuple(l)
3bf68998 MR	44
	45	# Return the specified BCD number (max. 8 bits) as integer.
	46	def bcd2int(b):
	47	return (b & 0x0f) + ((b >> 4) * 10)
	48
	49	class Decoder(srd.Decoder):
12851357	50	api_version = 2
3bf68998 MR	51	id = 'ds1307'
	52	name = 'DS1307'
	53	longname = 'Dallas DS1307'
	54	desc = 'Realtime clock module protocol.'
	55	license = 'gplv2+'
	56	inputs = ['i2c']
	57	outputs = ['ds1307']
5188abb9 UH	58	annotations = regs_and_bits() + (
	59	('read-datetime', 'Read date/time'),
	60	('write-datetime', 'Write date/time'),
	61	('reg-read', 'Register read'),
	62	('reg-write', 'Register write'),
	63	)
	64	annotation_rows = (
	65	('bits', 'Bits', tuple(range(9, 24))),
	66	('regs', 'Registers', tuple(range(9))),
	67	('date-time', 'Date/time', (24, 25, 26, 27)),
da9bcbd9	68	)
3bf68998 MR	69
	70	def __init__(self, **kwargs):
	71	self.state = 'IDLE'
	72	self.hours = -1
	73	self.minutes = -1
	74	self.seconds = -1
	75	self.days = -1
	76	self.date = -1
	77	self.months = -1
	78	self.years = -1
5188abb9	79	self.bits = []
3bf68998	80
8915b346	81	def start(self):
be465111	82	self.out_ann = self.register(srd.OUTPUT_ANN)
3bf68998	83
3bf68998 MR	84	def putx(self, data):
	85	self.put(self.ss, self.es, self.out_ann, data)
	86
5188abb9 UH	87	def putd(self, bit1, bit2, data):
	88	self.put(self.bits[bit1][1], self.bits[bit2][2], self.out_ann, data)
	89
	90	def putr(self, bit):
	91	self.put(self.bits[bit][1], self.bits[bit][2], self.out_ann,
	92	[11, ['Reserved bit', 'Reserved', 'Rsvd', 'R']])
	93
	94	def handle_reg_0x00(self, b): # Seconds (0-59) / Clock halt bit
	95	self.putd(7, 0, [0, ['Seconds', 'Sec', 'S']])
	96	ch = 1 if (b & (1 << 7)) else 0
	97	self.putd(7, 7, [9, ['Clock halt: %d' % ch, 'Clk hlt: %d' % ch,
	98	'CH: %d' % ch, 'CH']])
	99	s = self.seconds = bcd2int(b & 0x7f)
	100	self.putd(6, 0, [10, ['Second: %d' % s, 'Sec: %d' % s, 'S: %d' % s, 'S']])
	101
	102	def handle_reg_0x01(self, b): # Minutes (0-59)
	103	self.putd(7, 0, [1, ['Minutes', 'Min', 'M']])
	104	self.putr(7)
	105	m = self.minutes = bcd2int(b & 0x7f)
	106	self.putd(6, 0, [12, ['Minute: %d' % m, 'Min: %d' % m, 'M: %d' % m, 'M']])
	107
	108	def handle_reg_0x02(self, b): # Hours (1-12+AM/PM or 0-23)
	109	self.putd(7, 0, [2, ['Hours', 'H']])
	110	self.putr(7)
	111	ampm_mode = True if (b & (1 << 6)) else False
	112	if ampm_mode:
	113	self.putd(6, 6, [13, ['12-hour mode', '12h mode', '12h']])
	114	a = 'AM' if (b & (1 << 6)) else 'PM'
	115	self.putd(5, 5, [14, [a, a[0]]])
	116	h = self.hours = bcd2int(b & 0x1f)
	117	self.putd(4, 0, [15, ['Hour: %d' % h, 'H: %d' % h, 'H']])
	118	else:
	119	self.putd(6, 6, [13, ['24-hour mode', '24h mode', '24h']])
	120	h = self.hours = bcd2int(b & 0x3f)
	121	self.putd(5, 0, [15, ['Hour: %d' % h, 'H: %d' % h, 'H']])
	122
	123	def handle_reg_0x03(self, b): # Day / day of week (1-7)
	124	self.putd(7, 0, [3, ['Day of week', 'Day', 'D']])
	125	for i in (7, 6, 5, 4, 3):
	126	self.putr(i)
	127	w = self.days = bcd2int(b & 0x07)
	128	ws = days_of_week[self.days - 1]
	129	self.putd(2, 0, [16, ['Weekday: %s' % ws, 'WD: %s' % ws, 'WD', 'W']])
	130
	131	def handle_reg_0x04(self, b): # Date (1-31)
	132	self.putd(7, 0, [4, ['Date', 'D']])
	133	for i in (7, 6):
	134	self.putr(i)
	135	d = self.date = bcd2int(b & 0x3f)
	136	self.putd(5, 0, [17, ['Date: %d' % d, 'D: %d' % d, 'D']])
	137
	138	def handle_reg_0x05(self, b): # Month (1-12)
	139	self.putd(7, 0, [5, ['Month', 'Mon', 'M']])
	140	for i in (7, 6, 5):
	141	self.putr(i)
	142	m = self.months = bcd2int(b & 0x1f)
	143	self.putd(4, 0, [18, ['Month: %d' % m, 'Mon: %d' % m, 'M: %d' % m, 'M']])
	144
	145	def handle_reg_0x06(self, b): # Year (0-99)
	146	self.putd(7, 0, [6, ['Year', 'Y']])
	147	y = self.years = bcd2int(b & 0xff)
	148	self.years += 2000
	149	self.putd(7, 0, [19, ['Year: %d' % y, 'Y: %d' % y, 'Y']])
3bf68998 MR	150
	151	def handle_reg_0x07(self, b): # Control Register
	152	pass
	153
	154	def decode(self, ss, es, data):
	155	cmd, databyte = data
	156
5188abb9 UH	157	# Collect the 'BITS' packet, then return. The next packet is
	158	# guaranteed to belong to these bits we just stored.
	159	if cmd == 'BITS':
	160	self.bits = databyte
	161	return
	162
00197484	163	# Store the start/end samples of this I²C packet.
3bf68998 MR	164	self.ss, self.es = ss, es
	165
	166	# State machine.
	167	if self.state == 'IDLE':
00197484	168	# Wait for an I²C START condition.
3bf68998 MR	169	if cmd != 'START':
	170	return
	171	self.state = 'GET SLAVE ADDR'
	172	self.block_start_sample = ss
	173	elif self.state == 'GET SLAVE ADDR':
	174	# Wait for an address write operation.
	175	# TODO: We should only handle packets to the RTC slave (0x68).
	176	if cmd != 'ADDRESS WRITE':
	177	return
	178	self.state = 'GET REG ADDR'
	179	elif self.state == 'GET REG ADDR':
	180	# Wait for a data write (master selects the slave register).
	181	if cmd != 'DATA WRITE':
	182	return
	183	self.reg = databyte
	184	self.state = 'WRITE RTC REGS'
	185	elif self.state == 'WRITE RTC REGS':
	186	# If we see a Repeated Start here, it's probably an RTC read.
	187	if cmd == 'START REPEAT':
	188	self.state = 'READ RTC REGS'
	189	return
	190	# Otherwise: Get data bytes until a STOP condition occurs.
	191	if cmd == 'DATA WRITE':
	192	handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
	193	handle_reg(databyte)
	194	self.reg += 1
	195	# TODO: Check for NACK!
	196	elif cmd == 'STOP':
	197	# TODO: Handle read/write of only parts of these items.
5188abb9	198	d = '%s, %02d.%02d.%4d %02d:%02d:%02d' % (
8b97d010 UH	199	days_of_week[self.days - 1], self.date, self.months,
8b97d010 UH	200	self.years, self.hours, self.minutes, self.seconds)
3bf68998	201	self.put(self.block_start_sample, es, self.out_ann,
5188abb9	202	[25, ['Written date/time: %s' % d]])
3bf68998 MR	203	self.state = 'IDLE'
	204	else:
	205	pass # TODO
	206	elif self.state == 'READ RTC REGS':
	207	# Wait for an address read operation.
	208	# TODO: We should only handle packets to the RTC slave (0x68).
	209	if cmd == 'ADDRESS READ':
	210	self.state = 'READ RTC REGS2'
	211	return
	212	else:
	213	pass # TODO
	214	elif self.state == 'READ RTC REGS2':
	215	if cmd == 'DATA READ':
	216	handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
	217	handle_reg(databyte)
	218	self.reg += 1
	219	# TODO: Check for NACK!
	220	elif cmd == 'STOP':
5188abb9	221	d = '%s, %02d.%02d.%4d %02d:%02d:%02d' % (
8b97d010 UH	222	days_of_week[self.days - 1], self.date, self.months,
8b97d010 UH	223	self.years, self.hours, self.minutes, self.seconds)
3bf68998	224	self.put(self.block_start_sample, es, self.out_ann,
5188abb9	225	[24, ['Read date/time: %s' % d]])
3bf68998 MR	226	self.state = 'IDLE'
	227	else:
	228	pass # TODO?