]> sigrok.org Git - libsigrok.git/commitdiff
dslogic: Implement continuous mode
authorDiego Asanza <redacted>
Fri, 6 May 2016 22:12:09 +0000 (00:12 +0200)
committerUwe Hermann <redacted>
Mon, 16 May 2016 16:18:58 +0000 (18:18 +0200)
For low sampling speeds (up to 25MHz) DSLogic offers a streaming mode where
samples are sent directly to the USB interface, like a fx2lafw device.

For high sampling speeds (up to 400MHz) only buffer mode is supported.

This commit allows the user to set which mode should be used. The configuration
is done by using SR_CONF_CONTINUOUS.

Signed-off-by: Diego Asanza <redacted>
src/hardware/fx2lafw/api.c
src/hardware/fx2lafw/dslogic.c
src/hardware/fx2lafw/protocol.c
src/hardware/fx2lafw/protocol.h

index ffb1cf1ed14b8d8d40eb4909807fcaeae7f7aa0c..6e8eff4e5aa8c7a8b91089fde584aff2eed6ffaa 100644 (file)
@@ -135,7 +135,7 @@ static const uint32_t devopts[] = {
 };
 
 static const uint32_t dslogic_devopts[] = {
-       SR_CONF_CONTINUOUS | SR_CONF_SET,
+       SR_CONF_CONTINUOUS | SR_CONF_SET | SR_CONF_GET,
        SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
        SR_CONF_VOLTAGE_THRESHOLD | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
        SR_CONF_CONN | SR_CONF_GET,
@@ -571,6 +571,9 @@ static int config_get(uint32_t key, GVariant **data, const struct sr_dev_inst *s
        case SR_CONF_EXTERNAL_CLOCK:
                *data = g_variant_new_boolean(devc->dslogic_external_clock);
                break;
+       case SR_CONF_CONTINUOUS:
+               *data = g_variant_new_boolean(devc->dslogic_continuous_mode);
+               break;
        default:
                return SR_ERR_NA;
        }
@@ -639,6 +642,9 @@ static int config_set(uint32_t key, GVariant *data, const struct sr_dev_inst *sd
        case SR_CONF_EXTERNAL_CLOCK:
                devc->dslogic_external_clock = g_variant_get_boolean(data);
                break;
+       case SR_CONF_CONTINUOUS:
+               devc->dslogic_continuous_mode = g_variant_get_boolean(data);
+               break;
        default:
                ret = SR_ERR_NA;
        }
index afd11a7d39404a0e62dc8ba7e7d22385bb155c4f..992a07a50febf4d08a4f162fd4fe60c12dffda89 100644 (file)
@@ -332,7 +332,7 @@ SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
         * 13   1 = loopback test mode
         * 12   1 = stream mode
         * 11   1 = serial trigger
-        * 8-12 unused
+        * 8-10 unused
         * 7    1 = analog mode
         * 6    1 = samplerate 400MHz
         * 5    1 = samplerate 200MHz or analog mode
@@ -348,6 +348,8 @@ SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
                v16 = 1 << 14;
        else if (devc->dslogic_mode == DS_OP_LOOPBACK_TEST)
                v16 = 1 << 13;
+       if (devc->dslogic_continuous_mode)
+               v16 |= 1 << 12;
        if (devc->dslogic_external_clock)
                v16 |= 1 << 1;
 
index f028d132711221301857b94eae5f1a85353e823d..5113462931d7fe46f0e9326c187be0e2b7ab2634 100644 (file)
@@ -306,6 +306,7 @@ SR_PRIV struct dev_context *fx2lafw_dev_new(void)
        devc->limit_samples = 0;
        devc->capture_ratio = 0;
        devc->sample_wide = FALSE;
+       devc->dslogic_continuous_mode = FALSE;
        devc->stl = NULL;
 
        return devc;
index a02c697f9c2708660428377464a06ed6f134f5d2..b9ceebb76ecd8834631b789d57fe2477c27f081a 100644 (file)
@@ -136,6 +136,7 @@ struct dev_context {
        uint16_t dslogic_mode;
        uint32_t trigger_pos;
        gboolean dslogic_external_clock;
+       gboolean dslogic_continuous_mode;
        int dslogic_voltage_threshold;
 };