src/hardware/zeroplus-logic-cube/analyzer.c

   1 /*
   2  * This file is part of the libsigrok project.
   3  *
   4  * Copyright (C) 2010 Sven Peter <sven@fail0verflow.com>
   5  * Copyright (C) 2010 Haxx Enterprises <bushing@gmail.com>
   6  * All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or
   9  * without modification, are permitted provided that the following
  10  * conditions are met:
  11  *
  12  * * Redistributions of source code must retain the above copyright notice,
  13  *   this list of conditions and the following disclaimer.
  14  *
  15  * * Redistributions in binary form must reproduce the above copyright notice,
  16  *   this list of conditions and the following disclaimer in the documentation
  17  *   and/or other materials provided with the distribution.
  18  *
  19  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
  23  *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  29  *  THE POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 #include <config.h>
  33 #include <assert.h>
  34 #include <libsigrok/libsigrok.h>
  35 #include "libsigrok-internal.h"
  36 #include "analyzer.h"
  37 #include "gl_usb.h"
  38 #include "protocol.h"
  39
  40 enum {
  41         HARD_DATA_CHECK_SUM             = 0x00,
  42         PASS_WORD,
  43
  44         DEV_ID0                         = 0x10,
  45         DEV_ID1,
  46
  47         START_STATUS                    = 0x20,
  48         DEV_STATUS                      = 0x21,
  49         FREQUENCY_REG0                  = 0x30,
  50         FREQUENCY_REG1,
  51         FREQUENCY_REG2,
  52         FREQUENCY_REG3,
  53         FREQUENCY_REG4,
  54         MEMORY_LENGTH,
  55         CLOCK_SOURCE,
  56
  57         TRIGGER_STATUS0                 = 0x40,
  58         TRIGGER_STATUS1,
  59         TRIGGER_STATUS2,
  60         TRIGGER_STATUS3,
  61         TRIGGER_STATUS4,
  62         TRIGGER_STATUS5,
  63         TRIGGER_STATUS6,
  64         TRIGGER_STATUS7,
  65         TRIGGER_EDGE,
  66
  67         TRIGGER_COUNT0                  = 0x50,
  68         TRIGGER_COUNT1,
  69
  70         TRIGGER_LEVEL0                  = 0x55,
  71         TRIGGER_LEVEL1,
  72         TRIGGER_LEVEL2,
  73         TRIGGER_LEVEL3,
  74
  75         RAMSIZE_TRIGGERBAR_ADDRESS0     = 0x60,
  76         RAMSIZE_TRIGGERBAR_ADDRESS1,
  77         RAMSIZE_TRIGGERBAR_ADDRESS2,
  78         TRIGGERBAR_ADDRESS0,
  79         TRIGGERBAR_ADDRESS1,
  80         TRIGGERBAR_ADDRESS2,
  81         DONT_CARE_TRIGGERBAR,
  82
  83         FILTER_ENABLE                   = 0x70,
  84         FILTER_STATUS,
  85
  86         ENABLE_DELAY_TIME0              = 0x7a,
  87         ENABLE_DELAY_TIME1,
  88
  89         ENABLE_INSERT_DATA0             = 0x80,
  90         ENABLE_INSERT_DATA1,
  91         ENABLE_INSERT_DATA2,
  92         ENABLE_INSERT_DATA3,
  93         COMPRESSION_TYPE0,
  94         COMPRESSION_TYPE1,
  95
  96         TRIGGER_ADDRESS0                = 0x90,
  97         TRIGGER_ADDRESS1,
  98         TRIGGER_ADDRESS2,
  99
 100         NOW_ADDRESS0                    = 0x96,
 101         NOW_ADDRESS1,
 102         NOW_ADDRESS2,
 103
 104         STOP_ADDRESS0                   = 0x9b,
 105         STOP_ADDRESS1,
 106         STOP_ADDRESS2,
 107
 108         READ_RAM_STATUS                 = 0xa0,
 109 };
 110
 111 static int g_trigger_status[8] = { 0 };
 112 static int g_trigger_edge = 0;
 113 static int g_trigger_count = 1;
 114 static int g_filter_status[8] = { 0 };
 115 static int g_filter_enable = 0;
 116
 117 static int g_freq_value = 1;
 118 static int g_freq_scale = FREQ_SCALE_MHZ;
 119 static int g_memory_size = MEMORY_SIZE_8K;
 120 static int g_ramsize_triggerbar_addr = 2 * 1024;
 121 static int g_triggerbar_addr = 0;
 122 static int g_compression = COMPRESSION_NONE;
 123 static int g_thresh = 0x31; /* 1.5V */
 124
 125 /* Maybe unk specifies an "endpoint" or "register" of sorts. */
 126 static int analyzer_write_status(libusb_device_handle *devh, unsigned char unk,
 127                                  unsigned char flags)
 128 {
 129         assert(unk <= 3);
 130         return gl_reg_write(devh, START_STATUS, unk << 6 | flags);
 131 }
 132
 133 #if 0
 134 static int __analyzer_set_freq(libusb_device_handle *devh, int freq, int scale)
 135 {
 136         int reg0 = 0, divisor = 0, reg2 = 0;
 137
 138         switch (scale) {
 139         case FREQ_SCALE_MHZ: /* MHz */
 140                 if (freq >= 100 && freq <= 200) {
 141                         reg0 = freq * 0.1;
 142                         divisor = 1;
 143                         reg2 = 0;
 144                         break;
 145                 }
 146                 if (freq >= 50 && freq < 100) {
 147                         reg0 = freq * 0.2;
 148                         divisor = 2;
 149                         reg2 = 0;
 150                         break;
 151                 }
 152                 if (freq >= 10 && freq < 50) {
 153                         if (freq == 25) {
 154                                 reg0 = 25;
 155                                 divisor = 5;
 156                                 reg2 = 1;
 157                                 break;
 158                         } else {
 159                                 reg0 = freq * 0.5;
 160                                 divisor = 5;
 161                                 reg2 = 1;
 162                                 break;
 163                         }
 164                 }
 165                 if (freq >= 2 && freq < 10) {
 166                         divisor = 5;
 167                         reg0 = freq * 2;
 168                         reg2 = 2;
 169                         break;
 170                 }
 171                 if (freq == 1) {
 172                         divisor = 5;
 173                         reg2 = 16;
 174                         reg0 = 5;
 175                         break;
 176                 }
 177                 divisor = 5;
 178                 reg0 = 5;
 179                 reg2 = 64;
 180                 break;
 181         case FREQ_SCALE_HZ: /* Hz */
 182                 if (freq >= 500 && freq < 1000) {
 183                         reg0 = freq * 0.01;
 184                         divisor = 10;
 185                         reg2 = 64;
 186                         break;
 187                 }
 188                 if (freq >= 300 && freq < 500) {
 189                         reg0 = freq * 0.005 * 8;
 190                         divisor = 5;
 191                         reg2 = 67;
 192                         break;
 193                 }
 194                 if (freq >= 100 && freq < 300) {
 195                         reg0 = freq * 0.005 * 16;
 196                         divisor = 5;
 197                         reg2 = 68;
 198                         break;
 199                 }
 200                 divisor = 5;
 201                 reg0 = 5;
 202                 reg2 = 64;
 203                 break;
 204         case FREQ_SCALE_KHZ: /* kHz */
 205                 if (freq >= 500 && freq < 1000) {
 206                         reg0 = freq * 0.01;
 207                         divisor = 5;
 208                         reg2 = 17;
 209                         break;
 210                 }
 211                 if (freq >= 100 && freq < 500) {
 212                         reg0 = freq * 0.05;
 213                         divisor = 5;
 214                         reg2 = 32;
 215                         break;
 216                 }
 217                 if (freq >= 50 && freq < 100) {
 218                         reg0 = freq * 0.1;
 219                         divisor = 5;
 220                         reg2 = 33;
 221                         break;
 222                 }
 223                 if (freq >= 10 && freq < 50) {
 224                         if (freq == 25) {
 225                                 reg0 = 25;
 226                                 divisor = 5;
 227                                 reg2 = 49;
 228                                 break;
 229                         }
 230                         reg0 = freq * 0.5;
 231                         divisor = 5;
 232                         reg2 = 48;
 233                         break;
 234                 }
 235                 if (freq >= 2 && freq < 10) {
 236                         divisor = 5;
 237                         reg0 = freq * 2;
 238                         reg2 = 50;
 239                         break;
 240                 }
 241                 divisor = 5;
 242                 reg0 = 5;
 243                 reg2 = 64;
 244                 break;
 245         default:
 246                 divisor = 5;
 247                 reg0 = 5;
 248                 reg2 = 64;
 249                 break;
 250         }
 251
 252         sr_dbg("Setting samplerate regs (freq=%d, scale=%d): "
 253                "reg0: %d, reg1: %d, reg2: %d, reg3: %d.",
 254                freq, scale, divisor, reg0, 0x02, reg2);
 255
 256         if (gl_reg_write(devh, FREQUENCY_REG0, divisor) < 0)
 257                 return -1; /* Divisor maybe? */
 258
 259         if (gl_reg_write(devh, FREQUENCY_REG1, reg0) < 0)
 260                 return -1; /* 10 / 0.2 */
 261
 262         if (gl_reg_write(devh, FREQUENCY_REG2, 0x02) < 0)
 263                 return -1; /* Always 2 */
 264
 265         if (gl_reg_write(devh, FREQUENCY_REG4, reg2) < 0)
 266                 return -1;
 267
 268         return 0;
 269 }
 270 #endif
 271
 272 /*
 273  * It seems that ...
 274  *      FREQUENCT_REG0 - division factor (?)
 275  *      FREQUENCT_REG1 - multiplication factor (?)
 276  *      FREQUENCT_REG4 - clock selection (?)
 277  *
 278  *      clock selection
 279  *      0  10MHz  16   1MHz  32 100kHz  48  10kHz  64   1kHz
 280  *      1   5MHz  17 500kHz  33  50kHz  49   5kHz  65  500Hz
 281  *      2 2.5MHz   .          .         50 2.5kHz  66  250Hz
 282  *      .          .          .          .         67  125Hz
 283  *      .          .          .          .         68 62.5Hz
 284  */
 285 static int __analyzer_set_freq(libusb_device_handle *devh, int freq, int scale)
 286 {
 287         struct freq_factor {
 288                 int freq;
 289                 int scale;
 290                 int sel;
 291                 int div;
 292                 int mul;
 293         };
 294
 295         static const struct freq_factor f[] = {
 296                 { 200, FREQ_SCALE_MHZ,  0,  1, 20 },
 297                 { 150, FREQ_SCALE_MHZ,  0,  1, 15 },
 298                 { 100, FREQ_SCALE_MHZ,  0,  1, 10 },
 299                 {  80, FREQ_SCALE_MHZ,  0,  2, 16 },
 300                 {  50, FREQ_SCALE_MHZ,  0,  2, 10 },
 301                 {  25, FREQ_SCALE_MHZ,  1,  5, 25 },
 302                 {  10, FREQ_SCALE_MHZ,  1,  5, 10 },
 303                 {   1, FREQ_SCALE_MHZ, 16,  5,  5 },
 304                 { 800, FREQ_SCALE_KHZ, 17,  5,  8 },
 305                 { 400, FREQ_SCALE_KHZ, 32,  5, 20 },
 306                 { 200, FREQ_SCALE_KHZ, 32,  5, 10 },
 307                 { 100, FREQ_SCALE_KHZ, 32,  5,  5 },
 308                 {  50, FREQ_SCALE_KHZ, 33,  5,  5 },
 309                 {  25, FREQ_SCALE_KHZ, 49,  5, 25 },
 310                 {   5, FREQ_SCALE_KHZ, 50,  5, 10 },
 311                 {   1, FREQ_SCALE_KHZ, 64,  5,  5 },
 312                 { 500, FREQ_SCALE_HZ,  64, 10,  5 },
 313                 { 100, FREQ_SCALE_HZ,  68,  5,  8 },
 314                 ALL_ZERO
 315         };
 316
 317         int i;
 318
 319         for (i = 0; f[i].freq; i++) {
 320                 if (scale == f[i].scale && freq == f[i].freq)
 321                         break;
 322         }
 323         if (!f[i].freq)
 324                 return -1;
 325
 326         sr_dbg("Setting samplerate regs (freq=%d, scale=%d): "
 327                "reg0: %d, reg1: %d, reg2: %d, reg3: %d.",
 328                freq, scale, f[i].div, f[i].mul, 0x02, f[i].sel);
 329
 330         if (gl_reg_write(devh, FREQUENCY_REG0, f[i].div) < 0)
 331                 return -1;
 332
 333         if (gl_reg_write(devh, FREQUENCY_REG1, f[i].mul) < 0)
 334                 return -1;
 335
 336         if (gl_reg_write(devh, FREQUENCY_REG2, 0x02) < 0)
 337                 return -1;
 338
 339         if (gl_reg_write(devh, FREQUENCY_REG4, f[i].sel) < 0)
 340                 return -1;
 341
 342         return 0;
 343 }
 344
 345 static void __analyzer_set_ramsize_trigger_address(libusb_device_handle *devh,
 346                                                    unsigned int address)
 347 {
 348         gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
 349         gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
 350         gl_reg_write(devh, RAMSIZE_TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
 351 }
 352
 353 static void __analyzer_set_triggerbar_address(libusb_device_handle *devh,
 354                                               unsigned int address)
 355 {
 356         gl_reg_write(devh, TRIGGERBAR_ADDRESS0, (address >> 0) & 0xFF);
 357         gl_reg_write(devh, TRIGGERBAR_ADDRESS1, (address >> 8) & 0xFF);
 358         gl_reg_write(devh, TRIGGERBAR_ADDRESS2, (address >> 16) & 0xFF);
 359 }
 360
 361 static void __analyzer_set_compression(libusb_device_handle *devh,
 362                                        unsigned int type)
 363 {
 364         gl_reg_write(devh, COMPRESSION_TYPE0, (type >> 0) & 0xFF);
 365         gl_reg_write(devh, COMPRESSION_TYPE1, (type >> 8) & 0xFF);
 366 }
 367
 368 static void __analyzer_set_trigger_count(libusb_device_handle *devh,
 369                                          unsigned int count)
 370 {
 371         gl_reg_write(devh, TRIGGER_COUNT0, (count >> 0) & 0xFF);
 372         gl_reg_write(devh, TRIGGER_COUNT1, (count >> 8) & 0xFF);
 373 }
 374
 375 static void analyzer_write_enable_insert_data(libusb_device_handle *devh)
 376 {
 377         gl_reg_write(devh, ENABLE_INSERT_DATA0, 0x12);
 378         gl_reg_write(devh, ENABLE_INSERT_DATA1, 0x34);
 379         gl_reg_write(devh, ENABLE_INSERT_DATA2, 0x56);
 380         gl_reg_write(devh, ENABLE_INSERT_DATA3, 0x78);
 381 }
 382
 383 static void analyzer_set_filter(libusb_device_handle *devh)
 384 {
 385         int i;
 386         gl_reg_write(devh, FILTER_ENABLE, g_filter_enable);
 387         for (i = 0; i < 8; i++)
 388                 gl_reg_write(devh, FILTER_STATUS + i, g_filter_status[i]);
 389 }
 390
 391 SR_PRIV void analyzer_reset(libusb_device_handle *devh)
 392 {
 393         analyzer_write_status(devh, 3, STATUS_FLAG_NONE);       // reset device
 394         analyzer_write_status(devh, 3, STATUS_FLAG_RESET);      // reset device
 395 }
 396
 397 SR_PRIV void analyzer_initialize(libusb_device_handle *devh)
 398 {
 399         analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
 400         analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
 401         analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
 402 }
 403
 404 SR_PRIV void analyzer_wait(libusb_device_handle *devh, int set, int unset)
 405 {
 406         int status;
 407
 408         while (1) {
 409                 status = gl_reg_read(devh, DEV_STATUS);
 410                 if ((!set || (status & set)) && ((status & unset) == 0))
 411                         return;
 412         }
 413 }
 414
 415 SR_PRIV void analyzer_read_start(libusb_device_handle *devh)
 416 {
 417         analyzer_write_status(devh, 3, STATUS_FLAG_20 | STATUS_FLAG_READ);
 418
 419         /* Prep for bulk reads */
 420         gl_reg_read_buf(devh, READ_RAM_STATUS, NULL, 0);
 421 }
 422
 423 SR_PRIV int analyzer_read_data(libusb_device_handle *devh, void *buffer,
 424                 unsigned int size)
 425 {
 426         return gl_read_bulk(devh, buffer, size);
 427 }
 428
 429 SR_PRIV void analyzer_read_stop(libusb_device_handle *devh)
 430 {
 431         analyzer_write_status(devh, 3, STATUS_FLAG_20);
 432         analyzer_write_status(devh, 3, STATUS_FLAG_NONE);
 433 }
 434
 435 SR_PRIV void analyzer_start(libusb_device_handle *devh)
 436 {
 437         analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
 438         analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
 439         analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
 440         analyzer_write_status(devh, 1, STATUS_FLAG_GO);
 441 }
 442
 443 SR_PRIV void analyzer_configure(libusb_device_handle *devh)
 444 {
 445         int i;
 446
 447         /* Write_Start_Status */
 448         analyzer_write_status(devh, 1, STATUS_FLAG_RESET);
 449         analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
 450
 451         /* Start_Config_Outside_Device ? */
 452         analyzer_write_status(devh, 1, STATUS_FLAG_INIT);
 453         analyzer_write_status(devh, 1, STATUS_FLAG_NONE);
 454
 455         /* SetData_To_Frequence_Reg */
 456         __analyzer_set_freq(devh, g_freq_value, g_freq_scale);
 457
 458         /* SetMemory_Length */
 459         gl_reg_write(devh, MEMORY_LENGTH, g_memory_size);
 460
 461         /* Sele_Inside_Outside_Clock */
 462         gl_reg_write(devh, CLOCK_SOURCE, 0x03);
 463
 464         /* Set_Trigger_Status */
 465         for (i = 0; i < 8; i++)
 466                 gl_reg_write(devh, TRIGGER_STATUS0 + i, g_trigger_status[i]);
 467         gl_reg_write(devh, TRIGGER_EDGE, g_trigger_edge);
 468
 469         __analyzer_set_trigger_count(devh, g_trigger_count);
 470
 471         /* Set_Trigger_Level */
 472         gl_reg_write(devh, TRIGGER_LEVEL0, g_thresh);
 473         gl_reg_write(devh, TRIGGER_LEVEL1, g_thresh);
 474         gl_reg_write(devh, TRIGGER_LEVEL2, g_thresh);
 475         gl_reg_write(devh, TRIGGER_LEVEL3, g_thresh);
 476
 477         /* Size of actual memory >> 2 */
 478         __analyzer_set_ramsize_trigger_address(devh, g_ramsize_triggerbar_addr);
 479         __analyzer_set_triggerbar_address(devh, g_triggerbar_addr);
 480
 481         /* Set_Dont_Care_TriggerBar */
 482         gl_reg_write(devh, DONT_CARE_TRIGGERBAR, 0x01);
 483
 484         /* Enable_Status */
 485         analyzer_set_filter(devh);
 486
 487         /* Set_Enable_Delay_Time */
 488         gl_reg_write(devh, 0x7a, 0x00);
 489         gl_reg_write(devh, 0x7b, 0x00);
 490         analyzer_write_enable_insert_data(devh);
 491         __analyzer_set_compression(devh, g_compression);
 492 }
 493
 494 SR_PRIV int analyzer_add_triggers(const struct sr_dev_inst *sdi)
 495 {
 496         struct dev_context *devc;
 497         struct sr_trigger *trigger;
 498         struct sr_trigger_stage *stage;
 499         struct sr_trigger_match *match;
 500         GSList *l, *m;
 501         int channel;
 502
 503         devc = sdi->priv;
 504
 505         if (!(trigger = sr_session_trigger_get(sdi->session)))
 506                 return SR_OK;
 507
 508         memset(g_trigger_status, 0, sizeof(g_trigger_status));
 509         g_trigger_edge = 0;
 510
 511         for (l = trigger->stages; l; l = l->next) {
 512                 stage = l->data;
 513                 for (m = stage->matches; m; m = m->next) {
 514                         match = m->data;
 515                         devc->trigger = 1;
 516                         if (!match->channel->enabled)
 517                                 /* Ignore disabled channels with a trigger. */
 518                                 continue;
 519                         channel = match->channel->index;
 520                         switch (match->match) {
 521                         case SR_TRIGGER_ZERO:
 522                                 g_trigger_status[channel / 4] |= 2 << (channel % 4 * 2);
 523                                 break;
 524                         case SR_TRIGGER_ONE:
 525                                 g_trigger_status[channel / 4] |= 1 << (channel % 4 * 2);
 526                                 break;
 527                         case SR_TRIGGER_RISING:
 528                                 g_trigger_edge = 0x40 | (channel & 0x1F);
 529                                 break;
 530                         case SR_TRIGGER_FALLING:
 531                                 g_trigger_edge = 0x80 | (channel & 0x1F);
 532                                 break;
 533                         case SR_TRIGGER_EDGE:
 534                                 g_trigger_edge = 0xc0 | (channel & 0x1F);
 535                                 break;
 536                         default:
 537                                 sr_err("Unsupported match %d", match->match);
 538                                 return SR_ERR;
 539                         }
 540                 }
 541         }
 542
 543         return SR_OK;
 544 }
 545
 546 SR_PRIV void analyzer_add_filter(int channel, int type)
 547 {
 548         int i;
 549
 550         if (type != FILTER_HIGH && type != FILTER_LOW)
 551                 return;
 552         if ((channel & 0xf) >= 8)
 553                 return;
 554
 555         if (channel & CHANNEL_A)
 556                 i = 0;
 557         else if (channel & CHANNEL_B)
 558                 i = 2;
 559         else if (channel & CHANNEL_C)
 560                 i = 4;
 561         else if (channel & CHANNEL_D)
 562                 i = 6;
 563         else
 564                 return;
 565
 566         if ((channel & 0xf) >= 4) {
 567                 i++;
 568                 channel -= 4;
 569         }
 570
 571         g_filter_status[i] |=
 572                 1 << ((2 * channel) + (type == FILTER_LOW ? 1 : 0));
 573
 574         g_filter_enable = 1;
 575 }
 576
 577 SR_PRIV void analyzer_set_trigger_count(int count)
 578 {
 579         g_trigger_count = count;
 580 }
 581
 582 SR_PRIV void analyzer_set_freq(int freq, int scale)
 583 {
 584         g_freq_value = freq;
 585         g_freq_scale = scale;
 586 }
 587
 588 SR_PRIV void analyzer_set_memory_size(unsigned int size)
 589 {
 590         g_memory_size = size;
 591 }
 592
 593 SR_PRIV void analyzer_set_ramsize_trigger_address(unsigned int address)
 594 {
 595         g_ramsize_triggerbar_addr = address;
 596 }
 597
 598 SR_PRIV unsigned int analyzer_get_ramsize_trigger_address(void)
 599 {
 600         return g_ramsize_triggerbar_addr;
 601 }
 602
 603 SR_PRIV void analyzer_set_triggerbar_address(unsigned int address)
 604 {
 605         g_triggerbar_addr = address;
 606 }
 607
 608 SR_PRIV unsigned int analyzer_get_triggerbar_address(void)
 609 {
 610         return g_triggerbar_addr;
 611 }
 612
 613 SR_PRIV unsigned int analyzer_read_status(libusb_device_handle *devh)
 614 {
 615         return gl_reg_read(devh, DEV_STATUS);
 616 }
 617
 618 SR_PRIV unsigned int analyzer_read_id(libusb_device_handle *devh)
 619 {
 620         return gl_reg_read(devh, DEV_ID1) << 8 | gl_reg_read(devh, DEV_ID0);
 621 }
 622
 623 SR_PRIV unsigned int analyzer_get_stop_address(libusb_device_handle *devh)
 624 {
 625         return gl_reg_read(devh, STOP_ADDRESS2) << 16 | gl_reg_read(devh,
 626                         STOP_ADDRESS1) << 8 | gl_reg_read(devh, STOP_ADDRESS0);
 627 }
 628
 629 SR_PRIV unsigned int analyzer_get_now_address(libusb_device_handle *devh)
 630 {
 631         return gl_reg_read(devh, NOW_ADDRESS2) << 16 | gl_reg_read(devh,
 632                         NOW_ADDRESS1) << 8 | gl_reg_read(devh, NOW_ADDRESS0);
 633 }
 634
 635 SR_PRIV unsigned int analyzer_get_trigger_address(libusb_device_handle *devh)
 636 {
 637         return gl_reg_read(devh, TRIGGER_ADDRESS2) << 16 | gl_reg_read(devh,
 638                 TRIGGER_ADDRESS1) << 8 | gl_reg_read(devh, TRIGGER_ADDRESS0);
 639 }
 640
 641 SR_PRIV void analyzer_set_compression(unsigned int type)
 642 {
 643         g_compression = type;
 644 }
 645
 646 SR_PRIV void analyzer_set_voltage_threshold(int thresh)
 647 {
 648         g_thresh = thresh;
 649 }
 650
 651 SR_PRIV void analyzer_wait_button(libusb_device_handle *devh)
 652 {
 653         analyzer_wait(devh, STATUS_BUTTON_PRESSED, 0);
 654 }
 655
 656 SR_PRIV void analyzer_wait_data(libusb_device_handle *devh)
 657 {
 658         analyzer_wait(devh, 0, STATUS_BUSY);
 659 }
 660
 661 SR_PRIV int analyzer_decompress(void *input, unsigned int input_len,
 662                                 void *output, unsigned int output_len)
 663 {
 664         unsigned char *in = input;
 665         unsigned char *out = output;
 666         unsigned int A, B, C, count;
 667         unsigned int written = 0;
 668
 669         while (input_len > 0) {
 670                 A = *in++;
 671                 B = *in++;
 672                 C = *in++;
 673                 count = (*in++) + 1;
 674
 675                 if (count > output_len)
 676                         count = output_len;
 677                 output_len -= count;
 678                 written += count;
 679
 680                 while (count--) {
 681                         *out++ = A;
 682                         *out++ = B;
 683                         *out++ = C;
 684                         *out++ = 0; /* Channel D */
 685                 }
 686
 687                 input_len -= 4;
 688                 if (output_len == 0)
 689                         break;
 690         }
 691
 692         return written;
 693 }