src/hardware/sysclk-lwla/lwla1016.c

   1 /*
   2  * This file is part of the libsigrok project.
   3  *
   4  * Copyright (C) 2015 Daniel Elstner <daniel.kitta@gmail.com>
   5  *
   6  * This program is free software: you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation, either version 3 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <config.h>
  21 #include "lwla.h"
  22 #include "protocol.h"
  23
  24 /* Number of logic channels.
  25  */
  26 #define NUM_CHANNELS    16
  27
  28 /* Unit size for the sigrok logic datafeed.
  29  */
  30 #define UNIT_SIZE       ((NUM_CHANNELS + 7) / 8)
  31
  32 /* Size of the acquisition buffer in device memory units.
  33  */
  34 #define MEMORY_DEPTH    (256 * 1024)    /* 256k x 32 bit */
  35
  36 /* Capture memory read start address.
  37  */
  38 #define READ_START_ADDR 2
  39
  40 /* Number of device memory units (32 bit) to read at a time.
  41  */
  42 #define READ_CHUNK_LEN  250
  43
  44 /** LWLA1016 register addresses.
  45  */
  46 enum reg_addr {
  47         REG_CHAN_MASK   = 0x1000, /* bit mask of enabled channels */
  48
  49         REG_DURATION    = 0x1010, /* capture duration in ms */
  50
  51         REG_MEM_WR_PTR  = 0x1070,
  52         REG_MEM_RD_PTR  = 0x1074,
  53         REG_MEM_DATA    = 0x1078,
  54         REG_MEM_CTRL    = 0x107C,
  55
  56         REG_CAP_COUNT   = 0x10B0,
  57
  58         REG_TEST_ID     = 0x10B4, /* read */
  59         REG_TRG_SEL     = 0x10B4, /* write */
  60
  61         REG_CAP_CTRL    = 0x10B8,
  62
  63         REG_CAP_TOTAL   = 0x10BC, /* read */
  64         REG_DIV_COUNT   = 0x10BC, /* write */
  65 };
  66
  67 /** Flag bits for REG_MEM_CTRL.
  68  */
  69 enum mem_ctrl_flag {
  70         MEM_CTRL_RESET  = 1 << 0,
  71         MEM_CTRL_WRITE  = 1 << 1,
  72 };
  73
  74 /** Flag bits for REG_CAP_CTRL.
  75  */
  76 enum cap_ctrl_flag {
  77         CAP_CTRL_FIFO32_FULL    = 1 << 0, /* "fifo32_ful" bit */
  78         CAP_CTRL_FIFO64_FULL    = 1 << 1, /* "fifo64_ful" bit */
  79         CAP_CTRL_TRG_EN         = 1 << 2, /* "trg_en" bit */
  80         CAP_CTRL_CLR_TIMEBASE   = 1 << 3, /* "do_clr_timebase" bit */
  81         CAP_CTRL_FIFO_EMPTY     = 1 << 4, /* "fifo_empty" bit */
  82         CAP_CTRL_SAMPLE_EN      = 1 << 5, /* "sample_en" bit */
  83         CAP_CTRL_CNTR_NOT_ENDR  = 1 << 6, /* "cntr_not_endr" bit */
  84 };
  85
  86 /* Available FPGA configurations.
  87  */
  88 enum fpga_config {
  89         FPGA_100 = 0,   /* 100 MS/s, no compression */
  90         FPGA_100_TS,    /* 100 MS/s, timing-state mode */
  91 };
  92
  93 /* FPGA bitstream resource filenames.
  94  */
  95 static const char bitstream_map[][32] = {
  96         [FPGA_100]      = "sysclk-lwla1016-100.rbf",
  97         [FPGA_100_TS]   = "sysclk-lwla1016-100-ts.rbf",
  98 };
  99
 100 /* Demangle incoming sample data from the transfer buffer.
 101  */
 102 static void read_response(struct acquisition_state *acq)
 103 {
 104         uint32_t *in_p, *out_p;
 105         unsigned int words_left, num_words;
 106         unsigned int max_samples, run_samples;
 107         unsigned int i;
 108
 109         words_left = MIN(acq->mem_addr_next, acq->mem_addr_stop)
 110                         - acq->mem_addr_done;
 111         /* Calculate number of samples to write into packet. */
 112         max_samples = MIN(acq->samples_max - acq->samples_done,
 113                           PACKET_SIZE / UNIT_SIZE - acq->out_index);
 114         run_samples = MIN(max_samples, 2 * words_left);
 115
 116         /* Round up in case the samples limit is an odd number. */
 117         num_words = (run_samples + 1) / 2;
 118         /*
 119          * Without RLE the output index will always be a multiple of two
 120          * samples (at least before reaching the samples limit), thus 32-bit
 121          * alignment is guaranteed.
 122          */
 123         out_p = (uint32_t *)&acq->out_packet[acq->out_index * UNIT_SIZE];
 124         in_p  = &acq->xfer_buf_in[acq->in_index];
 125         /*
 126          * Transfer two samples at a time, taking care to swap the 16-bit
 127          * halves of each input word but keeping the samples themselves in
 128          * the original Little Endian order.
 129          */
 130         for (i = 0; i < num_words; i++)
 131                 out_p[i] = LROTATE(in_p[i], 16);
 132
 133         acq->in_index += num_words;
 134         acq->mem_addr_done += num_words;
 135         acq->out_index += run_samples;
 136         acq->samples_done += run_samples;
 137 }
 138
 139 /* Demangle and decompress incoming sample data from the transfer buffer.
 140  */
 141 static void read_response_rle(struct acquisition_state *acq)
 142 {
 143         uint32_t *in_p;
 144         uint16_t *out_p;
 145         unsigned int words_left;
 146         unsigned int max_samples, run_samples;
 147         unsigned int wi, ri;
 148         uint32_t word;
 149         uint16_t sample;
 150
 151         words_left = MIN(acq->mem_addr_next, acq->mem_addr_stop)
 152                         - acq->mem_addr_done;
 153         in_p = &acq->xfer_buf_in[acq->in_index];
 154
 155         for (wi = 0;; wi++) {
 156                 /* Calculate number of samples to write into packet. */
 157                 max_samples = MIN(acq->samples_max - acq->samples_done,
 158                                   PACKET_SIZE / UNIT_SIZE - acq->out_index);
 159                 run_samples = MIN(max_samples, acq->run_len);
 160
 161                 /* Expand run-length samples into session packet. */
 162                 sample = GUINT16_TO_LE(acq->sample);
 163                 out_p = &((uint16_t *)acq->out_packet)[acq->out_index];
 164
 165                 for (ri = 0; ri < run_samples; ri++)
 166                         out_p[ri] = sample;
 167
 168                 acq->run_len -= run_samples;
 169                 acq->out_index += run_samples;
 170                 acq->samples_done += run_samples;
 171
 172                 if (run_samples == max_samples)
 173                         break; /* packet full or sample limit reached */
 174                 if (wi >= words_left)
 175                         break; /* done with current transfer */
 176
 177                 word = GUINT32_FROM_LE(in_p[wi]);
 178                 acq->sample = word >> 16;
 179                 acq->run_len = (word & 0xFFFF) + 1;
 180         }
 181         acq->in_index += wi;
 182         acq->mem_addr_done += wi;
 183 }
 184
 185 /* Check whether we can receive responses of more than 64 bytes.
 186  * The FX2 firmware of the LWLA1016 has a bug in the reset logic which
 187  * sometimes causes the response endpoint to be limited to transfers of
 188  * 64 bytes at a time, instead of the expected 2*512 bytes. The problem
 189  * can be worked around by never requesting more than 64 bytes.
 190  * This quirk manifests itself only under certain conditions, and some
 191  * users seem to see it more frequently than others. Detect it here in
 192  * order to avoid paying the penalty unnecessarily.
 193  */
 194 static int test_read_memory(const struct sr_dev_inst *sdi,
 195                             unsigned int start, unsigned int count)
 196 {
 197         struct dev_context *devc;
 198         struct sr_usb_dev_inst *usb;
 199         unsigned int i;
 200         int xfer_len;
 201         int ret;
 202         uint16_t command[5];
 203         unsigned char reply[512];
 204
 205         devc = sdi->priv;
 206         usb  = sdi->conn;
 207
 208         command[0] = LWLA_WORD(CMD_READ_MEM32);
 209         command[1] = LWLA_WORD_0(start);
 210         command[2] = LWLA_WORD_1(start);
 211         command[3] = LWLA_WORD_0(count);
 212         command[4] = LWLA_WORD_1(count);
 213
 214         ret = lwla_send_command(usb, command, ARRAY_SIZE(command));
 215         if (ret != SR_OK)
 216                 return ret;
 217
 218         ret = lwla_receive_reply(usb, reply, sizeof(reply), &xfer_len);
 219         if (ret != SR_OK)
 220                 return ret;
 221
 222         devc->short_transfer_quirk = (xfer_len == 64);
 223
 224         for (i = xfer_len; i < 4 * count && xfer_len == 64; i += xfer_len) {
 225                 ret = lwla_receive_reply(usb, reply, sizeof(reply), &xfer_len);
 226                 if (ret != SR_OK)
 227                         return ret;
 228         }
 229         if (i != 4 * count) {
 230                 sr_err("Invalid read response of unexpected length %d.",
 231                        xfer_len);
 232                 return SR_ERR;
 233         }
 234         return SR_OK;
 235 }
 236
 237 /* Select and transfer FPGA bitstream for the current configuration.
 238  */
 239 static int apply_fpga_config(const struct sr_dev_inst *sdi)
 240 {
 241         struct dev_context *devc;
 242         struct drv_context *drvc;
 243         int config;
 244         int ret;
 245
 246         devc = sdi->priv;
 247         drvc = sdi->driver->context;
 248
 249         if (sdi->status == SR_ST_INACTIVE)
 250                 return SR_OK; /* the LWLA1016 has no off state */
 251
 252         config = (devc->cfg_rle) ? FPGA_100_TS : FPGA_100;
 253
 254         if (config == devc->active_fpga_config)
 255                 return SR_OK; /* no change */
 256
 257         ret = lwla_send_bitstream(drvc->sr_ctx, sdi->conn,
 258                                   bitstream_map[config]);
 259         devc->active_fpga_config = (ret == SR_OK) ? config : FPGA_NOCONF;
 260
 261         return ret;
 262 }
 263
 264 /* Perform initialization self test.
 265  */
 266 static int device_init_check(const struct sr_dev_inst *sdi)
 267 {
 268         static const struct regval mem_reset[] = {
 269                 {REG_MEM_CTRL, MEM_CTRL_RESET},
 270                 {REG_MEM_CTRL, 0},
 271         };
 272         uint32_t value;
 273         int ret;
 274
 275         const unsigned int test_count = 24;
 276
 277         ret = lwla_read_reg(sdi->conn, REG_TEST_ID, &value);
 278         if (ret != SR_OK)
 279                 return ret;
 280
 281         /* Ignore the value returned by the first read. */
 282         ret = lwla_read_reg(sdi->conn, REG_TEST_ID, &value);
 283         if (ret != SR_OK)
 284                 return ret;
 285
 286         if (value != 0x12345678) {
 287                 sr_err("Received invalid test word 0x%08X.", value);
 288                 return SR_ERR;
 289         }
 290
 291         ret = lwla_write_regs(sdi->conn, mem_reset, ARRAY_SIZE(mem_reset));
 292         if (ret != SR_OK)
 293                 return ret;
 294
 295         ret = test_read_memory(sdi, 0, test_count);
 296         if (ret != SR_OK)
 297                 return ret;
 298         /*
 299          * Issue another read request or the device will stall, for whatever
 300          * reason. This happens both with and without the short transfer quirk.
 301          */
 302         return test_read_memory(sdi, test_count, test_count);
 303 }
 304
 305 static int setup_acquisition(const struct sr_dev_inst *sdi)
 306 {
 307         struct dev_context *devc;
 308         struct sr_usb_dev_inst *usb;
 309         struct acquisition_state *acq;
 310         uint32_t divider_count;
 311         int ret;
 312
 313         devc = sdi->priv;
 314         usb  = sdi->conn;
 315         acq  = devc->acquisition;
 316
 317         acq->reg_seq_pos = 0;
 318         acq->reg_seq_len = 0;
 319
 320         lwla_queue_regval(acq, REG_CHAN_MASK, devc->channel_mask);
 321
 322         if (devc->samplerate > 0 && devc->samplerate < SR_MHZ(100))
 323                 divider_count = SR_MHZ(100) / devc->samplerate - 1;
 324         else
 325                 divider_count = 0;
 326
 327         lwla_queue_regval(acq, REG_DIV_COUNT, divider_count);
 328
 329         lwla_queue_regval(acq, REG_CAP_CTRL, 0);
 330         lwla_queue_regval(acq, REG_DURATION, 0);
 331
 332         lwla_queue_regval(acq, REG_MEM_CTRL, MEM_CTRL_RESET);
 333         lwla_queue_regval(acq, REG_MEM_CTRL, 0);
 334         lwla_queue_regval(acq, REG_MEM_CTRL, MEM_CTRL_WRITE);
 335
 336         lwla_queue_regval(acq, REG_CAP_CTRL,
 337                 CAP_CTRL_FIFO32_FULL | CAP_CTRL_FIFO64_FULL);
 338
 339         lwla_queue_regval(acq, REG_CAP_CTRL, CAP_CTRL_FIFO_EMPTY);
 340         lwla_queue_regval(acq, REG_CAP_CTRL, 0);
 341
 342         lwla_queue_regval(acq, REG_CAP_COUNT, MEMORY_DEPTH - 5);
 343
 344         lwla_queue_regval(acq, REG_TRG_SEL,
 345                 ((devc->trigger_edge_mask & 0xFFFF) << 16)
 346                 | (devc->trigger_values & 0xFFFF));
 347
 348         ret = lwla_write_regs(usb, acq->reg_sequence, acq->reg_seq_len);
 349         acq->reg_seq_len = 0;
 350
 351         return ret;
 352 }
 353
 354 static int prepare_request(const struct sr_dev_inst *sdi)
 355 {
 356         struct dev_context *devc;
 357         struct acquisition_state *acq;
 358         unsigned int chunk_len, count;
 359
 360         devc = sdi->priv;
 361         acq  = devc->acquisition;
 362
 363         acq->xfer_out->length = 0;
 364         acq->reg_seq_pos = 0;
 365         acq->reg_seq_len = 0;
 366
 367         switch (devc->state) {
 368         case STATE_START_CAPTURE:
 369                 lwla_queue_regval(acq, REG_CAP_CTRL, CAP_CTRL_TRG_EN
 370                                 | ((devc->trigger_mask & 0xFFFF) << 16));
 371                 break;
 372         case STATE_STOP_CAPTURE:
 373                 lwla_queue_regval(acq, REG_CAP_CTRL, 0);
 374                 lwla_queue_regval(acq, REG_DIV_COUNT, 0);
 375                 break;
 376         case STATE_READ_PREPARE:
 377                 lwla_queue_regval(acq, REG_MEM_CTRL, 0);
 378                 break;
 379         case STATE_READ_FINISH:
 380                 lwla_queue_regval(acq, REG_MEM_CTRL, MEM_CTRL_RESET);
 381                 lwla_queue_regval(acq, REG_MEM_CTRL, 0);
 382                 break;
 383         case STATE_STATUS_REQUEST:
 384                 lwla_queue_regval(acq, REG_CAP_CTRL, 0);
 385                 lwla_queue_regval(acq, REG_MEM_WR_PTR, 0);
 386                 lwla_queue_regval(acq, REG_DURATION, 0);
 387                 break;
 388         case STATE_LENGTH_REQUEST:
 389                 lwla_queue_regval(acq, REG_CAP_COUNT, 0);
 390                 break;
 391         case STATE_READ_REQUEST:
 392                 /* Limit reads to 16 device words (64 bytes) at a time if the
 393                  * device firmware has the short transfer quirk. */
 394                 chunk_len = (devc->short_transfer_quirk) ? 16 : READ_CHUNK_LEN;
 395                 count = MIN(chunk_len, acq->mem_addr_stop - acq->mem_addr_next);
 396
 397                 acq->xfer_buf_out[0] = LWLA_WORD(CMD_READ_MEM32);
 398                 acq->xfer_buf_out[1] = LWLA_WORD_0(acq->mem_addr_next);
 399                 acq->xfer_buf_out[2] = LWLA_WORD_1(acq->mem_addr_next);
 400                 acq->xfer_buf_out[3] = LWLA_WORD_0(count);
 401                 acq->xfer_buf_out[4] = LWLA_WORD_1(count);
 402                 acq->xfer_out->length = 5 * sizeof(acq->xfer_buf_out[0]);
 403
 404                 acq->mem_addr_next += count;
 405                 break;
 406         default:
 407                 sr_err("BUG: unhandled request state %d.", devc->state);
 408                 return SR_ERR_BUG;
 409         }
 410
 411         return SR_OK;
 412 }
 413
 414 static int handle_response(const struct sr_dev_inst *sdi)
 415 {
 416         struct dev_context *devc;
 417         struct acquisition_state *acq;
 418         int expect_len;
 419
 420         devc = sdi->priv;
 421         acq  = devc->acquisition;
 422
 423         switch (devc->state) {
 424         case STATE_STATUS_REQUEST:
 425                 acq->status = acq->reg_sequence[0].val & 0x7F;
 426                 acq->mem_addr_fill = acq->reg_sequence[1].val;
 427                 acq->duration_now  = acq->reg_sequence[2].val;
 428                 break;
 429         case STATE_LENGTH_REQUEST:
 430                 acq->mem_addr_next = READ_START_ADDR;
 431                 acq->mem_addr_stop = acq->reg_sequence[0].val + READ_START_ADDR - 1;
 432                 break;
 433         case STATE_READ_REQUEST:
 434                 expect_len = (acq->mem_addr_next - acq->mem_addr_done
 435                                 + acq->in_index) * sizeof(acq->xfer_buf_in[0]);
 436                 if (acq->xfer_in->actual_length != expect_len) {
 437                         sr_err("Received size %d does not match expected size %d.",
 438                                acq->xfer_in->actual_length, expect_len);
 439                         devc->transfer_error = TRUE;
 440                         return SR_ERR;
 441                 }
 442                 if (acq->rle_enabled)
 443                         read_response_rle(acq);
 444                 else
 445                         read_response(acq);
 446                 break;
 447         default:
 448                 sr_err("BUG: unhandled response state %d.", devc->state);
 449                 return SR_ERR_BUG;
 450         }
 451
 452         return SR_OK;
 453 }
 454
 455 /* Model descriptor for the LWLA1016.
 456  */
 457 SR_PRIV const struct model_info lwla1016_info = {
 458         .name = "LWLA1016",
 459         .num_channels = NUM_CHANNELS,
 460
 461         .num_devopts = 5,
 462         .devopts = {
 463                 SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET,
 464                 SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET,
 465                 SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
 466                 SR_CONF_TRIGGER_MATCH | SR_CONF_LIST,
 467                 SR_CONF_RLE | SR_CONF_GET | SR_CONF_SET,
 468         },
 469         .num_samplerates = 19,
 470         .samplerates = {
 471                 SR_MHZ(100),
 472                 SR_MHZ(50),  SR_MHZ(20),  SR_MHZ(10),
 473                 SR_MHZ(5),   SR_MHZ(2),   SR_MHZ(1),
 474                 SR_KHZ(500), SR_KHZ(200), SR_KHZ(100),
 475                 SR_KHZ(50),  SR_KHZ(20),  SR_KHZ(10),
 476                 SR_KHZ(5),   SR_KHZ(2),   SR_KHZ(1),
 477                 SR_HZ(500),  SR_HZ(200),  SR_HZ(100),
 478         },
 479
 480         .apply_fpga_config = &apply_fpga_config,
 481         .device_init_check = &device_init_check,
 482         .setup_acquisition = &setup_acquisition,
 483
 484         .prepare_request = &prepare_request,
 485         .handle_response = &handle_response,
 486 };