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[libsigrok.git] / src / hardware / yokogawa-dlm / api.c
CommitLineData
10763937
SA
1/*
2 * This file is part of the libsigrok project.
3 *
4 * Copyright (C) 2014 abraxa (Soeren Apel) <soeren@apelpie.net>
5 * Based on the Hameg HMO driver by poljar (Damir Jelić) <poljarinho@gmail.com>
6 *
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation, either version 3 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
6ec6c43b 21#include <config.h>
10763937 22#include <stdlib.h>
5a1afc09 23#include "scpi.h"
10763937
SA
24#include "protocol.h"
25
dd5c48a6 26static struct sr_dev_driver yokogawa_dlm_driver_info;
8ab929d6 27
329733d9 28static const char *MANUFACTURER_ID = "YOKOGAWA";
8ab929d6 29
4b25cbff 30static const uint32_t scanopts[] = {
f3c60fb6
SA
31 SR_CONF_CONN,
32};
33
4b25cbff 34static const uint32_t drvopts[] = {
cf0280fa
AJ
35 SR_CONF_LOGIC_ANALYZER,
36 SR_CONF_OSCILLOSCOPE,
37};
38
4b25cbff 39static const uint32_t devopts[] = {
f3c60fb6
SA
40 SR_CONF_LIMIT_FRAMES | SR_CONF_GET | SR_CONF_SET,
41 SR_CONF_SAMPLERATE | SR_CONF_GET,
42 SR_CONF_TIMEBASE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
43 SR_CONF_NUM_HDIV | SR_CONF_GET,
44 SR_CONF_HORIZ_TRIGGERPOS | SR_CONF_GET | SR_CONF_SET,
f3c60fb6 45 SR_CONF_TRIGGER_SOURCE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
86621306 46 SR_CONF_TRIGGER_SLOPE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
f3c60fb6
SA
47};
48
6b82c3e5 49static const uint32_t devopts_cg_analog[] = {
f3c60fb6 50 SR_CONF_NUM_VDIV | SR_CONF_GET,
86621306
UH
51 SR_CONF_VDIV | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
52 SR_CONF_COUPLING | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
f3c60fb6
SA
53};
54
6b82c3e5 55static const uint32_t devopts_cg_digital[] = {
ad7b0c17 56 /* EMPTY */
f3c60fb6
SA
57};
58
8ab929d6
SA
59enum {
60 CG_INVALID = -1,
61 CG_NONE,
62 CG_ANALOG,
63 CG_DIGITAL,
64};
65
373e92a4 66static struct sr_dev_inst *probe_device(struct sr_scpi_dev_inst *scpi)
8ab929d6
SA
67{
68 struct sr_dev_inst *sdi;
69 struct dev_context *devc;
70 struct sr_scpi_hw_info *hw_info;
71 char *model_name;
72 int model_index;
73
74 sdi = NULL;
75 devc = NULL;
76 hw_info = NULL;
77
78 if (sr_scpi_get_hw_id(scpi, &hw_info) != SR_OK) {
79 sr_info("Couldn't get IDN response.");
80 goto fail;
81 }
82
83 if (strcmp(hw_info->manufacturer, MANUFACTURER_ID) != 0)
84 goto fail;
85
86 if (dlm_model_get(hw_info->model, &model_name, &model_index) != SR_OK)
87 goto fail;
88
aac29cc1 89 sdi = g_malloc0(sizeof(struct sr_dev_inst));
b15ff1c9 90 sdi->vendor = g_strdup("Yokogawa");
0af636be
UH
91 sdi->model = g_strdup(model_name);
92 sdi->version = g_strdup(hw_info->firmware_version);
8ab929d6 93
d1314831
SA
94 sdi->serial_num = g_strdup(hw_info->serial_number);
95
8ab929d6
SA
96 sr_scpi_hw_info_free(hw_info);
97 hw_info = NULL;
98
ac10a927 99 devc = g_malloc0(sizeof(struct dev_context));
8ab929d6 100
4f840ce9 101 sdi->driver = &yokogawa_dlm_driver_info;
8ab929d6
SA
102 sdi->priv = devc;
103 sdi->inst_type = SR_INST_SCPI;
104 sdi->conn = scpi;
105
106 if (dlm_device_init(sdi, model_index) != SR_OK)
107 goto fail;
108
8ab929d6
SA
109 return sdi;
110
111fail:
7b365c47 112 sr_scpi_hw_info_free(hw_info);
4bf93988 113 sr_dev_inst_free(sdi);
b1f83103 114 g_free(devc);
8ab929d6
SA
115
116 return NULL;
117}
118
4f840ce9 119static GSList *scan(struct sr_dev_driver *di, GSList *options)
8ab929d6 120{
373e92a4 121 return sr_scpi_scan(di->context, options, probe_device);
8ab929d6
SA
122}
123
3553451f 124static void clear_helper(struct dev_context *devc)
8ab929d6 125{
8ab929d6 126 dlm_scope_state_destroy(devc->model_state);
8ab929d6
SA
127 g_free(devc->analog_groups);
128 g_free(devc->digital_groups);
8ab929d6
SA
129}
130
4f840ce9 131static int dev_clear(const struct sr_dev_driver *di)
8ab929d6 132{
3553451f 133 return std_dev_clear_with_callback(di, (std_dev_clear_callback)clear_helper);
8ab929d6
SA
134}
135
136static int dev_open(struct sr_dev_inst *sdi)
137{
6402c379 138 if (sr_scpi_open(sdi->conn) != SR_OK)
8ab929d6
SA
139 return SR_ERR;
140
141 if (dlm_scope_state_query(sdi) != SR_OK)
142 return SR_ERR;
143
8ab929d6
SA
144 return SR_OK;
145}
146
147static int dev_close(struct sr_dev_inst *sdi)
148{
f1ba6b4b 149 return sr_scpi_close(sdi->conn);
8ab929d6
SA
150}
151
8ab929d6
SA
152/**
153 * Check which category a given channel group belongs to.
154 *
155 * @param devc Our internal device context.
a9308652 156 * @param cg The channel group to check.
8ab929d6 157 *
a9308652
UH
158 * @retval CG_NONE cg is NULL
159 * @retval CG_ANALOG cg is an analog group
8ab929d6
SA
160 * @retval CG_DIGITAL cg is a digital group
161 * @retval CG_INVALID cg is something else
162 */
163static int check_channel_group(struct dev_context *devc,
ac10a927 164 const struct sr_channel_group *cg)
8ab929d6 165{
329733d9 166 const struct scope_config *model;
8ab929d6 167
93b5cd69
GS
168 if (!devc)
169 return CG_INVALID;
8ab929d6
SA
170 model = devc->model_config;
171
172 if (!cg)
173 return CG_NONE;
174
fcd6a8bd
UH
175 if (std_cg_idx(cg, devc->analog_groups, model->analog_channels) >= 0)
176 return CG_ANALOG;
8ab929d6 177
fcd6a8bd
UH
178 if (std_cg_idx(cg, devc->digital_groups, model->pods) >= 0)
179 return CG_DIGITAL;
8ab929d6
SA
180
181 sr_err("Invalid channel group specified.");
fcd6a8bd 182
8ab929d6
SA
183 return CG_INVALID;
184}
185
dd7a72ea
UH
186static int config_get(uint32_t key, GVariant **data,
187 const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
8ab929d6 188{
fcd6a8bd 189 int ret, cg_type, idx;
8ab929d6 190 struct dev_context *devc;
329733d9 191 const struct scope_config *model;
8ab929d6
SA
192 struct scope_state *state;
193
709468ba 194 if (!sdi)
8ab929d6
SA
195 return SR_ERR_ARG;
196
709468ba
UH
197 devc = sdi->priv;
198
8ab929d6
SA
199 if ((cg_type = check_channel_group(devc, cg)) == CG_INVALID)
200 return SR_ERR;
201
8ab929d6
SA
202 model = devc->model_config;
203 state = devc->model_state;
204
205 switch (key) {
bf622e6d 206 case SR_CONF_NUM_HDIV:
8ab929d6
SA
207 *data = g_variant_new_int32(model->num_xdivs);
208 ret = SR_OK;
209 break;
210 case SR_CONF_TIMEBASE:
211 *data = g_variant_new("(tt)",
f3c60fb6
SA
212 dlm_timebases[state->timebase][0],
213 dlm_timebases[state->timebase][1]);
8ab929d6
SA
214 ret = SR_OK;
215 break;
216 case SR_CONF_NUM_VDIV:
3782e571 217 if (!cg)
8ab929d6 218 return SR_ERR_CHANNEL_GROUP;
3782e571
UH
219 if (cg_type != CG_ANALOG)
220 return SR_ERR_NA;
221 *data = g_variant_new_int32(model->num_ydivs);
222 ret = SR_OK;
8ab929d6
SA
223 break;
224 case SR_CONF_VDIV:
3782e571 225 if (!cg)
8ab929d6 226 return SR_ERR_CHANNEL_GROUP;
3782e571
UH
227 if (cg_type != CG_ANALOG)
228 return SR_ERR_NA;
fcd6a8bd
UH
229 if ((idx = std_cg_idx(cg, devc->analog_groups, model->analog_channels)) < 0)
230 return SR_ERR_ARG;
231 *data = g_variant_new("(tt)",
232 dlm_vdivs[state->analog_states[idx].vdiv][0],
233 dlm_vdivs[state->analog_states[idx].vdiv][1]);
234 ret = SR_OK;
8ab929d6
SA
235 break;
236 case SR_CONF_TRIGGER_SOURCE:
237 *data = g_variant_new_string((*model->trigger_sources)[state->trigger_source]);
238 ret = SR_OK;
239 break;
240 case SR_CONF_TRIGGER_SLOPE:
f3c60fb6 241 *data = g_variant_new_string(dlm_trigger_slopes[state->trigger_slope]);
8ab929d6
SA
242 ret = SR_OK;
243 break;
244 case SR_CONF_HORIZ_TRIGGERPOS:
245 *data = g_variant_new_double(state->horiz_triggerpos);
246 ret = SR_OK;
247 break;
248 case SR_CONF_COUPLING:
3782e571 249 if (!cg)
8ab929d6 250 return SR_ERR_CHANNEL_GROUP;
3782e571
UH
251 if (cg_type != CG_ANALOG)
252 return SR_ERR_NA;
fcd6a8bd
UH
253 if ((idx = std_cg_idx(cg, devc->analog_groups, model->analog_channels)) < 0)
254 return SR_ERR_ARG;
255 *data = g_variant_new_string((*model->coupling_options)[state->analog_states[idx].coupling]);
256 ret = SR_OK;
8ab929d6
SA
257 break;
258 case SR_CONF_SAMPLERATE:
259 *data = g_variant_new_uint64(state->sample_rate);
260 ret = SR_OK;
261 break;
262 default:
263 ret = SR_ERR_NA;
264 }
265
266 return ret;
267}
268
dd7a72ea
UH
269static int config_set(uint32_t key, GVariant *data,
270 const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
8ab929d6 271{
fcd6a8bd 272 int ret, cg_type, idx, j;
8ab929d6
SA
273 char float_str[30];
274 struct dev_context *devc;
329733d9 275 const struct scope_config *model;
8ab929d6 276 struct scope_state *state;
8ab929d6
SA
277 double tmp_d;
278 gboolean update_sample_rate;
279
280 if (!sdi || !(devc = sdi->priv))
281 return SR_ERR_ARG;
282
283 if ((cg_type = check_channel_group(devc, cg)) == CG_INVALID)
284 return SR_ERR;
285
286 model = devc->model_config;
287 state = devc->model_state;
288 update_sample_rate = FALSE;
289
8ab929d6
SA
290 switch (key) {
291 case SR_CONF_LIMIT_FRAMES:
292 devc->frame_limit = g_variant_get_uint64(data);
293 ret = SR_OK;
294 break;
295 case SR_CONF_TRIGGER_SOURCE:
bd633efa
UH
296 if ((idx = std_str_idx(data, *model->trigger_sources, model->num_trigger_sources)) < 0)
297 return SR_ERR_ARG;
298 state->trigger_source = idx;
299 /* TODO: A and B trigger support possible? */
300 ret = dlm_trigger_source_set(sdi->conn, (*model->trigger_sources)[idx]);
8ab929d6
SA
301 break;
302 case SR_CONF_VDIV:
61233697 303 if (!cg)
8ab929d6 304 return SR_ERR_CHANNEL_GROUP;
697fb6dd
UH
305 if ((idx = std_u64_tuple_idx(data, ARRAY_AND_SIZE(dlm_vdivs))) < 0)
306 return SR_ERR_ARG;
fcd6a8bd
UH
307 if ((j = std_cg_idx(cg, devc->analog_groups, model->analog_channels)) < 0)
308 return SR_ERR_ARG;
309 state->analog_states[j].vdiv = idx;
310 g_ascii_formatd(float_str, sizeof(float_str),
311 "%E", (float) dlm_vdivs[idx][0] / dlm_vdivs[idx][1]);
312 if (dlm_analog_chan_vdiv_set(sdi->conn, j + 1, float_str) != SR_OK ||
313 sr_scpi_get_opc(sdi->conn) != SR_OK)
314 return SR_ERR;
697fb6dd 315 ret = SR_OK;
8ab929d6
SA
316 break;
317 case SR_CONF_TIMEBASE:
697fb6dd
UH
318 if ((idx = std_u64_tuple_idx(data, ARRAY_AND_SIZE(dlm_timebases))) < 0)
319 return SR_ERR_ARG;
320 state->timebase = idx;
321 g_ascii_formatd(float_str, sizeof(float_str),
322 "%E", (float) dlm_timebases[idx][0] / dlm_timebases[idx][1]);
323 ret = dlm_timebase_set(sdi->conn, float_str);
324 update_sample_rate = TRUE;
8ab929d6
SA
325 break;
326 case SR_CONF_HORIZ_TRIGGERPOS:
327 tmp_d = g_variant_get_double(data);
328
329 /* TODO: Check if the calculation makes sense for the DLM. */
330 if (tmp_d < 0.0 || tmp_d > 1.0)
331 return SR_ERR;
332
333 state->horiz_triggerpos = tmp_d;
334 tmp_d = -(tmp_d - 0.5) *
f3c60fb6
SA
335 ((double) dlm_timebases[state->timebase][0] /
336 dlm_timebases[state->timebase][1])
ac10a927 337 * model->num_xdivs;
8ab929d6
SA
338
339 g_ascii_formatd(float_str, sizeof(float_str), "%E", tmp_d);
340 ret = dlm_horiz_trigger_pos_set(sdi->conn, float_str);
341 break;
342 case SR_CONF_TRIGGER_SLOPE:
bd633efa 343 if ((idx = std_str_idx(data, ARRAY_AND_SIZE(dlm_trigger_slopes))) < 0)
8ab929d6 344 return SR_ERR_ARG;
8ab929d6 345 /* Note: See dlm_trigger_slopes[] in protocol.c. */
bd633efa 346 state->trigger_slope = idx;
8ab929d6
SA
347 ret = dlm_trigger_slope_set(sdi->conn, state->trigger_slope);
348 break;
349 case SR_CONF_COUPLING:
61233697 350 if (!cg)
8ab929d6 351 return SR_ERR_CHANNEL_GROUP;
bd633efa
UH
352 if ((idx = std_str_idx(data, *model->coupling_options, model->num_coupling_options)) < 0)
353 return SR_ERR_ARG;
fcd6a8bd
UH
354 if ((j = std_cg_idx(cg, devc->analog_groups, model->analog_channels)) < 0)
355 return SR_ERR_ARG;
356 state->analog_states[j].coupling = idx;
357 if (dlm_analog_chan_coupl_set(sdi->conn, j + 1, (*model->coupling_options)[idx]) != SR_OK ||
358 sr_scpi_get_opc(sdi->conn) != SR_OK)
359 return SR_ERR;
bd633efa 360 ret = SR_OK;
8ab929d6
SA
361 break;
362 default:
363 ret = SR_ERR_NA;
364 break;
365 }
366
367 if (ret == SR_OK)
368 ret = sr_scpi_get_opc(sdi->conn);
369
370 if (ret == SR_OK && update_sample_rate)
371 ret = dlm_sample_rate_query(sdi);
372
373 return ret;
374}
375
c65a021c 376static int config_channel_set(const struct sr_dev_inst *sdi,
dd7a72ea 377 struct sr_channel *ch, unsigned int changes)
c65a021c 378{
a9308652 379 /* Currently we only handle SR_CHANNEL_SET_ENABLED. */
c65a021c
SA
380 if (changes != SR_CHANNEL_SET_ENABLED)
381 return SR_ERR_NA;
382
383 return dlm_channel_state_set(sdi, ch->index, ch->enabled);
384}
385
dd7a72ea
UH
386static int config_list(uint32_t key, GVariant **data,
387 const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
8ab929d6 388{
cf0280fa 389 int cg_type = CG_NONE;
e66d1892
UH
390 struct dev_context *devc;
391 const struct scope_config *model;
f3c60fb6 392
e66d1892
UH
393 devc = (sdi) ? sdi->priv : NULL;
394 model = (devc) ? devc->model_config : NULL;
f3c60fb6 395
f3c60fb6
SA
396 if (!cg) {
397 switch (key) {
e66d1892 398 case SR_CONF_SCAN_OPTIONS:
f3c60fb6 399 case SR_CONF_DEVICE_OPTIONS:
4b25cbff 400 return STD_CONFIG_LIST(key, data, sdi, cg, scanopts, drvopts, devopts);
f3c60fb6 401 case SR_CONF_TIMEBASE:
58ffcf97 402 *data = std_gvar_tuple_array(ARRAY_AND_SIZE(dlm_timebases));
f3c60fb6
SA
403 return SR_OK;
404 case SR_CONF_TRIGGER_SOURCE:
405 if (!model)
406 return SR_ERR_ARG;
692716f5 407 *data = g_variant_new_strv(*model->trigger_sources, model->num_trigger_sources);
f3c60fb6
SA
408 return SR_OK;
409 case SR_CONF_TRIGGER_SLOPE:
692716f5 410 *data = g_variant_new_strv(ARRAY_AND_SIZE(dlm_trigger_slopes));
f3c60fb6
SA
411 return SR_OK;
412 case SR_CONF_NUM_HDIV:
93b5cd69
GS
413 if (!model)
414 return SR_ERR_ARG;
49f49cb5 415 *data = g_variant_new_uint32(model->num_xdivs);
f3c60fb6
SA
416 return SR_OK;
417 default:
418 return SR_ERR_NA;
419 }
420 }
421
422 if ((cg_type = check_channel_group(devc, cg)) == CG_INVALID)
423 return SR_ERR;
424
8ab929d6 425 switch (key) {
8ab929d6 426 case SR_CONF_DEVICE_OPTIONS:
ad7b0c17 427 if (cg_type == CG_ANALOG) {
53012da6 428 *data = std_gvar_array_u32(ARRAY_AND_SIZE(devopts_cg_analog));
ad7b0c17
GS
429 break;
430 }
431 if (cg_type == CG_DIGITAL) {
432 if (!ARRAY_SIZE(devopts_cg_digital)) {
433 *data = std_gvar_array_u32(NULL, 0);
434 break;
435 }
53012da6 436 *data = std_gvar_array_u32(ARRAY_AND_SIZE(devopts_cg_digital));
ad7b0c17
GS
437 break;
438 }
439 *data = std_gvar_array_u32(NULL, 0);
8ab929d6
SA
440 break;
441 case SR_CONF_COUPLING:
61233697 442 if (!cg)
8ab929d6 443 return SR_ERR_CHANNEL_GROUP;
692716f5 444 *data = g_variant_new_strv(*model->coupling_options, model->num_coupling_options);
8ab929d6 445 break;
8ab929d6 446 case SR_CONF_VDIV:
61233697 447 if (!cg)
8ab929d6 448 return SR_ERR_CHANNEL_GROUP;
58ffcf97 449 *data = std_gvar_tuple_array(ARRAY_AND_SIZE(dlm_vdivs));
8ab929d6
SA
450 break;
451 default:
452 return SR_ERR_NA;
453 }
454
455 return SR_OK;
456}
457
458static int dlm_check_channels(GSList *channels)
459{
460 GSList *l;
461 struct sr_channel *ch;
462 gboolean enabled_pod1, enabled_chan4;
463
464 enabled_pod1 = enabled_chan4 = FALSE;
465
466 /* Note: On the DLM2000, CH4 and Logic are shared. */
467 /* TODO Handle non-DLM2000 models. */
468 for (l = channels; l; l = l->next) {
469 ch = l->data;
470 switch (ch->type) {
471 case SR_CHANNEL_ANALOG:
472 if (ch->index == 3)
473 enabled_chan4 = TRUE;
474 break;
475 case SR_CHANNEL_LOGIC:
476 enabled_pod1 = TRUE;
477 break;
478 default:
479 return SR_ERR;
480 }
481 }
482
483 if (enabled_pod1 && enabled_chan4)
484 return SR_ERR;
485
486 return SR_OK;
487}
488
695dc859 489static int dev_acquisition_start(const struct sr_dev_inst *sdi)
8ab929d6
SA
490{
491 GSList *l;
492 gboolean digital_added;
493 struct sr_channel *ch;
494 struct dev_context *devc;
495 struct sr_scpi_dev_inst *scpi;
496
8ab929d6
SA
497 scpi = sdi->conn;
498 devc = sdi->priv;
499 digital_added = FALSE;
500
501 g_slist_free(devc->enabled_channels);
502 devc->enabled_channels = NULL;
503
504 for (l = sdi->channels; l; l = l->next) {
505 ch = l->data;
506 if (!ch->enabled)
507 continue;
508 /* Only add a single digital channel. */
509 if (ch->type != SR_CHANNEL_LOGIC || !digital_added) {
510 devc->enabled_channels = g_slist_append(
ac10a927
SA
511 devc->enabled_channels, ch);
512 if (ch->type == SR_CHANNEL_LOGIC)
513 digital_added = TRUE;
8ab929d6
SA
514 }
515 }
516
517 if (!devc->enabled_channels)
518 return SR_ERR;
519
520 if (dlm_check_channels(devc->enabled_channels) != SR_OK) {
521 sr_err("Invalid channel configuration specified!");
522 return SR_ERR_NA;
523 }
524
af3487ec
SA
525 /* Request data for the first enabled channel. */
526 devc->current_channel = devc->enabled_channels;
527 dlm_channel_data_request(sdi);
528
0028d5a1 529 sr_scpi_source_add(sdi->session, scpi, G_IO_IN, 5,
8ab929d6
SA
530 dlm_data_receive, (void *)sdi);
531
532 return SR_OK;
533}
534
695dc859 535static int dev_acquisition_stop(struct sr_dev_inst *sdi)
8ab929d6
SA
536{
537 struct dev_context *devc;
8ab929d6 538
bee2b016 539 std_session_send_df_end(sdi);
8ab929d6 540
8ab929d6
SA
541 devc = sdi->priv;
542
543 devc->num_frames = 0;
544 g_slist_free(devc->enabled_channels);
545 devc->enabled_channels = NULL;
af3487ec
SA
546
547 sr_scpi_source_remove(sdi->session, sdi->conn);
8ab929d6
SA
548
549 return SR_OK;
550}
10763937 551
dd5c48a6 552static struct sr_dev_driver yokogawa_dlm_driver_info = {
10763937 553 .name = "yokogawa-dlm",
ac10a927 554 .longname = "Yokogawa DL/DLM",
10763937 555 .api_version = 1,
c2fdcc25 556 .init = std_init,
700d6b64 557 .cleanup = std_cleanup,
8ab929d6 558 .scan = scan,
c01bf34c 559 .dev_list = std_dev_list,
8ab929d6
SA
560 .dev_clear = dev_clear,
561 .config_get = config_get,
562 .config_set = config_set,
c65a021c 563 .config_channel_set = config_channel_set,
8ab929d6
SA
564 .config_list = config_list,
565 .dev_open = dev_open,
566 .dev_close = dev_close,
567 .dev_acquisition_start = dev_acquisition_start,
568 .dev_acquisition_stop = dev_acquisition_stop,
41812aca 569 .context = NULL,
10763937 570};
dd5c48a6 571SR_REGISTER_DEV_DRIVER(yokogawa_dlm_driver_info);