]>
Commit | Line | Data |
---|---|---|
f2cd2deb FS |
1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2020 Florian Schmidt <schmidt_florian@gmx.de> | |
5 | * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se> | |
6 | * Copyright (C) 2013 Bert Vermeulen <bert@biot.com> | |
7 | * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk> | |
8 | * | |
9 | * This program is free software: you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation, either version 3 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #include <config.h> | |
a7740b06 | 24 | |
f2cd2deb | 25 | #include <libsigrok/libsigrok.h> |
a7740b06 GS |
26 | #include <string.h> |
27 | ||
f2cd2deb FS |
28 | #include "libsigrok-internal.h" |
29 | #include "protocol.h" | |
30 | ||
f2cd2deb | 31 | #define UC_FIRMWARE "kingst-la-%04x.fw" |
9de389b1 KG |
32 | #define FPGA_FW_LA2016 "kingst-la2016-fpga.bitstream" |
33 | #define FPGA_FW_LA2016A "kingst-la2016a1-fpga.bitstream" | |
8b172e78 KG |
34 | #define FPGA_FW_LA1016 "kingst-la1016-fpga.bitstream" |
35 | #define FPGA_FW_LA1016A "kingst-la1016a1-fpga.bitstream" | |
f2cd2deb | 36 | |
852c7d14 | 37 | /* Maximum device capabilities. May differ between models. */ |
8b172e78 KG |
38 | #define MAX_SAMPLE_RATE_LA2016 SR_MHZ(200) |
39 | #define MAX_SAMPLE_RATE_LA1016 SR_MHZ(100) | |
e9430410 GS |
40 | #define MAX_SAMPLE_DEPTH 10e9 |
41 | #define MAX_PWM_FREQ SR_MHZ(20) | |
42 | #define PWM_CLOCK SR_MHZ(200) /* 200MHz for both LA2016 and LA1016 */ | |
f2cd2deb | 43 | |
852c7d14 GS |
44 | /* |
45 | * Default device configuration. Must be applicable to any of the | |
46 | * supported devices (no model specific default values yet). Specific | |
47 | * firmware implementation details unfortunately won't let us detect | |
48 | * and keep using previously configured values. | |
49 | */ | |
50 | #define LA2016_DFLT_SAMPLERATE SR_MHZ(100) | |
51 | #define LA2016_DFLT_SAMPLEDEPTH (5 * 1000 * 1000) | |
52 | #define LA2016_DFLT_CAPT_RATIO 5 /* Capture ratio, in percent. */ | |
53 | ||
54 | /* TODO | |
55 | * What is the origin and motivation of that 128Mi literal? What is its | |
56 | * unit? How does it relate to a device's hardware capabilities? How to | |
57 | * map the 1GiB of RAM of an LA2016 (at 16 channels) to the 128Mi value? | |
58 | * It cannot be sample count. Is it memory size in bytes perhaps? | |
59 | */ | |
60 | #define LA2016_PRE_MEM_LIMIT_BASE (128 * 1024 * 1024) | |
61 | ||
96dc954e | 62 | /* USB vendor class control requests, executed by the Cypress FX2 MCU. */ |
84fe94bd | 63 | #define CMD_FPGA_ENABLE 0x10 |
96dc954e GS |
64 | #define CMD_FPGA_SPI 0x20 /* R/W access to FPGA registers via SPI. */ |
65 | #define CMD_BULK_START 0x30 /* Start sample data download via USB EP6 IN. */ | |
66 | #define CMD_BULK_RESET 0x38 /* Flush FIFO of FX2 USB EP6 IN. */ | |
67 | #define CMD_FPGA_INIT 0x50 /* Used before and after FPGA bitstream upload. */ | |
68 | #define CMD_KAUTH 0x60 /* Communicate to auth IC (U10). Not used. */ | |
69 | #define CMD_EEPROM 0xa2 /* R/W access to EEPROM content. */ | |
00849545 | 70 | |
42f6dd55 | 71 | /* |
96dc954e GS |
72 | * FPGA register addresses (base addresses when registers span multiple |
73 | * bytes, in that case data is kept in little endian format). Passed to | |
74 | * CMD_FPGA_SPI requests. The FX2 MCU transparently handles the detail | |
75 | * of SPI transfers encoding the read (1) or write (0) direction in the | |
76 | * MSB of the address field. There are some 60 byte-wide FPGA registers. | |
d6f89d4b GS |
77 | * |
78 | * Unfortunately the FPGA registers change their meaning between the | |
79 | * read and write directions of access, or exclusively provide one of | |
80 | * these directions and not the other. This is an arbitrary vendor's | |
81 | * choice, there is nothing which the sigrok driver could do about it. | |
82 | * Values written to registers typically cannot get read back, neither | |
83 | * verified after writing a configuration, nor queried upon startup for | |
84 | * automatic detection of the current configuration. Neither appear to | |
85 | * be there echo registers for presence and communication checks, nor | |
86 | * version identifying registers, as far as we know. | |
42f6dd55 | 87 | */ |
96dc954e GS |
88 | #define REG_RUN 0x00 /* Read capture status, write start capture. */ |
89 | #define REG_PWM_EN 0x02 /* User PWM channels on/off. */ | |
90 | #define REG_CAPT_MODE 0x03 /* Write 0x00 capture to SDRAM, 0x01 streaming. */ | |
91 | #define REG_BULK 0x08 /* Write start addr, byte count to download samples. */ | |
92 | #define REG_SAMPLING 0x10 /* Write capture config, read capture SDRAM location. */ | |
93 | #define REG_TRIGGER 0x20 /* write level and edge trigger config. */ | |
94 | #define REG_THRESHOLD 0x68 /* Write PWM config to setup input threshold DAC. */ | |
95 | #define REG_PWM1 0x70 /* Write config for user PWM1. */ | |
96 | #define REG_PWM2 0x78 /* Write config for user PWM2. */ | |
f2cd2deb | 97 | |
852c7d14 GS |
98 | /* Bit patterns to write to REG_RUN, setup run mode. */ |
99 | #define RUNMODE_HALT 0x00 | |
100 | #define RUNMODE_RUN 0x03 | |
101 | ||
b711fd8e GS |
102 | /* Bit patterns when reading from REG_RUN, get run state. */ |
103 | #define RUNSTATE_IDLE_BIT (1UL << 0) | |
104 | #define RUNSTATE_DRAM_BIT (1UL << 1) | |
105 | #define RUNSTATE_TRGD_BIT (1UL << 2) | |
106 | #define RUNSTATE_POST_BIT (1UL << 3) | |
107 | ||
f2cd2deb | 108 | static int ctrl_in(const struct sr_dev_inst *sdi, |
1ed93110 GS |
109 | uint8_t bRequest, uint16_t wValue, uint16_t wIndex, |
110 | void *data, uint16_t wLength) | |
f2cd2deb FS |
111 | { |
112 | struct sr_usb_dev_inst *usb; | |
113 | int ret; | |
114 | ||
115 | usb = sdi->conn; | |
116 | ||
411ad77c GS |
117 | ret = libusb_control_transfer(usb->devhdl, |
118 | LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_IN, | |
119 | bRequest, wValue, wIndex, data, wLength, | |
120 | DEFAULT_TIMEOUT_MS); | |
121 | if (ret != wLength) { | |
91f73872 GS |
122 | sr_dbg("USB ctrl in: %d bytes, req %d val %#x idx %d: %s.", |
123 | wLength, bRequest, wValue, wIndex, | |
124 | libusb_error_name(ret)); | |
125 | sr_err("Cannot read %d bytes from USB: %s.", | |
126 | wLength, libusb_error_name(ret)); | |
f2cd2deb FS |
127 | return SR_ERR; |
128 | } | |
129 | ||
130 | return SR_OK; | |
131 | } | |
132 | ||
133 | static int ctrl_out(const struct sr_dev_inst *sdi, | |
1ed93110 GS |
134 | uint8_t bRequest, uint16_t wValue, uint16_t wIndex, |
135 | void *data, uint16_t wLength) | |
f2cd2deb FS |
136 | { |
137 | struct sr_usb_dev_inst *usb; | |
138 | int ret; | |
139 | ||
140 | usb = sdi->conn; | |
141 | ||
411ad77c GS |
142 | ret = libusb_control_transfer(usb->devhdl, |
143 | LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT, | |
144 | bRequest, wValue, wIndex, data, wLength, | |
145 | DEFAULT_TIMEOUT_MS); | |
146 | if (ret != wLength) { | |
91f73872 GS |
147 | sr_dbg("USB ctrl out: %d bytes, req %d val %#x idx %d: %s.", |
148 | wLength, bRequest, wValue, wIndex, | |
149 | libusb_error_name(ret)); | |
150 | sr_err("Cannot write %d bytes to USB: %s.", | |
151 | wLength, libusb_error_name(ret)); | |
f2cd2deb FS |
152 | return SR_ERR; |
153 | } | |
154 | ||
155 | return SR_OK; | |
156 | } | |
157 | ||
d6f89d4b GS |
158 | /* |
159 | * Check the necessity for FPGA bitstream upload, because another upload | |
160 | * would take some 600ms which is undesirable after program startup. Try | |
161 | * to access some FPGA registers and check the values' plausibility. The | |
162 | * check should fail on the safe side, request another upload when in | |
163 | * doubt. A positive response (the request to continue operation with the | |
164 | * currently active bitstream) should be conservative. Accessing multiple | |
165 | * registers is considered cheap compared to the cost of bitstream upload. | |
166 | * | |
167 | * It helps though that both the vendor software and the sigrok driver | |
168 | * use the same bundle of MCU firmware and FPGA bitstream for any of the | |
169 | * supported models. We don't expect to successfully communicate to the | |
170 | * device yet disagree on its protocol. Ideally we would access version | |
171 | * identifying registers for improved robustness, but are not aware of | |
172 | * any. A bitstream reload can always be forced by a power cycle. | |
173 | */ | |
174 | static int check_fpga_bitstream(const struct sr_dev_inst *sdi) | |
175 | { | |
176 | uint8_t init_rsp; | |
177 | int ret; | |
178 | uint16_t run_state; | |
179 | uint8_t pwm_en; | |
180 | size_t read_len; | |
181 | uint8_t buff[sizeof(run_state)]; | |
182 | const uint8_t *rdptr; | |
183 | ||
184 | sr_dbg("Checking operation of the FPGA bitstream."); | |
185 | ||
852c7d14 | 186 | init_rsp = ~0; |
d6f89d4b GS |
187 | ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &init_rsp, sizeof(init_rsp)); |
188 | if (ret != SR_OK || init_rsp != 0) { | |
189 | sr_dbg("FPGA init query failed, or unexpected response."); | |
190 | return SR_ERR_IO; | |
191 | } | |
192 | ||
193 | read_len = sizeof(run_state); | |
194 | ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, buff, read_len); | |
195 | if (ret != SR_OK) { | |
196 | sr_dbg("FPGA register access failed (run state)."); | |
197 | return SR_ERR_IO; | |
198 | } | |
199 | rdptr = buff; | |
200 | run_state = read_u16le_inc(&rdptr); | |
201 | sr_spew("FPGA register: run state 0x%04x.", run_state); | |
202 | if (run_state && (run_state & 0x3) != 0x1) { | |
203 | sr_dbg("Unexpected FPGA register content (run state)."); | |
204 | return SR_ERR_DATA; | |
205 | } | |
206 | if (run_state && (run_state & ~0xf) != 0x85e0) { | |
207 | sr_dbg("Unexpected FPGA register content (run state)."); | |
208 | return SR_ERR_DATA; | |
209 | } | |
210 | ||
211 | read_len = sizeof(pwm_en); | |
212 | ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, buff, read_len); | |
213 | if (ret != SR_OK) { | |
214 | sr_dbg("FPGA register access failed (PWM enable)."); | |
215 | return SR_ERR_IO; | |
216 | } | |
217 | rdptr = buff; | |
218 | pwm_en = read_u8_inc(&rdptr); | |
219 | sr_spew("FPGA register: PWM enable 0x%02x.", pwm_en); | |
220 | if ((pwm_en & 0x3) != 0x0) { | |
221 | sr_dbg("Unexpected FPGA register content (PWM enable)."); | |
222 | return SR_ERR_DATA; | |
223 | } | |
224 | ||
225 | sr_info("Could re-use current FPGA bitstream. No upload required."); | |
226 | return SR_OK; | |
227 | } | |
228 | ||
1ed93110 GS |
229 | static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, |
230 | const char *bitstream_fname) | |
f2cd2deb FS |
231 | { |
232 | struct drv_context *drvc; | |
233 | struct sr_usb_dev_inst *usb; | |
234 | struct sr_resource bitstream; | |
b0d0131e | 235 | uint32_t bitstream_size; |
c3d40037 HK |
236 | uint8_t buffer[sizeof(uint32_t)]; |
237 | uint8_t *wrptr; | |
f2cd2deb | 238 | uint8_t block[4096]; |
3f48ab02 FS |
239 | int len, act_len; |
240 | unsigned int pos; | |
f2cd2deb | 241 | int ret; |
b0d0131e | 242 | unsigned int zero_pad_to; |
f2cd2deb FS |
243 | |
244 | drvc = sdi->driver->context; | |
245 | usb = sdi->conn; | |
246 | ||
9de389b1 | 247 | sr_info("Uploading FPGA bitstream '%s'.", bitstream_fname); |
f2cd2deb | 248 | |
411ad77c GS |
249 | ret = sr_resource_open(drvc->sr_ctx, &bitstream, |
250 | SR_RESOURCE_FIRMWARE, bitstream_fname); | |
f2cd2deb | 251 | if (ret != SR_OK) { |
91f73872 | 252 | sr_err("Cannot find FPGA bitstream %s.", bitstream_fname); |
f2cd2deb FS |
253 | return ret; |
254 | } | |
255 | ||
b0d0131e | 256 | bitstream_size = (uint32_t)bitstream.size; |
c3d40037 | 257 | wrptr = buffer; |
b0d0131e | 258 | write_u32le_inc(&wrptr, bitstream_size); |
411ad77c GS |
259 | ret = ctrl_out(sdi, CMD_FPGA_INIT, 0x00, 0, buffer, wrptr - buffer); |
260 | if (ret != SR_OK) { | |
91f73872 | 261 | sr_err("Cannot initiate FPGA bitstream upload."); |
f2cd2deb FS |
262 | sr_resource_close(drvc->sr_ctx, &bitstream); |
263 | return ret; | |
264 | } | |
b0d0131e GS |
265 | zero_pad_to = bitstream_size; |
266 | zero_pad_to += LA2016_EP2_PADDING - 1; | |
267 | zero_pad_to /= LA2016_EP2_PADDING; | |
268 | zero_pad_to *= LA2016_EP2_PADDING; | |
f2cd2deb FS |
269 | |
270 | pos = 0; | |
271 | while (1) { | |
3f48ab02 | 272 | if (pos < bitstream.size) { |
411ad77c GS |
273 | len = (int)sr_resource_read(drvc->sr_ctx, &bitstream, |
274 | block, sizeof(block)); | |
3f48ab02 | 275 | if (len < 0) { |
91f73872 | 276 | sr_err("Cannot read FPGA bitstream."); |
3f48ab02 FS |
277 | sr_resource_close(drvc->sr_ctx, &bitstream); |
278 | return SR_ERR; | |
279 | } | |
280 | } else { | |
96dc954e | 281 | /* Zero-pad until 'zero_pad_to'. */ |
3f48ab02 FS |
282 | len = zero_pad_to - pos; |
283 | if ((unsigned)len > sizeof(block)) | |
284 | len = sizeof(block); | |
285 | memset(&block, 0, len); | |
f2cd2deb FS |
286 | } |
287 | if (len == 0) | |
288 | break; | |
289 | ||
852c7d14 | 290 | ret = libusb_bulk_transfer(usb->devhdl, USB_EP_FPGA_BITSTREAM, |
1ed93110 | 291 | &block[0], len, &act_len, DEFAULT_TIMEOUT_MS); |
f2cd2deb | 292 | if (ret != 0) { |
91f73872 GS |
293 | sr_dbg("Cannot write FPGA bitstream, block %#x len %d: %s.", |
294 | pos, (int)len, libusb_error_name(ret)); | |
f2cd2deb FS |
295 | ret = SR_ERR; |
296 | break; | |
297 | } | |
298 | if (act_len != len) { | |
91f73872 GS |
299 | sr_dbg("Short write for FPGA bitstream, block %#x len %d: got %d.", |
300 | pos, (int)len, act_len); | |
f2cd2deb FS |
301 | ret = SR_ERR; |
302 | break; | |
303 | } | |
304 | pos += len; | |
305 | } | |
306 | sr_resource_close(drvc->sr_ctx, &bitstream); | |
307 | if (ret != 0) | |
308 | return ret; | |
91f73872 GS |
309 | sr_info("FPGA bitstream upload (%" PRIu64 " bytes) done.", |
310 | bitstream.size); | |
f2cd2deb | 311 | |
d6f89d4b GS |
312 | return SR_OK; |
313 | } | |
314 | ||
315 | static int enable_fpga_bitstream(const struct sr_dev_inst *sdi) | |
316 | { | |
317 | int ret; | |
411ad77c | 318 | uint8_t resp; |
d6f89d4b | 319 | |
411ad77c GS |
320 | ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &resp, sizeof(resp)); |
321 | if (ret != SR_OK) { | |
91f73872 | 322 | sr_err("Cannot read response after FPGA bitstream upload."); |
f2cd2deb FS |
323 | return ret; |
324 | } | |
411ad77c | 325 | if (resp != 0) { |
91f73872 | 326 | sr_err("Unexpected FPGA bitstream upload response, got 0x%02x, want 0.", |
411ad77c | 327 | resp); |
3f48ab02 FS |
328 | return SR_ERR; |
329 | } | |
852c7d14 | 330 | g_usleep(30 * 1000); |
f2cd2deb | 331 | |
411ad77c GS |
332 | ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x01, 0, NULL, 0); |
333 | if (ret != SR_OK) { | |
91f73872 | 334 | sr_err("Cannot enable FPGA after bitstream upload."); |
f2cd2deb FS |
335 | return ret; |
336 | } | |
852c7d14 | 337 | g_usleep(40 * 1000); |
d6f89d4b | 338 | |
f2cd2deb FS |
339 | return SR_OK; |
340 | } | |
341 | ||
342 | static int set_threshold_voltage(const struct sr_dev_inst *sdi, float voltage) | |
343 | { | |
344 | struct dev_context *devc; | |
f2cd2deb FS |
345 | int ret; |
346 | ||
347 | devc = sdi->priv; | |
f2cd2deb | 348 | |
1ed93110 | 349 | uint16_t duty_R79, duty_R56; |
f2ad79d1 KG |
350 | uint8_t buf[2 * sizeof(uint16_t)]; |
351 | uint8_t *wrptr; | |
352 | ||
96dc954e | 353 | /* Clamp threshold setting to valid range for LA2016. */ |
f2ad79d1 KG |
354 | if (voltage > 4.0) { |
355 | voltage = 4.0; | |
1ed93110 | 356 | } else if (voltage < -4.0) { |
f2ad79d1 KG |
357 | voltage = -4.0; |
358 | } | |
359 | ||
360 | /* | |
96dc954e GS |
361 | * Two PWM output channels feed one DAC which generates a bias |
362 | * voltage, which offsets the input probe's voltage level, and | |
363 | * in combination with the FPGA pins' fixed threshold result in | |
364 | * a programmable input threshold from the user's perspective. | |
365 | * The PWM outputs can be seen on R79 and R56 respectively, the | |
366 | * frequency is 100kHz and the duty cycle varies. The R79 PWM | |
367 | * uses three discrete settings. The R56 PWM varies with desired | |
368 | * thresholds and depends on the R79 PWM configuration. See the | |
369 | * schematics comments which discuss the formulae. | |
f2ad79d1 KG |
370 | */ |
371 | if (voltage >= 2.9) { | |
96dc954e | 372 | duty_R79 = 0; /* PWM off (0V). */ |
f2ad79d1 | 373 | duty_R56 = (uint16_t)(302 * voltage - 363); |
c34f4a89 | 374 | } else if (voltage > -0.4) { |
96dc954e | 375 | duty_R79 = 0x00f2; /* 25% duty cycle. */ |
f2ad79d1 | 376 | duty_R56 = (uint16_t)(302 * voltage + 121); |
c34f4a89 GS |
377 | } else { |
378 | duty_R79 = 0x02d7; /* 72% duty cycle. */ | |
379 | duty_R56 = (uint16_t)(302 * voltage + 1090); | |
f2ad79d1 KG |
380 | } |
381 | ||
96dc954e | 382 | /* Clamp duty register values to sensible limits. */ |
f2ad79d1 KG |
383 | if (duty_R56 < 10) { |
384 | duty_R56 = 10; | |
1ed93110 | 385 | } else if (duty_R56 > 1100) { |
f2ad79d1 KG |
386 | duty_R56 = 1100; |
387 | } | |
388 | ||
91f73872 GS |
389 | sr_dbg("Set threshold voltage %.2fV.", voltage); |
390 | sr_dbg("Duty cycle values: R56 0x%04x, R79 0x%04x.", duty_R56, duty_R79); | |
f2ad79d1 KG |
391 | |
392 | wrptr = buf; | |
393 | write_u16le_inc(&wrptr, duty_R56); | |
394 | write_u16le_inc(&wrptr, duty_R79); | |
395 | ||
396 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_THRESHOLD, 0, buf, wrptr - buf); | |
f2cd2deb | 397 | if (ret != SR_OK) { |
91f73872 | 398 | sr_err("Cannot set threshold voltage %.2fV.", voltage); |
f2cd2deb FS |
399 | return ret; |
400 | } | |
401 | devc->threshold_voltage = voltage; | |
402 | ||
403 | return SR_OK; | |
404 | } | |
405 | ||
86d77b75 | 406 | static int enable_pwm(const struct sr_dev_inst *sdi, gboolean p1, gboolean p2) |
f2cd2deb FS |
407 | { |
408 | struct dev_context *devc; | |
409 | uint8_t cfg; | |
410 | int ret; | |
411 | ||
412 | devc = sdi->priv; | |
f2cd2deb | 413 | |
86d77b75 GS |
414 | cfg = 0; |
415 | if (p1) | |
416 | cfg |= 1U << 0; | |
417 | if (p2) | |
418 | cfg |= 1U << 1; | |
91f73872 | 419 | sr_dbg("Set PWM enable %d %d. Config 0x%02x.", p1, p2, cfg); |
86d77b75 | 420 | |
42f6dd55 | 421 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, &cfg, sizeof(cfg)); |
f2cd2deb | 422 | if (ret != SR_OK) { |
91f73872 | 423 | sr_err("Cannot setup PWM enabled state."); |
f2cd2deb FS |
424 | return ret; |
425 | } | |
86d77b75 | 426 | |
f2cd2deb FS |
427 | devc->pwm_setting[0].enabled = (p1) ? 1 : 0; |
428 | devc->pwm_setting[1].enabled = (p2) ? 1 : 0; | |
429 | ||
430 | return SR_OK; | |
431 | } | |
432 | ||
86d77b75 | 433 | static int configure_pwm(const struct sr_dev_inst *sdi, uint8_t which, |
1ed93110 | 434 | float freq, float duty) |
f2cd2deb | 435 | { |
86d77b75 GS |
436 | static uint8_t ctrl_reg_tab[] = { REG_PWM1, REG_PWM2, }; |
437 | ||
f2cd2deb | 438 | struct dev_context *devc; |
86d77b75 GS |
439 | uint8_t ctrl_reg; |
440 | struct pwm_setting_dev cfg; | |
441 | struct pwm_setting *setting; | |
f2cd2deb | 442 | int ret; |
c3d40037 HK |
443 | uint8_t buf[2 * sizeof(uint32_t)]; |
444 | uint8_t *wrptr; | |
f2cd2deb FS |
445 | |
446 | devc = sdi->priv; | |
447 | ||
86d77b75 | 448 | if (which < 1 || which > ARRAY_SIZE(ctrl_reg_tab)) { |
91f73872 | 449 | sr_err("Invalid PWM channel: %d.", which); |
f2cd2deb FS |
450 | return SR_ERR; |
451 | } | |
86d77b75 | 452 | if (freq < 0 || freq > MAX_PWM_FREQ) { |
91f73872 | 453 | sr_err("Too high a PWM frequency: %.1f.", freq); |
f2cd2deb FS |
454 | return SR_ERR; |
455 | } | |
86d77b75 | 456 | if (duty < 0 || duty > 100) { |
91f73872 | 457 | sr_err("Invalid PWM duty cycle: %f.", duty); |
f2cd2deb FS |
458 | return SR_ERR; |
459 | } | |
460 | ||
86d77b75 | 461 | memset(&cfg, 0, sizeof(cfg)); |
f2cd2deb FS |
462 | cfg.period = (uint32_t)(PWM_CLOCK / freq); |
463 | cfg.duty = (uint32_t)(0.5f + (cfg.period * duty / 100.)); | |
91f73872 | 464 | sr_dbg("Set PWM%d period %d, duty %d.", which, cfg.period, cfg.duty); |
f2cd2deb | 465 | |
86d77b75 | 466 | ctrl_reg = ctrl_reg_tab[which - 1]; |
c3d40037 HK |
467 | wrptr = buf; |
468 | write_u32le_inc(&wrptr, cfg.period); | |
469 | write_u32le_inc(&wrptr, cfg.duty); | |
86d77b75 | 470 | ret = ctrl_out(sdi, CMD_FPGA_SPI, ctrl_reg, 0, buf, wrptr - buf); |
f2cd2deb | 471 | if (ret != SR_OK) { |
91f73872 GS |
472 | sr_err("Cannot setup PWM%d configuration %d %d.", |
473 | which, cfg.period, cfg.duty); | |
f2cd2deb FS |
474 | return ret; |
475 | } | |
86d77b75 | 476 | |
f2cd2deb FS |
477 | setting = &devc->pwm_setting[which - 1]; |
478 | setting->freq = freq; | |
479 | setting->duty = duty; | |
f2cd2deb FS |
480 | |
481 | return SR_OK; | |
482 | } | |
483 | ||
484 | static int set_defaults(const struct sr_dev_inst *sdi) | |
485 | { | |
486 | struct dev_context *devc; | |
487 | int ret; | |
488 | ||
489 | devc = sdi->priv; | |
490 | ||
852c7d14 | 491 | devc->capture_ratio = LA2016_DFLT_CAPT_RATIO; |
852c7d14 GS |
492 | devc->limit_samples = LA2016_DFLT_SAMPLEDEPTH; |
493 | devc->cur_samplerate = LA2016_DFLT_SAMPLERATE; | |
f2cd2deb FS |
494 | |
495 | ret = set_threshold_voltage(sdi, devc->threshold_voltage); | |
496 | if (ret) | |
497 | return ret; | |
498 | ||
86d77b75 | 499 | ret = enable_pwm(sdi, FALSE, FALSE); |
f2cd2deb FS |
500 | if (ret) |
501 | return ret; | |
502 | ||
86d77b75 | 503 | ret = configure_pwm(sdi, 1, SR_KHZ(1), 50); |
f2cd2deb FS |
504 | if (ret) |
505 | return ret; | |
506 | ||
86d77b75 | 507 | ret = configure_pwm(sdi, 2, SR_KHZ(100), 50); |
f2cd2deb FS |
508 | if (ret) |
509 | return ret; | |
510 | ||
86d77b75 | 511 | ret = enable_pwm(sdi, TRUE, TRUE); |
f2cd2deb FS |
512 | if (ret) |
513 | return ret; | |
514 | ||
515 | return SR_OK; | |
516 | } | |
517 | ||
518 | static int set_trigger_config(const struct sr_dev_inst *sdi) | |
519 | { | |
520 | struct dev_context *devc; | |
521 | struct sr_trigger *trigger; | |
66f5f697 | 522 | struct trigger_cfg cfg; |
f2cd2deb FS |
523 | GSList *stages; |
524 | GSList *channel; | |
525 | struct sr_trigger_stage *stage1; | |
526 | struct sr_trigger_match *match; | |
527 | uint16_t ch_mask; | |
528 | int ret; | |
c3d40037 HK |
529 | uint8_t buf[4 * sizeof(uint32_t)]; |
530 | uint8_t *wrptr; | |
f2cd2deb FS |
531 | |
532 | devc = sdi->priv; | |
533 | trigger = sr_session_trigger_get(sdi->session); | |
534 | ||
535 | memset(&cfg, 0, sizeof(cfg)); | |
536 | ||
537 | cfg.channels = devc->cur_channels; | |
538 | ||
539 | if (trigger && trigger->stages) { | |
540 | stages = trigger->stages; | |
541 | stage1 = stages->data; | |
542 | if (stages->next) { | |
543 | sr_err("Only one trigger stage supported for now."); | |
544 | return SR_ERR; | |
545 | } | |
546 | channel = stage1->matches; | |
547 | while (channel) { | |
548 | match = channel->data; | |
cf057ac4 | 549 | ch_mask = 1UL << match->channel->index; |
f2cd2deb FS |
550 | |
551 | switch (match->match) { | |
552 | case SR_TRIGGER_ZERO: | |
553 | cfg.level |= ch_mask; | |
554 | cfg.high_or_falling &= ~ch_mask; | |
555 | break; | |
556 | case SR_TRIGGER_ONE: | |
557 | cfg.level |= ch_mask; | |
558 | cfg.high_or_falling |= ch_mask; | |
559 | break; | |
560 | case SR_TRIGGER_RISING: | |
561 | if ((cfg.enabled & ~cfg.level)) { | |
91f73872 | 562 | sr_err("Device only supports one edge trigger."); |
f2cd2deb FS |
563 | return SR_ERR; |
564 | } | |
565 | cfg.level &= ~ch_mask; | |
566 | cfg.high_or_falling &= ~ch_mask; | |
567 | break; | |
568 | case SR_TRIGGER_FALLING: | |
569 | if ((cfg.enabled & ~cfg.level)) { | |
91f73872 | 570 | sr_err("Device only supports one edge trigger."); |
f2cd2deb FS |
571 | return SR_ERR; |
572 | } | |
573 | cfg.level &= ~ch_mask; | |
574 | cfg.high_or_falling |= ch_mask; | |
575 | break; | |
576 | default: | |
91f73872 | 577 | sr_err("Unknown trigger condition."); |
f2cd2deb FS |
578 | return SR_ERR; |
579 | } | |
580 | cfg.enabled |= ch_mask; | |
581 | channel = channel->next; | |
582 | } | |
583 | } | |
91f73872 GS |
584 | sr_dbg("Set trigger config: " |
585 | "channels 0x%04x, trigger-enabled 0x%04x, " | |
586 | "level-triggered 0x%04x, high/falling 0x%04x.", | |
587 | cfg.channels, cfg.enabled, cfg.level, cfg.high_or_falling); | |
f2cd2deb | 588 | |
cf057ac4 | 589 | devc->trigger_involved = cfg.enabled != 0; |
f2cd2deb | 590 | |
c3d40037 HK |
591 | wrptr = buf; |
592 | write_u32le_inc(&wrptr, cfg.channels); | |
593 | write_u32le_inc(&wrptr, cfg.enabled); | |
594 | write_u32le_inc(&wrptr, cfg.level); | |
595 | write_u32le_inc(&wrptr, cfg.high_or_falling); | |
852c7d14 GS |
596 | /* TODO |
597 | * Comment on this literal 16. Origin, meaning? Cannot be the | |
598 | * register offset, nor the transfer length. Is it a channels | |
599 | * count that is relevant for 16 and 32 channel models? Is it | |
600 | * an obsolete experiment? | |
601 | */ | |
42f6dd55 | 602 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_TRIGGER, 16, buf, wrptr - buf); |
f2cd2deb | 603 | if (ret != SR_OK) { |
91f73872 | 604 | sr_err("Cannot setup trigger configuration."); |
f2cd2deb FS |
605 | return ret; |
606 | } | |
607 | ||
608 | return SR_OK; | |
609 | } | |
610 | ||
611 | static int set_sample_config(const struct sr_dev_inst *sdi) | |
612 | { | |
613 | struct dev_context *devc; | |
f2cd2deb | 614 | double clock_divisor; |
adab4d91 GS |
615 | uint16_t divider_u16; |
616 | uint64_t pre_trigger_samples; | |
617 | uint64_t pre_trigger_memory; | |
618 | uint8_t buf[REG_TRIGGER - REG_SAMPLING]; /* Width of REG_SAMPLING. */ | |
c3d40037 | 619 | uint8_t *wrptr; |
adab4d91 | 620 | int ret; |
f2cd2deb FS |
621 | |
622 | devc = sdi->priv; | |
f2cd2deb | 623 | |
8b172e78 | 624 | if (devc->cur_samplerate > devc->max_samplerate) { |
91f73872 GS |
625 | sr_err("Too high a sample rate: %" PRIu64 ".", |
626 | devc->cur_samplerate); | |
f2cd2deb FS |
627 | return SR_ERR; |
628 | } | |
629 | ||
8b172e78 | 630 | clock_divisor = devc->max_samplerate / (double)devc->cur_samplerate; |
adab4d91 GS |
631 | if (clock_divisor > 65535) |
632 | return SR_ERR_ARG; | |
633 | divider_u16 = (uint16_t)(clock_divisor + 0.5); | |
634 | devc->cur_samplerate = devc->max_samplerate / divider_u16; | |
f2cd2deb FS |
635 | |
636 | if (devc->limit_samples > MAX_SAMPLE_DEPTH) { | |
91f73872 GS |
637 | sr_err("Too high a sample depth: %" PRIu64 ".", |
638 | devc->limit_samples); | |
f2cd2deb FS |
639 | return SR_ERR; |
640 | } | |
f2cd2deb | 641 | |
adab4d91 GS |
642 | /* |
643 | * The acquisition configuration communicates "pre-trigger" | |
644 | * specs in several formats. sigrok users provide a percentage | |
645 | * (0-100%), which translates to a pre-trigger samples count | |
646 | * (assuming that a total samples count limit was specified). | |
647 | * The device supports hardware compression, which depends on | |
648 | * slowly changing input data to be effective. Fast changing | |
649 | * input data may occupy more space in sample memory than its | |
650 | * uncompressed form would. This is why a third parameter can | |
651 | * limit the amount of sample memory to use for pre-trigger | |
652 | * data. Only the upper 24 bits of that memory size spec get | |
653 | * communicated to the device (written to its FPGA register). | |
654 | */ | |
655 | pre_trigger_samples = devc->limit_samples * devc->capture_ratio / 100; | |
656 | pre_trigger_memory = LA2016_PRE_MEM_LIMIT_BASE; | |
657 | pre_trigger_memory *= devc->capture_ratio; | |
658 | pre_trigger_memory /= 100; | |
f2cd2deb | 659 | |
adab4d91 GS |
660 | sr_dbg("Set sample config: %" PRIu64 "kHz, %" PRIu64 " samples.", |
661 | devc->cur_samplerate / 1000, devc->limit_samples); | |
662 | sr_dbg("Capture ratio %" PRIu64 "%%, count %" PRIu64 ", mem %" PRIu64 ".", | |
663 | devc->capture_ratio, pre_trigger_samples, pre_trigger_memory); | |
f2cd2deb | 664 | |
b1a17c1a GS |
665 | /* |
666 | * The acquisition configuration occupies a total of 16 bytes: | |
667 | * - A 34bit total samples count limit (up to 10 billions) that | |
668 | * is kept in a 40bit register. | |
669 | * - A 34bit pre-trigger samples count limit (up to 10 billions) | |
670 | * in another 40bit register. | |
671 | * - A 32bit pre-trigger memory space limit (in bytes) of which | |
672 | * the upper 24bits are kept in an FPGA register. | |
673 | * - A 16bit clock divider which gets applied to the maximum | |
674 | * samplerate of the device. | |
675 | * - An 8bit register of unknown meaning. Currently always 0. | |
676 | */ | |
c3d40037 | 677 | wrptr = buf; |
b1a17c1a GS |
678 | write_u40le_inc(&wrptr, devc->limit_samples); |
679 | write_u40le_inc(&wrptr, pre_trigger_samples); | |
680 | write_u24le_inc(&wrptr, pre_trigger_memory >> 8); | |
adab4d91 | 681 | write_u16le_inc(&wrptr, divider_u16); |
0d8e1ffc | 682 | write_u8_inc(&wrptr, 0); |
42f6dd55 | 683 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, wrptr - buf); |
f2cd2deb | 684 | if (ret != SR_OK) { |
91f73872 | 685 | sr_err("Cannot setup acquisition configuration."); |
f2cd2deb FS |
686 | return ret; |
687 | } | |
688 | ||
689 | return SR_OK; | |
690 | } | |
691 | ||
96dc954e GS |
692 | /* |
693 | * FPGA register REG_RUN holds the run state (u16le format). Bit fields | |
694 | * of interest: | |
695 | * bit 0: value 1 = idle | |
696 | * bit 1: value 1 = writing to SDRAM | |
697 | * bit 2: value 0 = waiting for trigger, 1 = trigger seen | |
698 | * bit 3: value 0 = pretrigger sampling, 1 = posttrigger sampling | |
699 | * The meaning of other bit fields is unknown. | |
7601dca7 | 700 | * |
96dc954e | 701 | * Typical values in order of appearance during execution: |
b711fd8e GS |
702 | * 0x85e1: idle, no acquisition pending |
703 | * IDLE set, TRGD don't care, POST don't care; DRAM don't care | |
704 | * "In idle state." Takes precedence over all others. | |
96dc954e GS |
705 | * 0x85e2: pre-sampling, samples before the trigger position, |
706 | * when capture ratio > 0% | |
b711fd8e GS |
707 | * IDLE clear, TRGD clear, POST clear; DRAM don't care |
708 | * "Not idle any more, no post yet, not triggered yet." | |
96dc954e GS |
709 | * 0x85ea: pre-sampling complete, now waiting for the trigger |
710 | * (whilst sampling continuously) | |
b711fd8e GS |
711 | * IDLE clear, TRGD clear, POST set; DRAM don't care |
712 | * "Post set thus after pre, not triggered yet" | |
96dc954e | 713 | * 0x85ee: trigger seen, capturing post-trigger samples, running |
b711fd8e GS |
714 | * IDLE clear, TRGD set, POST set; DRAM don't care |
715 | * "Triggered and in post, not idle yet." | |
96dc954e | 716 | * 0x85ed: idle |
b711fd8e GS |
717 | * IDLE set, TRGD don't care, POST don't care; DRAM don't care |
718 | * "In idle state." TRGD/POST don't care, same meaning as above. | |
f2cd2deb | 719 | */ |
b711fd8e GS |
720 | static const uint16_t runstate_mask_idle = RUNSTATE_IDLE_BIT; |
721 | static const uint16_t runstate_patt_idle = RUNSTATE_IDLE_BIT; | |
722 | static const uint16_t runstate_mask_step = | |
723 | RUNSTATE_IDLE_BIT | RUNSTATE_TRGD_BIT | RUNSTATE_POST_BIT; | |
724 | static const uint16_t runstate_patt_pre_trig = 0; | |
725 | static const uint16_t runstate_patt_wait_trig = RUNSTATE_POST_BIT; | |
726 | static const uint16_t runstate_patt_post_trig = | |
727 | RUNSTATE_TRGD_BIT | RUNSTATE_POST_BIT; | |
728 | ||
f2cd2deb FS |
729 | static uint16_t run_state(const struct sr_dev_inst *sdi) |
730 | { | |
21d68fd9 GS |
731 | static uint16_t previous_state; |
732 | ||
f2cd2deb | 733 | int ret; |
21d68fd9 GS |
734 | uint16_t state; |
735 | uint8_t buff[sizeof(state)]; | |
736 | const uint8_t *rdptr; | |
737 | const char *label; | |
f2cd2deb | 738 | |
411ad77c GS |
739 | ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, buff, sizeof(state)); |
740 | if (ret != SR_OK) { | |
91f73872 | 741 | sr_err("Cannot read run state."); |
f2cd2deb FS |
742 | return ret; |
743 | } | |
21d68fd9 GS |
744 | rdptr = buff; |
745 | state = read_u16le_inc(&rdptr); | |
7601dca7 | 746 | |
96dc954e GS |
747 | /* |
748 | * Avoid flooding the log, only dump values as they change. | |
749 | * The routine is called about every 50ms. | |
7601dca7 | 750 | */ |
b711fd8e GS |
751 | if (state == previous_state) |
752 | return state; | |
753 | ||
754 | previous_state = state; | |
755 | label = NULL; | |
756 | if ((state & runstate_mask_idle) == runstate_patt_idle) | |
757 | label = "idle"; | |
758 | if ((state & runstate_mask_step) == runstate_patt_pre_trig) | |
759 | label = "pre-trigger sampling"; | |
760 | if ((state & runstate_mask_step) == runstate_patt_wait_trig) | |
761 | label = "sampling, waiting for trigger"; | |
762 | if ((state & runstate_mask_step) == runstate_patt_post_trig) | |
763 | label = "post-trigger sampling"; | |
764 | if (label && *label) | |
765 | sr_dbg("Run state: 0x%04x (%s).", state, label); | |
766 | else | |
767 | sr_dbg("Run state: 0x%04x.", state); | |
f2cd2deb FS |
768 | |
769 | return state; | |
770 | } | |
771 | ||
cf057ac4 | 772 | static int la2016_is_idle(const struct sr_dev_inst *sdi) |
c34f4a89 GS |
773 | { |
774 | uint16_t state; | |
775 | ||
776 | state = run_state(sdi); | |
b711fd8e | 777 | if ((state & runstate_mask_idle) == runstate_patt_idle) |
c34f4a89 GS |
778 | return 1; |
779 | ||
780 | return 0; | |
781 | } | |
782 | ||
783 | static int set_run_mode(const struct sr_dev_inst *sdi, uint8_t mode) | |
f2cd2deb FS |
784 | { |
785 | int ret; | |
786 | ||
411ad77c GS |
787 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_RUN, 0, &mode, sizeof(mode)); |
788 | if (ret != SR_OK) { | |
c34f4a89 | 789 | sr_err("Cannot configure run mode %d.", mode); |
f2cd2deb FS |
790 | return ret; |
791 | } | |
792 | ||
793 | return SR_OK; | |
794 | } | |
795 | ||
796 | static int get_capture_info(const struct sr_dev_inst *sdi) | |
797 | { | |
798 | struct dev_context *devc; | |
799 | int ret; | |
c3d40037 HK |
800 | uint8_t buf[3 * sizeof(uint32_t)]; |
801 | const uint8_t *rdptr; | |
f2cd2deb FS |
802 | |
803 | devc = sdi->priv; | |
804 | ||
411ad77c GS |
805 | ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, sizeof(buf)); |
806 | if (ret != SR_OK) { | |
91f73872 | 807 | sr_err("Cannot read capture info."); |
f2cd2deb FS |
808 | return ret; |
809 | } | |
c3d40037 HK |
810 | |
811 | rdptr = buf; | |
812 | devc->info.n_rep_packets = read_u32le_inc(&rdptr); | |
813 | devc->info.n_rep_packets_before_trigger = read_u32le_inc(&rdptr); | |
814 | devc->info.write_pos = read_u32le_inc(&rdptr); | |
f2cd2deb | 815 | |
cf057ac4 | 816 | sr_dbg("Capture info: n_rep_packets: 0x%08x/%d, before_trigger: 0x%08x/%d, write_pos: 0x%08x/%d.", |
1ed93110 GS |
817 | devc->info.n_rep_packets, devc->info.n_rep_packets, |
818 | devc->info.n_rep_packets_before_trigger, | |
819 | devc->info.n_rep_packets_before_trigger, | |
820 | devc->info.write_pos, devc->info.write_pos); | |
f2cd2deb | 821 | |
852c7d14 GS |
822 | if (devc->info.n_rep_packets % NUM_PACKETS_IN_CHUNK) { |
823 | sr_warn("Unexpected packets count %lu, not a multiple of %d.", | |
824 | (unsigned long)devc->info.n_rep_packets, | |
825 | NUM_PACKETS_IN_CHUNK); | |
91f73872 | 826 | } |
f2cd2deb FS |
827 | |
828 | return SR_OK; | |
829 | } | |
830 | ||
1ed93110 GS |
831 | SR_PRIV int la2016_upload_firmware(struct sr_context *sr_ctx, |
832 | libusb_device *dev, uint16_t product_id) | |
f2cd2deb FS |
833 | { |
834 | char fw_file[1024]; | |
835 | snprintf(fw_file, sizeof(fw_file) - 1, UC_FIRMWARE, product_id); | |
40a0b2f4 | 836 | return ezusb_upload_firmware(sr_ctx, dev, USB_CONFIGURATION, fw_file); |
f2cd2deb FS |
837 | } |
838 | ||
839 | SR_PRIV int la2016_setup_acquisition(const struct sr_dev_inst *sdi) | |
840 | { | |
841 | struct dev_context *devc; | |
842 | int ret; | |
843 | uint8_t cmd; | |
844 | ||
845 | devc = sdi->priv; | |
846 | ||
847 | ret = set_threshold_voltage(sdi, devc->threshold_voltage); | |
848 | if (ret != SR_OK) | |
849 | return ret; | |
850 | ||
851 | cmd = 0; | |
411ad77c GS |
852 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_CAPT_MODE, 0, &cmd, sizeof(cmd)); |
853 | if (ret != SR_OK) { | |
91f73872 | 854 | sr_err("Cannot send command to stop sampling."); |
f2cd2deb FS |
855 | return ret; |
856 | } | |
857 | ||
858 | ret = set_trigger_config(sdi); | |
859 | if (ret != SR_OK) | |
860 | return ret; | |
861 | ||
862 | ret = set_sample_config(sdi); | |
863 | if (ret != SR_OK) | |
864 | return ret; | |
865 | ||
866 | return SR_OK; | |
867 | } | |
868 | ||
869 | SR_PRIV int la2016_start_acquisition(const struct sr_dev_inst *sdi) | |
870 | { | |
3ebc1cb2 GS |
871 | int ret; |
872 | ||
852c7d14 | 873 | ret = set_run_mode(sdi, RUNMODE_RUN); |
3ebc1cb2 GS |
874 | if (ret != SR_OK) |
875 | return ret; | |
876 | ||
877 | return SR_OK; | |
f2cd2deb FS |
878 | } |
879 | ||
3ebc1cb2 | 880 | static int la2016_stop_acquisition(const struct sr_dev_inst *sdi) |
f2cd2deb | 881 | { |
3ebc1cb2 GS |
882 | int ret; |
883 | ||
852c7d14 | 884 | ret = set_run_mode(sdi, RUNMODE_HALT); |
3ebc1cb2 GS |
885 | if (ret != SR_OK) |
886 | return ret; | |
887 | ||
888 | return SR_OK; | |
f2cd2deb FS |
889 | } |
890 | ||
891 | SR_PRIV int la2016_abort_acquisition(const struct sr_dev_inst *sdi) | |
892 | { | |
3ebc1cb2 GS |
893 | int ret; |
894 | struct dev_context *devc; | |
895 | ||
896 | ret = la2016_stop_acquisition(sdi); | |
897 | if (ret != SR_OK) | |
898 | return ret; | |
899 | ||
900 | devc = sdi ? sdi->priv : NULL; | |
901 | if (devc && devc->transfer) | |
902 | libusb_cancel_transfer(devc->transfer); | |
903 | ||
904 | return SR_OK; | |
f2cd2deb FS |
905 | } |
906 | ||
cf057ac4 | 907 | static int la2016_start_download(const struct sr_dev_inst *sdi, |
1ed93110 | 908 | libusb_transfer_cb_fn cb) |
f2cd2deb FS |
909 | { |
910 | struct dev_context *devc; | |
911 | struct sr_usb_dev_inst *usb; | |
912 | int ret; | |
c3d40037 HK |
913 | uint8_t wrbuf[2 * sizeof(uint32_t)]; |
914 | uint8_t *wrptr; | |
f2cd2deb FS |
915 | uint32_t to_read; |
916 | uint8_t *buffer; | |
917 | ||
918 | devc = sdi->priv; | |
919 | usb = sdi->conn; | |
920 | ||
411ad77c GS |
921 | ret = get_capture_info(sdi); |
922 | if (ret != SR_OK) | |
f2cd2deb FS |
923 | return ret; |
924 | ||
c3d40037 HK |
925 | devc->n_transfer_packets_to_read = devc->info.n_rep_packets / NUM_PACKETS_IN_CHUNK; |
926 | devc->n_bytes_to_read = devc->n_transfer_packets_to_read * TRANSFER_PACKET_LENGTH; | |
f2cd2deb FS |
927 | devc->read_pos = devc->info.write_pos - devc->n_bytes_to_read; |
928 | devc->n_reps_until_trigger = devc->info.n_rep_packets_before_trigger; | |
929 | ||
91f73872 | 930 | sr_dbg("Want to read %u xfer-packets starting from pos %" PRIu32 ".", |
1ed93110 | 931 | devc->n_transfer_packets_to_read, devc->read_pos); |
f2cd2deb | 932 | |
411ad77c GS |
933 | ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0); |
934 | if (ret != SR_OK) { | |
91f73872 | 935 | sr_err("Cannot reset USB bulk state."); |
f2cd2deb FS |
936 | return ret; |
937 | } | |
91f73872 GS |
938 | sr_dbg("Will read from 0x%08lx, 0x%08x bytes.", |
939 | (unsigned long)devc->read_pos, devc->n_bytes_to_read); | |
c3d40037 HK |
940 | wrptr = wrbuf; |
941 | write_u32le_inc(&wrptr, devc->read_pos); | |
942 | write_u32le_inc(&wrptr, devc->n_bytes_to_read); | |
411ad77c GS |
943 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_BULK, 0, wrbuf, wrptr - wrbuf); |
944 | if (ret != SR_OK) { | |
91f73872 | 945 | sr_err("Cannot send USB bulk config."); |
f2cd2deb FS |
946 | return ret; |
947 | } | |
411ad77c GS |
948 | ret = ctrl_out(sdi, CMD_BULK_START, 0x00, 0, NULL, 0); |
949 | if (ret != SR_OK) { | |
91f73872 | 950 | sr_err("Cannot unblock USB bulk transfers."); |
f2cd2deb FS |
951 | return ret; |
952 | } | |
953 | ||
96dc954e GS |
954 | /* |
955 | * Pick a buffer size for all USB transfers. The buffer size | |
956 | * must be a multiple of the endpoint packet size. And cannot | |
957 | * exceed a maximum value. | |
958 | */ | |
f2cd2deb | 959 | to_read = devc->n_bytes_to_read; |
96dc954e GS |
960 | if (to_read >= LA2016_USB_BUFSZ) /* Multiple transfers. */ |
961 | to_read = LA2016_USB_BUFSZ; | |
962 | else /* One transfer. */ | |
e847645b | 963 | to_read = (to_read + (LA2016_EP6_PKTSZ-1)) & ~(LA2016_EP6_PKTSZ-1); |
f2cd2deb FS |
964 | buffer = g_try_malloc(to_read); |
965 | if (!buffer) { | |
91f73872 GS |
966 | sr_dbg("USB bulk transfer size %d bytes.", (int)to_read); |
967 | sr_err("Cannot allocate buffer for USB bulk transfer."); | |
f2cd2deb FS |
968 | return SR_ERR_MALLOC; |
969 | } | |
970 | ||
971 | devc->transfer = libusb_alloc_transfer(0); | |
852c7d14 GS |
972 | libusb_fill_bulk_transfer(devc->transfer, |
973 | usb->devhdl, USB_EP_CAPTURE_DATA | LIBUSB_ENDPOINT_IN, | |
411ad77c | 974 | buffer, to_read, cb, (void *)sdi, DEFAULT_TIMEOUT_MS); |
f2cd2deb | 975 | |
411ad77c GS |
976 | ret = libusb_submit_transfer(devc->transfer); |
977 | if (ret != 0) { | |
91f73872 | 978 | sr_err("Cannot submit USB transfer: %s.", libusb_error_name(ret)); |
f2cd2deb FS |
979 | libusb_free_transfer(devc->transfer); |
980 | devc->transfer = NULL; | |
981 | g_free(buffer); | |
982 | return SR_ERR; | |
983 | } | |
984 | ||
985 | return SR_OK; | |
986 | } | |
987 | ||
480efba2 GS |
988 | /* |
989 | * A chunk (received via USB) contains a number of transfers (USB length | |
990 | * divided by 16) which contain a number of packets (5 per transfer) which | |
991 | * contain a number of samples (8bit repeat count per 16bit sample data). | |
992 | */ | |
dfac9592 | 993 | static void send_chunk(struct sr_dev_inst *sdi, |
480efba2 | 994 | const uint8_t *packets, size_t num_xfers) |
dfac9592 GS |
995 | { |
996 | struct dev_context *devc; | |
997 | struct sr_datafeed_logic logic; | |
998 | struct sr_datafeed_packet sr_packet; | |
999 | unsigned int max_samples, n_samples, total_samples, free_n_samples; | |
480efba2 | 1000 | size_t num_pkts; |
cf057ac4 | 1001 | gboolean do_signal_trigger; |
fe953391 | 1002 | uint8_t *wp; |
dfac9592 | 1003 | const uint8_t *rp; |
480efba2 GS |
1004 | uint16_t sample_value; |
1005 | size_t repetitions; | |
1006 | uint8_t sample_buff[sizeof(sample_value)]; | |
dfac9592 GS |
1007 | |
1008 | devc = sdi->priv; | |
1009 | ||
fe953391 | 1010 | logic.unitsize = sizeof(sample_buff); |
dfac9592 GS |
1011 | logic.data = devc->convbuffer; |
1012 | ||
1013 | sr_packet.type = SR_DF_LOGIC; | |
1014 | sr_packet.payload = &logic; | |
1015 | ||
fe953391 | 1016 | max_samples = devc->convbuffer_size / sizeof(sample_buff); |
dfac9592 | 1017 | n_samples = 0; |
fe953391 | 1018 | wp = devc->convbuffer; |
dfac9592 | 1019 | total_samples = 0; |
cf057ac4 | 1020 | do_signal_trigger = FALSE; |
dfac9592 | 1021 | |
cf057ac4 | 1022 | if (devc->trigger_involved && !devc->trigger_marked && devc->info.n_rep_packets_before_trigger == 0) { |
dfac9592 | 1023 | std_session_send_df_trigger(sdi); |
cf057ac4 | 1024 | devc->trigger_marked = TRUE; |
dfac9592 GS |
1025 | } |
1026 | ||
1027 | rp = packets; | |
480efba2 GS |
1028 | while (num_xfers--) { |
1029 | num_pkts = NUM_PACKETS_IN_CHUNK; | |
1030 | while (num_pkts--) { | |
1031 | /* | |
1032 | * Flush the conversion buffer when a trigger | |
1033 | * location needs to get communicated, or when | |
1034 | * an to-get-expected sample repetition count | |
1035 | * would no longer fit into the buffer. | |
1036 | */ | |
dfac9592 GS |
1037 | free_n_samples = max_samples - n_samples; |
1038 | if (free_n_samples < 256 || do_signal_trigger) { | |
480efba2 | 1039 | logic.length = n_samples * sizeof(sample_buff);; |
dfac9592 GS |
1040 | sr_session_send(sdi, &sr_packet); |
1041 | n_samples = 0; | |
fe953391 | 1042 | wp = devc->convbuffer; |
dfac9592 GS |
1043 | if (do_signal_trigger) { |
1044 | std_session_send_df_trigger(sdi); | |
cf057ac4 | 1045 | do_signal_trigger = FALSE; |
dfac9592 GS |
1046 | } |
1047 | } | |
1048 | ||
480efba2 | 1049 | sample_value = read_u16le_inc(&rp); |
dfac9592 | 1050 | repetitions = read_u8_inc(&rp); |
dfac9592 GS |
1051 | |
1052 | n_samples += repetitions; | |
1053 | total_samples += repetitions; | |
1054 | devc->total_samples += repetitions; | |
480efba2 GS |
1055 | |
1056 | write_u16le(sample_buff, sample_value); | |
1057 | while (repetitions--) { | |
1058 | memcpy(wp, sample_buff, logic.unitsize); | |
1059 | wp += logic.unitsize; | |
1060 | } | |
1061 | ||
cf057ac4 GS |
1062 | if (devc->trigger_involved && !devc->trigger_marked) { |
1063 | if (!--devc->n_reps_until_trigger) { | |
1064 | devc->trigger_marked = TRUE; | |
1065 | do_signal_trigger = TRUE; | |
91f73872 | 1066 | sr_dbg("Trigger position after %" PRIu64 " samples, %.6fms.", |
1ed93110 GS |
1067 | devc->total_samples, |
1068 | (double)devc->total_samples / devc->cur_samplerate * 1e3); | |
dfac9592 GS |
1069 | } |
1070 | } | |
1071 | } | |
1072 | (void)read_u8_inc(&rp); /* Skip sequence number. */ | |
1073 | } | |
1074 | if (n_samples) { | |
fe953391 | 1075 | logic.length = n_samples * logic.unitsize; |
dfac9592 GS |
1076 | sr_session_send(sdi, &sr_packet); |
1077 | if (do_signal_trigger) { | |
1078 | std_session_send_df_trigger(sdi); | |
1079 | } | |
1080 | } | |
91f73872 | 1081 | sr_dbg("Send_chunk done after %u samples.", total_samples); |
dfac9592 GS |
1082 | } |
1083 | ||
1084 | static void LIBUSB_CALL receive_transfer(struct libusb_transfer *transfer) | |
1085 | { | |
1086 | struct sr_dev_inst *sdi; | |
1087 | struct dev_context *devc; | |
1088 | struct sr_usb_dev_inst *usb; | |
1089 | int ret; | |
1090 | ||
1091 | sdi = transfer->user_data; | |
1092 | devc = sdi->priv; | |
1093 | usb = sdi->conn; | |
1094 | ||
1095 | sr_dbg("receive_transfer(): status %s received %d bytes.", | |
1ed93110 | 1096 | libusb_error_name(transfer->status), transfer->actual_length); |
dfac9592 GS |
1097 | |
1098 | if (transfer->status == LIBUSB_TRANSFER_TIMED_OUT) { | |
91f73872 | 1099 | sr_err("USB bulk transfer timeout."); |
cf057ac4 | 1100 | devc->download_finished = TRUE; |
dfac9592 GS |
1101 | } |
1102 | send_chunk(sdi, transfer->buffer, transfer->actual_length / TRANSFER_PACKET_LENGTH); | |
1103 | ||
1104 | devc->n_bytes_to_read -= transfer->actual_length; | |
1105 | if (devc->n_bytes_to_read) { | |
1106 | uint32_t to_read = devc->n_bytes_to_read; | |
96dc954e GS |
1107 | /* |
1108 | * Determine read size for the next USB transfer. Make | |
1109 | * the buffer size a multiple of the endpoint packet | |
1110 | * size. Don't exceed a maximum value. | |
1111 | */ | |
dfac9592 GS |
1112 | if (to_read >= LA2016_USB_BUFSZ) |
1113 | to_read = LA2016_USB_BUFSZ; | |
96dc954e | 1114 | else |
dfac9592 | 1115 | to_read = (to_read + (LA2016_EP6_PKTSZ-1)) & ~(LA2016_EP6_PKTSZ-1); |
852c7d14 GS |
1116 | libusb_fill_bulk_transfer(transfer, |
1117 | usb->devhdl, USB_EP_CAPTURE_DATA | LIBUSB_ENDPOINT_IN, | |
1118 | transfer->buffer, to_read, | |
dfac9592 GS |
1119 | receive_transfer, (void *)sdi, DEFAULT_TIMEOUT_MS); |
1120 | ||
411ad77c GS |
1121 | ret = libusb_submit_transfer(transfer); |
1122 | if (ret == 0) | |
dfac9592 | 1123 | return; |
91f73872 GS |
1124 | sr_err("Cannot submit another USB transfer: %s.", |
1125 | libusb_error_name(ret)); | |
dfac9592 GS |
1126 | } |
1127 | ||
1128 | g_free(transfer->buffer); | |
1129 | libusb_free_transfer(transfer); | |
cf057ac4 | 1130 | devc->download_finished = TRUE; |
dfac9592 GS |
1131 | } |
1132 | ||
1133 | SR_PRIV int la2016_receive_data(int fd, int revents, void *cb_data) | |
1134 | { | |
1135 | const struct sr_dev_inst *sdi; | |
1136 | struct dev_context *devc; | |
1137 | struct drv_context *drvc; | |
1138 | struct timeval tv; | |
1139 | ||
1140 | (void)fd; | |
1141 | (void)revents; | |
1142 | ||
1143 | sdi = cb_data; | |
1144 | devc = sdi->priv; | |
1145 | drvc = sdi->driver->context; | |
1146 | ||
cf057ac4 GS |
1147 | if (!devc->completion_seen) { |
1148 | if (!la2016_is_idle(sdi)) { | |
96dc954e | 1149 | /* Not yet ready for sample data download. */ |
dfac9592 GS |
1150 | return TRUE; |
1151 | } | |
cf057ac4 GS |
1152 | devc->completion_seen = TRUE; |
1153 | devc->download_finished = FALSE; | |
1154 | devc->trigger_marked = FALSE; | |
dfac9592 | 1155 | devc->total_samples = 0; |
96dc954e | 1156 | /* We can start downloading sample data. */ |
cf057ac4 | 1157 | if (la2016_start_download(sdi, receive_transfer) != SR_OK) { |
91f73872 | 1158 | sr_err("Cannot start acquisition data download."); |
dfac9592 GS |
1159 | return FALSE; |
1160 | } | |
91f73872 | 1161 | sr_dbg("Acquisition data download started."); |
dfac9592 GS |
1162 | std_session_send_df_frame_begin(sdi); |
1163 | ||
1164 | return TRUE; | |
1165 | } | |
1166 | ||
1167 | tv.tv_sec = tv.tv_usec = 0; | |
1168 | libusb_handle_events_timeout(drvc->sr_ctx->libusb_ctx, &tv); | |
1169 | ||
cf057ac4 | 1170 | if (devc->download_finished) { |
91f73872 | 1171 | sr_dbg("Download finished, post processing."); |
dfac9592 GS |
1172 | std_session_send_df_frame_end(sdi); |
1173 | ||
1174 | usb_source_remove(sdi->session, drvc->sr_ctx); | |
1175 | std_session_send_df_end(sdi); | |
1176 | ||
1177 | la2016_stop_acquisition(sdi); | |
1178 | ||
1179 | g_free(devc->convbuffer); | |
1180 | devc->convbuffer = NULL; | |
1181 | ||
1182 | devc->transfer = NULL; | |
1183 | ||
91f73872 | 1184 | sr_dbg("Download finished, done post processing."); |
dfac9592 GS |
1185 | } |
1186 | ||
1187 | return TRUE; | |
1188 | } | |
1189 | ||
f2cd2deb FS |
1190 | SR_PRIV int la2016_init_device(const struct sr_dev_inst *sdi) |
1191 | { | |
8b172e78 | 1192 | struct dev_context *devc; |
f2cd2deb | 1193 | uint16_t state; |
9de389b1 | 1194 | uint8_t buf[8]; |
43d2e52f GS |
1195 | const uint8_t *rdptr; |
1196 | uint8_t date_yy, date_mm; | |
1197 | uint8_t dinv_yy, dinv_mm; | |
9de389b1 | 1198 | uint8_t magic; |
d6f89d4b | 1199 | const char *bitstream_fn; |
9de389b1 | 1200 | int ret; |
f2cd2deb | 1201 | |
8b172e78 KG |
1202 | devc = sdi->priv; |
1203 | ||
96dc954e | 1204 | /* |
43d2e52f GS |
1205 | * Four EEPROM bytes at offset 0x20 are the manufacturing date, |
1206 | * year and month in BCD format, followed by inverted values for | |
1207 | * consistency checks. For example bytes 20 04 df fb translate | |
1208 | * to 2020-04. This information can help identify the vintage of | |
1209 | * devices when unknown magic numbers are seen. | |
9de389b1 | 1210 | */ |
43d2e52f GS |
1211 | ret = ctrl_in(sdi, CMD_EEPROM, 0x20, 0, buf, 4 * sizeof(uint8_t)); |
1212 | if (ret != SR_OK) { | |
1213 | sr_err("Cannot read manufacture date in EEPROM."); | |
1ed93110 | 1214 | } else { |
43d2e52f GS |
1215 | rdptr = &buf[0]; |
1216 | date_yy = read_u8_inc(&rdptr); | |
1217 | date_mm = read_u8_inc(&rdptr); | |
1218 | dinv_yy = read_u8_inc(&rdptr); | |
1219 | dinv_mm = read_u8_inc(&rdptr); | |
1220 | sr_info("Manufacture date: 20%02hx-%02hx.", date_yy, date_mm); | |
1221 | if ((date_mm ^ dinv_mm) != 0xff || (date_yy ^ dinv_yy) != 0xff) | |
1222 | sr_warn("Manufacture date fails checksum test."); | |
f2cd2deb | 1223 | } |
f2cd2deb | 1224 | |
9de389b1 | 1225 | /* |
96dc954e GS |
1226 | * Several Kingst logic analyzer devices share the same USB VID |
1227 | * and PID. The product ID determines which MCU firmware to load. | |
1228 | * The MCU firmware provides access to EEPROM content which then | |
1229 | * allows to identify the device model. Which in turn determines | |
1230 | * which FPGA bitstream to load. Eight bytes at offset 0x08 are | |
1231 | * to get inspected. | |
9de389b1 | 1232 | * |
96dc954e GS |
1233 | * EEPROM content for model identification is kept redundantly |
1234 | * in memory. The values are stored in verbatim and in inverted | |
1235 | * form, multiple copies are kept at different offsets. Example | |
1236 | * data: | |
9de389b1 | 1237 | * |
96dc954e GS |
1238 | * magic 0x08 |
1239 | * | ~magic 0xf7 | |
1240 | * | | | |
1241 | * 08f7000008f710ef | |
1242 | * | | | |
1243 | * | ~magic backup | |
1244 | * magic backup | |
9de389b1 | 1245 | * |
96dc954e GS |
1246 | * Exclusively inspecting the magic byte appears to be sufficient, |
1247 | * other fields seem to be 'don't care'. | |
9de389b1 | 1248 | * |
96dc954e GS |
1249 | * magic 2 == LA2016 using "kingst-la2016-fpga.bitstream" |
1250 | * magic 3 == LA1016 using "kingst-la1016-fpga.bitstream" | |
1251 | * magic 8 == LA2016a using "kingst-la2016a1-fpga.bitstream" | |
1252 | * (latest v1.3.0 PCB, perhaps others) | |
1253 | * magic 9 == LA1016a using "kingst-la1016a1-fpga.bitstream" | |
1254 | * (latest v1.3.0 PCB, perhaps others) | |
9de389b1 | 1255 | * |
96dc954e GS |
1256 | * When EEPROM content does not match the hardware configuration |
1257 | * (the board layout), the software may load but yield incorrect | |
1258 | * results (like swapped channels). The FPGA bitstream itself | |
1259 | * will authenticate with IC U10 and fail when its capabilities | |
1260 | * do not match the hardware model. An LA1016 won't become a | |
1261 | * LA2016 by faking its EEPROM content. | |
9de389b1 | 1262 | */ |
9de389b1 | 1263 | if ((ret = ctrl_in(sdi, CMD_EEPROM, 0x08, 0, &buf, sizeof(buf))) != SR_OK) { |
91f73872 | 1264 | sr_err("Cannot read EEPROM device identifier bytes."); |
f2cd2deb FS |
1265 | return ret; |
1266 | } | |
43d2e52f | 1267 | if ((buf[0] ^ buf[1]) == 0xff) { |
96dc954e | 1268 | /* Primary copy of magic passes complement check. */ |
43d2e52f | 1269 | sr_dbg("Using primary copy of device type magic number."); |
9de389b1 | 1270 | magic = buf[0]; |
43d2e52f | 1271 | } else if ((buf[4] ^ buf[5]) == 0xff) { |
96dc954e | 1272 | /* Backup copy of magic passes complement check. */ |
91f73872 | 1273 | sr_dbg("Using backup copy of device type magic number."); |
9de389b1 | 1274 | magic = buf[4]; |
43d2e52f GS |
1275 | } else { |
1276 | sr_err("Cannot find consistent device type identification."); | |
1277 | magic = 0; | |
f2cd2deb | 1278 | } |
91f73872 | 1279 | sr_dbg("Device type: magic number is %hhu.", magic); |
9de389b1 | 1280 | |
96dc954e | 1281 | /* Select the FPGA bitstream depending on the model. */ |
9de389b1 KG |
1282 | switch (magic) { |
1283 | case 2: | |
d6f89d4b | 1284 | bitstream_fn = FPGA_FW_LA2016; |
8b172e78 KG |
1285 | devc->max_samplerate = MAX_SAMPLE_RATE_LA2016; |
1286 | break; | |
1287 | case 3: | |
d6f89d4b | 1288 | bitstream_fn = FPGA_FW_LA1016; |
8b172e78 | 1289 | devc->max_samplerate = MAX_SAMPLE_RATE_LA1016; |
9de389b1 KG |
1290 | break; |
1291 | case 8: | |
d6f89d4b | 1292 | bitstream_fn = FPGA_FW_LA2016A; |
8b172e78 KG |
1293 | devc->max_samplerate = MAX_SAMPLE_RATE_LA2016; |
1294 | break; | |
1295 | case 9: | |
d6f89d4b | 1296 | bitstream_fn = FPGA_FW_LA1016A; |
8b172e78 | 1297 | devc->max_samplerate = MAX_SAMPLE_RATE_LA1016; |
9de389b1 KG |
1298 | break; |
1299 | default: | |
d6f89d4b GS |
1300 | bitstream_fn = NULL; |
1301 | break; | |
1302 | } | |
1303 | if (!bitstream_fn || !*bitstream_fn) { | |
91f73872 | 1304 | sr_err("Cannot identify as one of the supported models."); |
3f48ab02 FS |
1305 | return SR_ERR; |
1306 | } | |
f2cd2deb | 1307 | |
d6f89d4b GS |
1308 | if (check_fpga_bitstream(sdi) != SR_OK) { |
1309 | ret = upload_fpga_bitstream(sdi, bitstream_fn); | |
1310 | if (ret != SR_OK) { | |
1311 | sr_err("Cannot upload FPGA bitstream."); | |
1312 | return ret; | |
1313 | } | |
1314 | } | |
1315 | ret = enable_fpga_bitstream(sdi); | |
9de389b1 | 1316 | if (ret != SR_OK) { |
d6f89d4b | 1317 | sr_err("Cannot enable FPGA bitstream after upload."); |
9de389b1 KG |
1318 | return ret; |
1319 | } | |
1320 | ||
f2cd2deb | 1321 | state = run_state(sdi); |
9de389b1 | 1322 | if (state != 0x85e9) { |
91f73872 | 1323 | sr_warn("Unexpected run state, want 0x85e9, got 0x%04x.", state); |
9de389b1 | 1324 | } |
f2cd2deb | 1325 | |
00849545 | 1326 | if ((ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0)) != SR_OK) { |
91f73872 | 1327 | sr_err("Cannot reset USB bulk transfer."); |
f2cd2deb FS |
1328 | return ret; |
1329 | } | |
9de389b1 | 1330 | |
91f73872 | 1331 | sr_dbg("Device should be initialized."); |
f2cd2deb | 1332 | |
c34f4a89 GS |
1333 | ret = set_defaults(sdi); |
1334 | if (ret != SR_OK) | |
1335 | return ret; | |
1336 | ||
1337 | return SR_OK; | |
f2cd2deb FS |
1338 | } |
1339 | ||
1340 | SR_PRIV int la2016_deinit_device(const struct sr_dev_inst *sdi) | |
1341 | { | |
1342 | int ret; | |
1343 | ||
00849545 | 1344 | if ((ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x00, 0, NULL, 0)) != SR_OK) { |
91f73872 | 1345 | sr_err("Cannot deinitialize device's FPGA."); |
f2cd2deb FS |
1346 | return ret; |
1347 | } | |
1348 | ||
1349 | return SR_OK; | |
1350 | } |