]> sigrok.org Git - libsigrok.git/blame - src/hardware/kingst-la2016/protocol.c
projects / libsigrok.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
kingst-la2016: Upload firmware to correct USB configuration 1
[libsigrok.git] / src / hardware / kingst-la2016 / protocol.c
CommitLineData
f2cd2deb
FS		 1/*
2 * This file is part of the libsigrok project.
3 *
4 * Copyright (C) 2020 Florian Schmidt <schmidt_florian@gmx.de>
5 * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se>
6 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
7 * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk>
8 *
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation, either version 3 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#include <config.h>
24#include <stdint.h>
25#include <string.h>
26#include <glib.h>
27#include <glib/gstdio.h>
28#include <stdio.h>
29#include <errno.h>
30#include <math.h>
3f48ab02 31#include <inttypes.h>
f2cd2deb
FS		 32#include <libsigrok/libsigrok.h>
33#include "libsigrok-internal.h"
34#include "protocol.h"
35
36#define FPGA_FIRMWARE "kingst-la2016a-fpga.bitstream"
37#define UC_FIRMWARE "kingst-la-%04x.fw"
38
39#define MAX_SAMPLE_RATE SR_MHZ(200)
40#define MAX_SAMPLE_DEPTH 10e9
41#define MAX_PWM_FREQ SR_MHZ(20)
42#define PWM_CLOCK SR_MHZ(200)
43
44/* registers for control request 32: */
45#define CTRL_RUN 0x00
46#define CTRL_PWM_EN 0x02
47#define CTRL_BULK 0x10 /* can be read to get 12 byte sampling_info (III) */
48#define CTRL_SAMPLING 0x20
49#define CTRL_TRIGGER 0x30
50#define CTRL_THRESHOLD 0x48
51#define CTRL_PWM1 0x70
52#define CTRL_PWM2 0x78
53
54static int ctrl_in(const struct sr_dev_inst *sdi,
55 uint8_t bRequest, uint16_t wValue, uint16_t wIndex,
56 void *data, uint16_t wLength)
57{
58 struct sr_usb_dev_inst *usb;
59 int ret;
60
61 usb = sdi->conn;
62
63 if ((ret = libusb_control_transfer(
64 usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_IN,
65 bRequest, wValue, wIndex, (unsigned char *)data, wLength,
66 DEFAULT_TIMEOUT_MS)) != wLength) {
67 sr_err("failed to read %d bytes via ctrl-in %d %#x, %d: %s.",
68 wLength, bRequest, wValue, wIndex,
69 libusb_error_name(ret));
70 return SR_ERR;
71 }
72
73 return SR_OK;
74}
75
76static int ctrl_out(const struct sr_dev_inst *sdi,
77 uint8_t bRequest, uint16_t wValue, uint16_t wIndex,
78 void *data, uint16_t wLength)
79{
80 struct sr_usb_dev_inst *usb;
81 int ret;
82
83 usb = sdi->conn;
84
85 if ((ret = libusb_control_transfer(
86 usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT,
87 bRequest, wValue, wIndex, (unsigned char*)data, wLength,
88 DEFAULT_TIMEOUT_MS)) != wLength) {
89 sr_err("failed to write %d bytes via ctrl-out %d %#x, %d: %s.",
90 wLength, bRequest, wValue, wIndex,
91 libusb_error_name(ret));
92 return SR_ERR;
93 }
94
95 return SR_OK;
96}
97
98static int upload_fpga_bitstream(const struct sr_dev_inst *sdi)
99{
3f48ab02 100 struct dev_context *devc;
f2cd2deb
FS		 101 struct drv_context *drvc;
102 struct sr_usb_dev_inst *usb;
103 struct sr_resource bitstream;
104 uint32_t cmd;
105 uint8_t cmd_resp;
106 uint8_t block[4096];
3f48ab02
FS		 107 int len, act_len;
108 unsigned int pos;
f2cd2deb 109 int ret;
3f48ab02 110 unsigned int zero_pad_to = 0x2c000;
f2cd2deb 111
3f48ab02 112 devc = sdi->priv;
f2cd2deb
FS		 113 drvc = sdi->driver->context;
114 usb = sdi->conn;
115
116 sr_info("Uploading FPGA bitstream '%s'.", FPGA_FIRMWARE);
117
118 ret = sr_resource_open(drvc->sr_ctx, &bitstream, SR_RESOURCE_FIRMWARE, FPGA_FIRMWARE);
119 if (ret != SR_OK) {
120 sr_err("could not find la2016 firmware %s!", FPGA_FIRMWARE);
121 return ret;
122 }
123
3f48ab02
FS		 124 devc->bitstream_size = (uint32_t)bitstream.size;
125 WL32(&cmd, devc->bitstream_size);
f2cd2deb
FS		 126 if ((ret = ctrl_out(sdi, 80, 0x00, 0, &cmd, sizeof(cmd))) != SR_OK) {
127 sr_err("failed to give upload init command");
128 sr_resource_close(drvc->sr_ctx, &bitstream);
129 return ret;
130 }
131
132 pos = 0;
133 while (1) {
3f48ab02
FS		 134 if (pos < bitstream.size) {
135 len = (int)sr_resource_read(drvc->sr_ctx, &bitstream, &block, sizeof(block));
136 if (len < 0) {
137 sr_err("failed to read from fpga bitstream!");
138 sr_resource_close(drvc->sr_ctx, &bitstream);
139 return SR_ERR;
140 }
141 } else {
142 // fill with zero's until zero_pad_to
143 len = zero_pad_to - pos;
144 if ((unsigned)len > sizeof(block))
145 len = sizeof(block);
146 memset(&block, 0, len);
f2cd2deb
FS		 147 }
148 if (len == 0)
149 break;
150
151 ret = libusb_bulk_transfer(usb->devhdl, 2, (unsigned char*)&block[0], len, &act_len, DEFAULT_TIMEOUT_MS);
152 if (ret != 0) {
153 sr_dbg("failed to write fpga bitstream block at %#x len %d: %s.", pos, (int)len, libusb_error_name(ret));
154 ret = SR_ERR;
155 break;
156 }
157 if (act_len != len) {
158 sr_dbg("failed to write fpga bitstream block at %#x len %d: act_len is %d.", pos, (int)len, act_len);
159 ret = SR_ERR;
160 break;
161 }
162 pos += len;
163 }
164 sr_resource_close(drvc->sr_ctx, &bitstream);
165 if (ret != 0)
166 return ret;
3f48ab02 167 sr_info("FPGA bitstream upload (%" PRIu64 " bytes) done.", bitstream.size);
f2cd2deb
FS		 168
169 if ((ret = ctrl_in(sdi, 80, 0x00, 0, &cmd_resp, sizeof(cmd_resp))) != SR_OK) {
170 sr_err("failed to read response after FPGA bitstream upload");
171 return ret;
172 }
3f48ab02
FS		 173 if (cmd_resp != 0) {
174 sr_err("after fpga bitstream upload command response is 0x%02x, expect 0!", cmd_resp);
175 return SR_ERR;
176 }
177
178 g_usleep(30000);
f2cd2deb
FS		 179
180 if ((ret = ctrl_out(sdi, 16, 0x01, 0, NULL, 0)) != SR_OK) {
181 sr_err("failed enable fpga");
182 return ret;
183 }
184
3f48ab02 185 g_usleep(40000);
f2cd2deb
FS		 186 return SR_OK;
187}
188
189static int set_threshold_voltage(const struct sr_dev_inst *sdi, float voltage)
190{
191 struct dev_context *devc;
192 float o1, o2, v1, v2, f;
193 uint32_t cfg;
194 int ret;
195
196 devc = sdi->priv;
197 o1 = 15859969; v1 = 0.45;
198 o2 = 15860333; v2 = 1.65;
199 f = (o2 - o1) / (v2 - v1);
200 WL32(&cfg, (uint32_t)(o1 + (voltage - v1) * f));
201
202 sr_dbg("set threshold voltage %.2fV", voltage);
203 ret = ctrl_out(sdi, 32, CTRL_THRESHOLD, 0, &cfg, sizeof(cfg));
204 if (ret != SR_OK) {
205 sr_err("error setting new threshold voltage of %.2fV (%d)", voltage, RL16(&cfg));
206 return ret;
207 }
208 devc->threshold_voltage = voltage;
209
210 return SR_OK;
211}
212
213static int enable_pwm(const struct sr_dev_inst *sdi, uint8_t p1, uint8_t p2)
214{
215 struct dev_context *devc;
216 uint8_t cfg;
217 int ret;
218
219 devc = sdi->priv;
220 cfg = 0;
221
222 if (p1) cfg |= 1 << 0;
223 if (p2) cfg |= 1 << 1;
224
225 sr_dbg("set pwm enable %d %d", p1, p2);
226 ret = ctrl_out(sdi, 32, CTRL_PWM_EN, 0, &cfg, sizeof(cfg));
227 if (ret != SR_OK) {
228 sr_err("error setting new pwm enable 0x%02x", cfg);
229 return ret;
230 }
231 devc->pwm_setting[0].enabled = (p1) ? 1 : 0;
232 devc->pwm_setting[1].enabled = (p2) ? 1 : 0;
233
234 return SR_OK;
235}
236
237static int set_pwm(const struct sr_dev_inst *sdi, uint8_t which, float freq, float duty)
238{
239 int CTRL_PWM[] = { CTRL_PWM1, CTRL_PWM2 };
240 struct dev_context *devc;
241 pwm_setting_dev_t cfg;
242 pwm_setting_t *setting;
243 int ret;
244
245 devc = sdi->priv;
246
247 if (which < 1 || which > 2) {
248 sr_err("invalid pwm channel: %d", which);
249 return SR_ERR;
250 }
251 if (freq > MAX_PWM_FREQ) {
252 sr_err("pwm frequency too high: %.1f", freq);
253 return SR_ERR;
254 }
255 if (duty > 100 || duty < 0) {
256 sr_err("invalid pwm percentage: %f", duty);
257 return SR_ERR;
258 }
259
260 cfg.period = (uint32_t)(PWM_CLOCK / freq);
261 cfg.duty = (uint32_t)(0.5f + (cfg.period * duty / 100.));
262 sr_dbg("set pwm%d period %d, duty %d", which, cfg.period, cfg.duty);
263
264 pwm_setting_dev_le(cfg);
265 ret = ctrl_out(sdi, 32, CTRL_PWM[which - 1], 0, &cfg, sizeof(cfg));
266 if (ret != SR_OK) {
267 sr_err("error setting new pwm%d config %d %d", which, cfg.period, cfg.duty);
268 return ret;
269 }
270 setting = &devc->pwm_setting[which - 1];
271 setting->freq = freq;
272 setting->duty = duty;
273 setting->dev = cfg;
274
275 return SR_OK;
276}
277
278static int set_defaults(const struct sr_dev_inst *sdi)
279{
280 struct dev_context *devc;
281 int ret;
282
283 devc = sdi->priv;
284
285 devc->capture_ratio = 5; /* percent */
286 devc->cur_channels = 0xffff;
287 devc->limit_samples = 5000000;
288 devc->cur_samplerate = 200000000;
289
290 ret = set_threshold_voltage(sdi, devc->threshold_voltage);
291 if (ret)
292 return ret;
293
294 ret = enable_pwm(sdi, 0, 0);
295 if (ret)
296 return ret;
297
298 ret = set_pwm(sdi, 1, 1e3, 50);
299 if (ret)
300 return ret;
301
302 ret = set_pwm(sdi, 2, 100e3, 50);
303 if (ret)
304 return ret;
305
306 ret = enable_pwm(sdi, 1, 1);
307 if (ret)
308 return ret;
309
310 return SR_OK;
311}
312
313static int set_trigger_config(const struct sr_dev_inst *sdi)
314{
315 struct dev_context *devc;
316 struct sr_trigger *trigger;
317 trigger_cfg_t cfg;
318 GSList *stages;
319 GSList *channel;
320 struct sr_trigger_stage *stage1;
321 struct sr_trigger_match *match;
322 uint16_t ch_mask;
323 int ret;
324
325 devc = sdi->priv;
326 trigger = sr_session_trigger_get(sdi->session);
327
328 memset(&cfg, 0, sizeof(cfg));
329
330 cfg.channels = devc->cur_channels;
331
332 if (trigger && trigger->stages) {
333 stages = trigger->stages;
334 stage1 = stages->data;
335 if (stages->next) {
336 sr_err("Only one trigger stage supported for now.");
337 return SR_ERR;
338 }
339 channel = stage1->matches;
340 while (channel) {
341 match = channel->data;
342 ch_mask = 1 << match->channel->index;
343
344 switch (match->match) {
345 case SR_TRIGGER_ZERO:
346 cfg.level |= ch_mask;
347 cfg.high_or_falling &= ~ch_mask;
348 break;
349 case SR_TRIGGER_ONE:
350 cfg.level |= ch_mask;
351 cfg.high_or_falling |= ch_mask;
352 break;
353 case SR_TRIGGER_RISING:
354 if ((cfg.enabled & ~cfg.level)) {
355 sr_err("Only one trigger signal with falling-/rising-edge allowed.");
356 return SR_ERR;
357 }
358 cfg.level &= ~ch_mask;
359 cfg.high_or_falling &= ~ch_mask;
360 break;
361 case SR_TRIGGER_FALLING:
362 if ((cfg.enabled & ~cfg.level)) {
363 sr_err("Only one trigger signal with falling-/rising-edge allowed.");
364 return SR_ERR;
365 }
366 cfg.level &= ~ch_mask;
367 cfg.high_or_falling |= ch_mask;
368 break;
369 default:
370 sr_err("Unknown trigger value.");
371 return SR_ERR;
372 }
373 cfg.enabled |= ch_mask;
374 channel = channel->next;
375 }
376 }
377 sr_dbg("set trigger configuration channels: 0x%04x, "
378 "trigger-enabled 0x%04x, level-triggered 0x%04x, "
379 "high/falling 0x%04x", cfg.channels, cfg.enabled, cfg.level,
380 cfg.high_or_falling);
381
382 devc->had_triggers_configured = cfg.enabled != 0;
383
384 trigger_cfg_le(cfg);
385 ret = ctrl_out(sdi, 32, CTRL_TRIGGER, 16, &cfg, sizeof(cfg));
386 if (ret != SR_OK) {
387 sr_err("error setting trigger config!");
388 return ret;
389 }
390
391 return SR_OK;
392}
393
394static int set_sample_config(const struct sr_dev_inst *sdi)
395{
396 struct dev_context *devc;
397 sample_config_t cfg;
398 double clock_divisor;
399 uint64_t psa;
400 uint64_t total;
401 int ret;
402
403 devc = sdi->priv;
404 total = 128 * 1024 * 1024;
405
406 if (devc->cur_samplerate > MAX_SAMPLE_RATE) {
407 sr_err("too high sample rate: %" PRIu64, devc->cur_samplerate);
408 return SR_ERR;
409 }
410
411 clock_divisor = MAX_SAMPLE_RATE / (double)devc->cur_samplerate;
412 if (clock_divisor > 0xffff)
413 clock_divisor = 0xffff;
414 cfg.clock_divisor = (uint16_t)(clock_divisor + 0.5);
415 devc->cur_samplerate = MAX_SAMPLE_RATE / cfg.clock_divisor;
416
417 if (devc->limit_samples > MAX_SAMPLE_DEPTH) {
418 sr_err("too high sample depth: %" PRIu64, devc->limit_samples);
419 return SR_ERR;
420 }
421 cfg.sample_depth = devc->limit_samples;
422
423 devc->pre_trigger_size = (devc->capture_ratio * devc->limit_samples) / 100;
424
425 psa = devc->pre_trigger_size * 256;
426 cfg.psa = (uint32_t)(psa & 0xffffffff);
427 cfg.u1 = (uint16_t)((psa >> 32) & 0xffff);
428 cfg.u2 = (uint32_t)((total * devc->capture_ratio) / 100);
429
430 sr_dbg("set sampling configuration %.0fkHz, %d samples, trigger-pos %d%%",
431 devc->cur_samplerate/1e3, (unsigned int)cfg.sample_depth, (unsigned int)devc->capture_ratio);
432
433 sample_config_le(cfg);
434 ret = ctrl_out(sdi, 32, CTRL_SAMPLING, 0, &cfg, sizeof(cfg));
435 if (ret != SR_OK) {
436 sr_err("error setting sample config!");
437 return ret;
438 }
439
440 return SR_OK;
441}
442
443/**
444 * lowest 2 bit are probably:
445 * 2: recording
446 * 1: finished
447 * next 2 bit indicate whether we are still waiting for triggering
448 * 0: waiting
449 * 3: triggered
450 */
451static uint16_t run_state(const struct sr_dev_inst *sdi)
452{
453 uint16_t state;
454 int ret;
455
456 if ((ret = ctrl_in(sdi, 32, CTRL_RUN, 0, &state, sizeof(state))) != SR_OK) {
457 sr_err("failed to read run state!");
458 return ret;
459 }
460 sr_dbg("run_state: 0x%04x", state);
461
462 return state;
463}
464
465static int set_run_mode(const struct sr_dev_inst *sdi, uint8_t fast_blinking)
466{
467 int ret;
468
469 if ((ret = ctrl_out(sdi, 32, CTRL_RUN, 0, &fast_blinking, sizeof(fast_blinking))) != SR_OK) {
470 sr_err("failed to send set-run-mode command %d", fast_blinking);
471 return ret;
472 }
473
474 return SR_OK;
475}
476
477static int get_capture_info(const struct sr_dev_inst *sdi)
478{
479 struct dev_context *devc;
480 int ret;
481
482 devc = sdi->priv;
483
484 if ((ret = ctrl_in(sdi, 32, CTRL_BULK, 0, &devc->info, sizeof(devc->info))) != SR_OK) {
485 sr_err("failed to read capture info!");
486 return ret;
487 }
488 capture_info_host(devc->info);
489
490 sr_dbg("capture info: n_rep_packets: 0x%08x/%d, before_trigger: 0x%08x/%d, write_pos: 0x%08x%d",
491 devc->info.n_rep_packets, devc->info.n_rep_packets,
492 devc->info.n_rep_packets_before_trigger, devc->info.n_rep_packets_before_trigger,
493 devc->info.write_pos, devc->info.write_pos);
494
495 if (devc->info.n_rep_packets % 5)
496 sr_warn("number of packets is not as expected multiples of 5: %d", devc->info.n_rep_packets);
497
498 return SR_OK;
499}
500
501SR_PRIV int la2016_upload_firmware(struct sr_context *sr_ctx, libusb_device *dev, uint16_t product_id)
502{
503 char fw_file[1024];
504 snprintf(fw_file, sizeof(fw_file) - 1, UC_FIRMWARE, product_id);
40a0b2f4 505 return ezusb_upload_firmware(sr_ctx, dev, USB_CONFIGURATION, fw_file);
f2cd2deb
FS		 506}
507
508SR_PRIV int la2016_setup_acquisition(const struct sr_dev_inst *sdi)
509{
510 struct dev_context *devc;
511 int ret;
512 uint8_t cmd;
513
514 devc = sdi->priv;
515
516 ret = set_threshold_voltage(sdi, devc->threshold_voltage);
517 if (ret != SR_OK)
518 return ret;
519
520 cmd = 0;
521 if ((ret = ctrl_out(sdi, 32, 0x03, 0, &cmd, sizeof(cmd))) != SR_OK) {
522 sr_err("failed to send stop sampling command");
523 return ret;
524 }
525
526 ret = set_trigger_config(sdi);
527 if (ret != SR_OK)
528 return ret;
529
530 ret = set_sample_config(sdi);
531 if (ret != SR_OK)
532 return ret;
533
534 return SR_OK;
535}
536
537SR_PRIV int la2016_start_acquisition(const struct sr_dev_inst *sdi)
538{
539 return set_run_mode(sdi, 3);
540}
541
542SR_PRIV int la2016_stop_acquisition(const struct sr_dev_inst *sdi)
543{
544 return set_run_mode(sdi, 0);
545}
546
547SR_PRIV int la2016_abort_acquisition(const struct sr_dev_inst *sdi)
548{
549 return la2016_stop_acquisition(sdi);
550}
551
552SR_PRIV int la2016_has_triggered(const struct sr_dev_inst *sdi)
553{
554 uint16_t state;
555
556 state = run_state(sdi);
557
558 return (state & 0x3) == 1;
559}
560
561SR_PRIV int la2016_start_retrieval(const struct sr_dev_inst *sdi, libusb_transfer_cb_fn cb)
562{
563 struct dev_context *devc;
564 struct sr_usb_dev_inst *usb;
565 int ret;
566 uint32_t bulk_cfg[2];
567 uint32_t to_read;
568 uint8_t *buffer;
569
570 devc = sdi->priv;
571 usb = sdi->conn;
572
573 if ((ret = get_capture_info(sdi)) != SR_OK)
574 return ret;
575
576 devc->n_transfer_packets_to_read = devc->info.n_rep_packets / 5;
577 devc->n_bytes_to_read = devc->n_transfer_packets_to_read * sizeof(transfer_packet_t);
578 devc->read_pos = devc->info.write_pos - devc->n_bytes_to_read;
579 devc->n_reps_until_trigger = devc->info.n_rep_packets_before_trigger;
580
581 sr_dbg("want to read %d tfer-packets starting from pos %d",
582 devc->n_transfer_packets_to_read, devc->read_pos);
583
584 if ((ret = ctrl_out(sdi, 56, 0x00, 0, NULL, 0)) != SR_OK) {
585 sr_err("failed to reset bulk state");
586 return ret;
587 }
588 WL32(&bulk_cfg[0], devc->read_pos);
589 WL32(&bulk_cfg[1], devc->n_bytes_to_read);
590 sr_dbg("will read from 0x%08x, 0x%08x bytes", devc->read_pos, devc->n_bytes_to_read);
591 if ((ret = ctrl_out(sdi, 32, CTRL_BULK, 0, &bulk_cfg, sizeof(bulk_cfg))) != SR_OK) {
592 sr_err("failed to send bulk config");
593 return ret;
594 }
595 if ((ret = ctrl_out(sdi, 48, 0x00, 0, NULL, 0)) != SR_OK) {
596 sr_err("failed to unblock bulk transfers");
597 return ret;
598 }
599
600 to_read = devc->n_bytes_to_read;
601 if (to_read > LA2016_BULK_MAX)
602 to_read = LA2016_BULK_MAX;
603
604 buffer = g_try_malloc(to_read);
605 if (!buffer) {
606 sr_err("Failed to allocate %d bytes for bulk transfer", to_read);
607 return SR_ERR_MALLOC;
608 }
609
610 devc->transfer = libusb_alloc_transfer(0);
611 libusb_fill_bulk_transfer(
612 devc->transfer, usb->devhdl,
613 0x86, buffer, to_read,
614 cb, (void *)sdi, DEFAULT_TIMEOUT_MS);
615
616 if ((ret = libusb_submit_transfer(devc->transfer)) != 0) {
617 sr_err("Failed to submit transfer: %s.", libusb_error_name(ret));
618 libusb_free_transfer(devc->transfer);
619 devc->transfer = NULL;
620 g_free(buffer);
621 return SR_ERR;
622 }
623
624 return SR_OK;
625}
626
627SR_PRIV int la2016_init_device(const struct sr_dev_inst *sdi)
628{
3f48ab02 629 struct dev_context *devc;
f2cd2deb
FS		 630 int ret;
631 uint32_t i1;
632 uint32_t i2[2];
633 uint16_t state;
634
3f48ab02
FS		 635 /* this unknown_cmd1 seems to depend on the FPGA bitstream */
636 uint8_t unknown_cmd1_340[] = { 0xa3, 0x09, 0xc9, 0x8d, 0xe7, 0xad, 0x7a, 0x62, 0xb6, 0xd1, 0xbf };
637 uint8_t unknown_cmd1_342[] = { 0xa3, 0x09, 0xc9, 0xf4, 0x32, 0x4c, 0x4d, 0xee, 0xab, 0xa0, 0xdd };
638 uint8_t expected_unknown_resp1_340[] = { 0xa3, 0x10, 0xda, 0x66, 0x6b, 0x93, 0x5c, 0x55, 0x38, 0x50, 0x39, 0x51, 0x98, 0x86, 0x5d, 0x06, 0x7c, 0xea };
639 uint8_t expected_unknown_resp1_342[] = { 0xa3, 0x10, 0xb3, 0x92, 0x7b, 0xd8, 0x6b, 0xca, 0xa5, 0xab, 0x42, 0x6e, 0xda, 0xcd, 0x9d, 0xf1, 0x31, 0x2f };
640 uint8_t unknown_resp1[sizeof(expected_unknown_resp1_340)];
641 uint8_t *expected_unknown_resp1;
642 uint8_t *unknown_cmd1;
f2cd2deb
FS		 643
644 uint8_t unknown_cmd2[] = { 0xa3, 0x01, 0xca };
645 uint8_t expected_unknown_resp2[] = { 0xa3, 0x08, 0x06, 0x83, 0x96, 0x29, 0x15, 0xe1, 0x92, 0x74, 0x00, 0x00 };
646 uint8_t unknown_resp2[sizeof(expected_unknown_resp2)];
647
3f48ab02
FS		 648 devc = sdi->priv;
649
f2cd2deb
FS		 650 if ((ret = ctrl_in(sdi, 162, 0x20, 0, &i1, sizeof(i1))) != SR_OK) {
651 sr_err("failed to read i1");
652 return ret;
653 }
654 sr_dbg("i1: 0x%08x", i1);
655
656 if ((ret = ctrl_in(sdi, 162, 0x08, 0, &i2, sizeof(i2))) != SR_OK) {
657 sr_err("failed to read i2");
658 return ret;
659 }
660 sr_dbg("i2: 0x%08x, 0x%08x", i2[0], i2[1]);
661
662 if ((ret = upload_fpga_bitstream(sdi)) != SR_OK) {
663 sr_err("failed to upload fpga bitstream");
664 return ret;
665 }
666
3f48ab02
FS		 667 if (run_state(sdi) == 0xffff) {
668 sr_err("run_state after fpga bitstream upload is 0xffff!");
669 return SR_ERR;
670 }
f2cd2deb 671
3f48ab02
FS		 672 if (devc->bitstream_size == 0x2b602) {
673 // v3.4.0
674 unknown_cmd1 = unknown_cmd1_340;
675 expected_unknown_resp1 = expected_unknown_resp1_340;
676 } else {
677 // v3.4.2
678 if (devc->bitstream_size != 0x2b839)
679 sr_warn("the FPGA bitstream size %d is unknown. tested bistreams from vendor's version 3.4.0 and 3.4.2\n", devc->bitstream_size);
680 unknown_cmd1 = unknown_cmd1_342;
681 expected_unknown_resp1 = expected_unknown_resp1_342;
682 }
683 if ((ret = ctrl_out(sdi, 96, 0x00, 0, unknown_cmd1, sizeof(unknown_cmd1_340))) != SR_OK) {
f2cd2deb
FS		 684 sr_err("failed to send unknown_cmd1");
685 return ret;
686 }
687 g_usleep(80 * 1000);
688 if ((ret = ctrl_in(sdi, 96, 0x00, 0, unknown_resp1, sizeof(unknown_resp1))) != SR_OK) {
689 sr_err("failed to read unknown_resp1");
690 return ret;
691 }
692 if (memcmp(unknown_resp1, expected_unknown_resp1, sizeof(unknown_resp1)))
3f48ab02 693 sr_dbg("unknown_cmd1 response is not as expected, this is to be expected...");
f2cd2deb
FS		 694
695 state = run_state(sdi);
696 if (state != 0x85e9)
697 sr_warn("expect run state to be 0x85e9, but it reads 0x%04x", state);
698
699 if ((ret = ctrl_out(sdi, 96, 0x00, 0, unknown_cmd2, sizeof(unknown_cmd2))) != SR_OK) {
700 sr_err("failed to send unknown_cmd2");
701 return ret;
702 }
703 g_usleep(80 * 1000);
704 if ((ret = ctrl_in(sdi, 96, 0x00, 0, unknown_resp2, sizeof(unknown_resp2))) != SR_OK) {
705 sr_err("failed to read unknown_resp2");
706 return ret;
707 }
708 if (memcmp(unknown_resp2, expected_unknown_resp2, sizeof(unknown_resp2)))
709 sr_dbg("unknown_cmd2 response is not as expected!");
710
711 if ((ret = ctrl_out(sdi, 56, 0x00, 0, NULL, 0)) != SR_OK) {
712 sr_err("failed to send unknown_cmd3");
713 return ret;
714 }
715 sr_dbg("device should be initialized");
716
717 return set_defaults(sdi);
718}
719
720SR_PRIV int la2016_deinit_device(const struct sr_dev_inst *sdi)
721{
722 int ret;
723
724 if ((ret = ctrl_out(sdi, 16, 0x00, 0, NULL, 0)) != SR_OK) {
725 sr_err("failed to send deinit command");
726 return ret;
727 }
728
729 return SR_OK;
730}
Hardware access and backend lib