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[libsigrok.git] / src / hardware / atten-pps3xxx / api.c
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1/*
2 * This file is part of the libsigrok project.
3 *
4 * Copyright (C) 2014 Bert Vermeulen <bert@biot.com>
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
6ec6c43b 20#include <config.h>
33c40990 21#include <string.h>
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22#include "protocol.h"
23
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24/*
25 * The default serial communication settings on the device are 9600
26 * baud, 9 data bits. The 9th bit isn't actually used, and the vendor
27 * software uses Mark parity to absorb the extra bit.
28 *
29 * Since 9 data bits is not a standard available in POSIX, we use two
30 * stop bits to skip over the extra bit instead.
31 */
32#define SERIALCOMM "9600/8n2"
33
584560f1 34static const uint32_t scanopts[] = {
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35 SR_CONF_CONN,
36 SR_CONF_SERIALCOMM,
37};
38
1f889afd 39static const uint32_t drvopts[] = {
33c40990 40 SR_CONF_POWER_SUPPLY,
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BV
41};
42
1f889afd 43static const uint32_t devopts[] = {
e91bb0a6 44 SR_CONF_CONTINUOUS,
7a0b98b5 45 SR_CONF_CHANNEL_CONFIG | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
5827f61b 46 SR_CONF_OVER_CURRENT_PROTECTION_ENABLED | SR_CONF_GET | SR_CONF_SET,
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47};
48
584560f1 49static const uint32_t devopts_cg[] = {
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AJ
50 SR_CONF_VOLTAGE | SR_CONF_GET,
51 SR_CONF_VOLTAGE_TARGET | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
52 SR_CONF_CURRENT | SR_CONF_GET,
53 SR_CONF_CURRENT_LIMIT | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
54 SR_CONF_ENABLED | SR_CONF_GET | SR_CONF_SET,
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55};
56
57static const char *channel_modes[] = {
58 "Independent",
59 "Series",
60 "Parallel",
61};
62
329733d9 63static const struct pps_model models[] = {
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64 { PPS_3203T_3S, "PPS3203T-3S",
65 CHANMODE_INDEPENDENT | CHANMODE_SERIES | CHANMODE_PARALLEL,
66 3,
67 {
68 /* Channel 1 */
69 { { 0, 32, 0.01 }, { 0, 3, 0.001 } },
70 /* Channel 2 */
71 { { 0, 32, 0.01 }, { 0, 3, 0.001 } },
72 /* Channel 3 */
73 { { 0, 6, 0.01 }, { 0, 3, 0.001 } },
74 },
75 },
76};
77
4f840ce9 78static GSList *scan(struct sr_dev_driver *di, GSList *options, int modelid)
fa0d6afe 79{
33c40990 80 struct sr_dev_inst *sdi;
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81 struct dev_context *devc;
82 struct sr_config *src;
ba7dd8bb 83 struct sr_channel *ch;
40fd0264 84 struct sr_channel_group *cg;
33c40990 85 struct sr_serial_dev_inst *serial;
43376f33 86 GSList *l;
329733d9 87 const struct pps_model *model;
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88 uint8_t packet[PACKET_SIZE];
89 unsigned int i;
2eb1612d 90 int delay_ms, ret;
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91 const char *conn, *serialcomm;
92 char channel[10];
fa0d6afe 93
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94 conn = serialcomm = NULL;
95 for (l = options; l; l = l->next) {
96 src = l->data;
97 switch (src->key) {
98 case SR_CONF_CONN:
99 conn = g_variant_get_string(src->data, NULL);
100 break;
101 case SR_CONF_SERIALCOMM:
102 serialcomm = g_variant_get_string(src->data, NULL);
103 break;
104 }
105 }
106 if (!conn)
107 return NULL;
108 if (!serialcomm)
109 serialcomm = SERIALCOMM;
110
91219afc 111 serial = sr_serial_dev_inst_new(conn, serialcomm);
33c40990 112
5305266a 113 if (serial_open(serial, SERIAL_RDWR) != SR_OK)
33c40990 114 return NULL;
91219afc 115
945cfd4f 116 /* This is how the vendor software scans for hardware. */
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117 memset(packet, 0, PACKET_SIZE);
118 packet[0] = 0xaa;
119 packet[1] = 0xaa;
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120 delay_ms = serial_timeout(serial, PACKET_SIZE);
121 if (serial_write_blocking(serial, packet, PACKET_SIZE, delay_ms) < PACKET_SIZE) {
081c214e 122 sr_err("Unable to write while probing for hardware.");
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123 return NULL;
124 }
125 /* The device responds with a 24-byte packet when it receives a packet.
126 * At 9600 baud, 300ms is long enough for it to have arrived. */
127 g_usleep(300 * 1000);
128 memset(packet, 0, PACKET_SIZE);
129 if ((ret = serial_read_nonblocking(serial, packet, PACKET_SIZE)) < 0) {
130 sr_err("Unable to read while probing for hardware: %s",
8d522801 131 sr_strerror(ret));
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132 return NULL;
133 }
134 if (ret != PACKET_SIZE || packet[0] != 0xaa || packet[1] != 0xaa) {
135 /* Doesn't look like an Atten PPS. */
136 return NULL;
137 }
138
139 model = NULL;
140 for (i = 0; i < ARRAY_SIZE(models); i++) {
141 if (models[i].modelid == modelid) {
142 model = &models[i];
143 break;
144 }
145 }
146 if (!model) {
147 sr_err("Unknown modelid %d", modelid);
148 return NULL;
149 }
150
aac29cc1 151 sdi = g_malloc0(sizeof(struct sr_dev_inst));
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152 sdi->status = SR_ST_INACTIVE;
153 sdi->vendor = g_strdup("Atten");
154 sdi->model = g_strdup(model->name);
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155 sdi->inst_type = SR_INST_SERIAL;
156 sdi->conn = serial;
157 for (i = 0; i < MAX_CHANNELS; i++) {
158 snprintf(channel, 10, "CH%d", i + 1);
5e23fcab 159 ch = sr_channel_new(sdi, i, SR_CHANNEL_ANALOG, TRUE, channel);
d810901a 160 cg = sr_channel_group_new(sdi, channel, NULL);
ba7dd8bb 161 cg->channels = g_slist_append(NULL, ch);
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162 }
163
164 devc = g_malloc0(sizeof(struct dev_context));
165 devc->model = model;
166 devc->config = g_malloc0(sizeof(struct per_channel_config) * model->num_channels);
2eb1612d 167 devc->delay_ms = delay_ms;
33c40990 168 sdi->priv = devc;
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169
170 serial_close(serial);
fa0d6afe 171
43376f33 172 return std_scan_complete(di, g_slist_append(NULL, sdi));
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173}
174
4f840ce9 175static GSList *scan_3203(struct sr_dev_driver *di, GSList *options)
33c40990 176{
4f840ce9 177 return scan(di, options, PPS_3203T_3S);
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178}
179
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180static int config_get(uint32_t key, GVariant **data,
181 const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
fa0d6afe 182{
33c40990 183 struct dev_context *devc;
ba7dd8bb 184 struct sr_channel *ch;
a9010323 185 int channel;
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186
187 if (!sdi)
188 return SR_ERR_ARG;
fa0d6afe 189
33c40990 190 devc = sdi->priv;
fa0d6afe 191
53b4680f 192 if (!cg) {
33c40990 193 switch (key) {
7a0b98b5 194 case SR_CONF_CHANNEL_CONFIG:
fe997353 195 *data = g_variant_new_string(channel_modes[devc->channel_mode]);
33c40990 196 break;
a1eaa9e0 197 case SR_CONF_OVER_CURRENT_PROTECTION_ENABLED:
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198 *data = g_variant_new_boolean(devc->over_current_protection);
199 break;
200 default:
201 return SR_ERR_NA;
202 }
203 } else {
660e398f 204 /* We only ever have one channel per channel group in this driver. */
ba7dd8bb
UH
205 ch = cg->channels->data;
206 channel = ch->index;
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207
208 switch (key) {
7a0b98b5 209 case SR_CONF_VOLTAGE:
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210 *data = g_variant_new_double(devc->config[channel].output_voltage_last);
211 break;
7a0b98b5 212 case SR_CONF_VOLTAGE_TARGET:
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213 *data = g_variant_new_double(devc->config[channel].output_voltage_max);
214 break;
7a0b98b5 215 case SR_CONF_CURRENT:
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216 *data = g_variant_new_double(devc->config[channel].output_current_last);
217 break;
7a0b98b5 218 case SR_CONF_CURRENT_LIMIT:
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219 *data = g_variant_new_double(devc->config[channel].output_current_max);
220 break;
7a0b98b5 221 case SR_CONF_ENABLED:
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222 *data = g_variant_new_boolean(devc->config[channel].output_enabled);
223 break;
224 default:
225 return SR_ERR_NA;
226 }
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227 }
228
a9010323 229 return SR_OK;
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230}
231
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232static int config_set(uint32_t key, GVariant *data,
233 const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
fa0d6afe 234{
33c40990 235 struct dev_context *devc;
ba7dd8bb 236 struct sr_channel *ch;
33c40990 237 gdouble dval;
758906aa 238 int channel, ival;
33c40990 239 gboolean bval;
fa0d6afe 240
33c40990 241 devc = sdi->priv;
758906aa 242
53b4680f 243 if (!cg) {
33c40990 244 switch (key) {
7a0b98b5 245 case SR_CONF_CHANNEL_CONFIG:
697fb6dd
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246 if ((ival = std_str_idx(data, ARRAY_AND_SIZE(channel_modes))) < 0)
247 return SR_ERR_ARG;
758906aa
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248 if (devc->model->channel_modes && (1 << ival) == 0)
249 return SR_ERR_ARG; /* Not supported on this model. */
33c40990 250 if (ival == devc->channel_mode_set)
758906aa 251 break; /* Nothing to do. */
33c40990 252 devc->channel_mode_set = ival;
ab988ecb 253 devc->config_dirty = TRUE;
33c40990 254 break;
a1eaa9e0 255 case SR_CONF_OVER_CURRENT_PROTECTION_ENABLED:
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256 bval = g_variant_get_boolean(data);
257 if (bval == devc->over_current_protection_set)
758906aa 258 break; /* Nothing to do. */
33c40990 259 devc->over_current_protection_set = bval;
ab988ecb 260 devc->config_dirty = TRUE;
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261 break;
262 default:
263 return SR_ERR_NA;
264 }
265 } else {
660e398f 266 /* We only ever have one channel per channel group in this driver. */
ba7dd8bb
UH
267 ch = cg->channels->data;
268 channel = ch->index;
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269
270 switch (key) {
7a0b98b5 271 case SR_CONF_VOLTAGE_TARGET:
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272 dval = g_variant_get_double(data);
273 if (dval < 0 || dval > devc->model->channels[channel].voltage[1])
758906aa 274 return SR_ERR_ARG;
33c40990 275 devc->config[channel].output_voltage_max = dval;
ab988ecb 276 devc->config_dirty = TRUE;
33c40990 277 break;
7a0b98b5 278 case SR_CONF_CURRENT_LIMIT:
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279 dval = g_variant_get_double(data);
280 if (dval < 0 || dval > devc->model->channels[channel].current[1])
758906aa 281 return SR_ERR_ARG;
33c40990 282 devc->config[channel].output_current_max = dval;
ab988ecb 283 devc->config_dirty = TRUE;
33c40990 284 break;
7a0b98b5 285 case SR_CONF_ENABLED:
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286 bval = g_variant_get_boolean(data);
287 if (bval == devc->config[channel].output_enabled_set)
758906aa 288 break; /* Nothing to do. */
33c40990 289 devc->config[channel].output_enabled_set = bval;
ab988ecb 290 devc->config_dirty = TRUE;
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291 break;
292 default:
758906aa 293 return SR_ERR_NA;
33c40990 294 }
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295 }
296
758906aa 297 return SR_OK;
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298}
299
dd7a72ea
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300static int config_list(uint32_t key, GVariant **data,
301 const struct sr_dev_inst *sdi, const struct sr_channel_group *cg)
fa0d6afe 302{
33c40990 303 struct dev_context *devc;
ba7dd8bb 304 struct sr_channel *ch;
54d471f4 305 int channel;
33c40990 306
e66d1892 307 devc = (sdi) ? sdi->priv : NULL;
a9010323 308
53b4680f 309 if (!cg) {
33c40990 310 switch (key) {
e66d1892 311 case SR_CONF_SCAN_OPTIONS:
33c40990 312 case SR_CONF_DEVICE_OPTIONS:
e66d1892 313 return STD_CONFIG_LIST(key, data, sdi, cg, scanopts, drvopts, devopts);
7a0b98b5 314 case SR_CONF_CHANNEL_CONFIG:
f6c685e4
GS
315 if (!devc || !devc->model)
316 return SR_ERR_ARG;
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317 if (devc->model->channel_modes == CHANMODE_INDEPENDENT) {
318 /* The 1-channel models. */
319 *data = g_variant_new_strv(channel_modes, 1);
320 } else {
321 /* The other models support all modes. */
53012da6 322 *data = g_variant_new_strv(ARRAY_AND_SIZE(channel_modes));
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323 }
324 break;
325 default:
326 return SR_ERR_NA;
327 }
328 } else {
660e398f 329 /* We only ever have one channel per channel group in this driver. */
ba7dd8bb
UH
330 ch = cg->channels->data;
331 channel = ch->index;
33c40990
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332
333 switch (key) {
334 case SR_CONF_DEVICE_OPTIONS:
53012da6 335 *data = std_gvar_array_u32(ARRAY_AND_SIZE(devopts_cg));
33c40990 336 break;
7a0b98b5 337 case SR_CONF_VOLTAGE_TARGET:
f6c685e4
GS
338 if (!devc || !devc->model)
339 return SR_ERR_ARG;
54d471f4 340 *data = std_gvar_min_max_step_array(devc->model->channels[channel].voltage);
33c40990 341 break;
7a0b98b5 342 case SR_CONF_CURRENT_LIMIT:
f6c685e4
GS
343 if (!devc || !devc->model)
344 return SR_ERR_ARG;
54d471f4 345 *data = std_gvar_min_max_step_array(devc->model->channels[channel].current);
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346 break;
347 default:
348 return SR_ERR_NA;
349 }
fa0d6afe
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350 }
351
a9010323 352 return SR_OK;
fa0d6afe
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353}
354
ab988ecb
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355static int dev_close(struct sr_dev_inst *sdi)
356{
357 struct dev_context *devc;
358
359 devc = sdi->priv;
f1ba6b4b 360
ab988ecb
BV
361 if (devc->config_dirty)
362 /* Some configuration changes were queued up but didn't
363 * get sent to the device, likely because we were never
364 * in acquisition mode. Send them out now. */
365 send_config(sdi);
366
367 return std_serial_dev_close(sdi);
368}
369
695dc859 370static int dev_acquisition_start(const struct sr_dev_inst *sdi)
fa0d6afe 371{
33c40990
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372 struct dev_context *devc;
373 struct sr_serial_dev_inst *serial;
374 uint8_t packet[PACKET_SIZE];
375
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376 devc = sdi->priv;
377 memset(devc->packet, 0x44, PACKET_SIZE);
378 devc->packet_size = 0;
379
380 devc->acquisition_running = TRUE;
381
382 serial = sdi->conn;
102f1239
BV
383 serial_source_add(sdi->session, serial, G_IO_IN, 50,
384 atten_pps3xxx_receive_data, (void *)sdi);
bee2b016 385 std_session_send_df_header(sdi);
33c40990 386
ba7dd8bb 387 /* Send a "channel" configuration packet now. */
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388 memset(packet, 0, PACKET_SIZE);
389 packet[0] = 0xaa;
390 packet[1] = 0xaa;
391 send_packet(sdi, packet);
fa0d6afe
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392
393 return SR_OK;
394}
395
695dc859 396static int dev_acquisition_stop(struct sr_dev_inst *sdi)
fa0d6afe 397{
33c40990
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398 struct dev_context *devc;
399
33c40990
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400 devc = sdi->priv;
401 devc->acquisition_running = FALSE;
fa0d6afe
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402
403 return SR_OK;
404}
405
dd5c48a6 406static struct sr_dev_driver atten_pps3203_driver_info = {
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407 .name = "atten-pps3203",
408 .longname = "Atten PPS3203T-3S",
fa0d6afe 409 .api_version = 1,
c2fdcc25 410 .init = std_init,
700d6b64 411 .cleanup = std_cleanup,
33c40990 412 .scan = scan_3203,
c01bf34c 413 .dev_list = std_dev_list,
f778bf02 414 .dev_clear = std_dev_clear,
fa0d6afe
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415 .config_get = config_get,
416 .config_set = config_set,
417 .config_list = config_list,
33c40990 418 .dev_open = std_serial_dev_open,
ab988ecb 419 .dev_close = dev_close,
fa0d6afe
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420 .dev_acquisition_start = dev_acquisition_start,
421 .dev_acquisition_stop = dev_acquisition_stop,
41812aca 422 .context = NULL,
fa0d6afe 423};
dd5c48a6 424SR_REGISTER_DEV_DRIVER(atten_pps3203_driver_info);