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sr: remove obsolete SR_DI_INST
[libsigrok.git] / hardware / openbench-logic-sniffer / ols.c
CommitLineData
a1bb33af
UH
1/*
2 * This file is part of the sigrok project.
3 *
c73d2ea4 4 * Copyright (C) 2010-2012 Bert Vermeulen <bert@biot.com>
a1bb33af
UH
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include <stdio.h>
21#include <stdint.h>
22#include <stdlib.h>
23#include <sys/types.h>
24#include <sys/stat.h>
25#include <fcntl.h>
26#include <unistd.h>
a9f54bcd
UH
27#ifdef _WIN32
28#include <windows.h>
29#else
a1bb33af 30#include <termios.h>
926b866c 31#endif
a1bb33af
UH
32#include <string.h>
33#include <sys/time.h>
34#include <inttypes.h>
926b866c
UH
35#ifdef _WIN32
36/* TODO */
37#else
6937bb75 38#include <arpa/inet.h>
926b866c 39#endif
a1bb33af 40#include <glib.h>
45c59c8b
BV
41#include "libsigrok.h"
42#include "libsigrok-internal.h"
4fe9a6da 43#include "ols.h"
a1bb33af 44
1fdb75e1
UH
45#ifdef _WIN32
46#define O_NONBLOCK FIONBIO
47#endif
48
915f7cc8 49static const int hwcaps[] = {
5a2326a7
UH
50 SR_HWCAP_LOGIC_ANALYZER,
51 SR_HWCAP_SAMPLERATE,
52 SR_HWCAP_CAPTURE_RATIO,
53 SR_HWCAP_LIMIT_SAMPLES,
3a4d09c0 54 SR_HWCAP_RLE,
43fc7885 55 0,
a1bb33af
UH
56};
57
d261dbbf 58/* Probes are numbered 0-31 (on the PCB silkscreen). */
c37d2b1b 59static const char *probe_names[NUM_PROBES + 1] = {
464d12c7
KS
60 "0",
61 "1",
62 "2",
63 "3",
64 "4",
65 "5",
66 "6",
67 "7",
68 "8",
69 "9",
70 "10",
71 "11",
72 "12",
73 "13",
74 "14",
75 "15",
76 "16",
77 "17",
78 "18",
79 "19",
80 "20",
81 "21",
82 "22",
83 "23",
84 "24",
85 "25",
86 "26",
87 "27",
88 "28",
89 "29",
90 "30",
91 "31",
92 NULL,
93};
94
4fe9a6da 95/* default supported samplerates, can be overridden by device metadata */
a533743d 96static const struct sr_samplerates samplerates = {
c9140419 97 SR_HZ(10),
59df0c77 98 SR_MHZ(200),
c9140419
UH
99 SR_HZ(1),
100 NULL,
a1bb33af
UH
101};
102
e5e81856
BV
103SR_PRIV struct sr_dev_driver ols_driver_info;
104static struct sr_dev_driver *odi = &ols_driver_info;
a1bb33af 105
6937bb75 106static int send_shortcommand(int fd, uint8_t command)
a1bb33af
UH
107{
108 char buf[1];
109
b08024a8 110 sr_dbg("ols: sending cmd 0x%.2x", command);
a1bb33af 111 buf[0] = command;
2119ab03 112 if (serial_write(fd, buf, 1) != 1)
e46b8fb1 113 return SR_ERR;
a1bb33af 114
e46b8fb1 115 return SR_OK;
a1bb33af
UH
116}
117
6937bb75 118static int send_longcommand(int fd, uint8_t command, uint32_t data)
a1bb33af
UH
119{
120 char buf[5];
121
b08024a8 122 sr_dbg("ols: sending cmd 0x%.2x data 0x%.8x", command, data);
a1bb33af 123 buf[0] = command;
6937bb75
BV
124 buf[1] = (data & 0xff000000) >> 24;
125 buf[2] = (data & 0xff0000) >> 16;
126 buf[3] = (data & 0xff00) >> 8;
127 buf[4] = data & 0xff;
2119ab03 128 if (serial_write(fd, buf, 5) != 5)
e46b8fb1 129 return SR_ERR;
a1bb33af 130
e46b8fb1 131 return SR_OK;
a1bb33af
UH
132}
133
1b79df2f 134static int configure_probes(struct context *ctx, const GSList *probes)
a1bb33af 135{
1b79df2f
JH
136 const struct sr_probe *probe;
137 const GSList *l;
6937bb75 138 int probe_bit, stage, i;
a1bb33af
UH
139 char *tc;
140
ea9cfed7 141 ctx->probe_mask = 0;
43fc7885 142 for (i = 0; i < NUM_TRIGGER_STAGES; i++) {
ea9cfed7
UH
143 ctx->trigger_mask[i] = 0;
144 ctx->trigger_value[i] = 0;
a1bb33af
UH
145 }
146
ea9cfed7 147 ctx->num_stages = 0;
43fc7885 148 for (l = probes; l; l = l->next) {
1b79df2f 149 probe = (const struct sr_probe *)l->data;
43fc7885 150 if (!probe->enabled)
6937bb75
BV
151 continue;
152
43fc7885
UH
153 /*
154 * Set up the probe mask for later configuration into the
155 * flag register.
156 */
b35c8293 157 probe_bit = 1 << (probe->index);
ea9cfed7 158 ctx->probe_mask |= probe_bit;
6937bb75 159
a803c0db 160 if (!probe->trigger)
6937bb75
BV
161 continue;
162
43fc7885 163 /* Configure trigger mask and value. */
6937bb75 164 stage = 0;
43fc7885 165 for (tc = probe->trigger; tc && *tc; tc++) {
ea9cfed7 166 ctx->trigger_mask[stage] |= probe_bit;
43fc7885 167 if (*tc == '1')
ea9cfed7 168 ctx->trigger_value[stage] |= probe_bit;
6937bb75 169 stage++;
43fc7885
UH
170 if (stage > 3)
171 /*
172 * TODO: Only supporting parallel mode, with
173 * up to 4 stages.
174 */
e46b8fb1 175 return SR_ERR;
a1bb33af 176 }
ea9cfed7
UH
177 if (stage > ctx->num_stages)
178 ctx->num_stages = stage;
a1bb33af
UH
179 }
180
e46b8fb1 181 return SR_OK;
a1bb33af
UH
182}
183
a803c0db 184static uint32_t reverse16(uint32_t in)
6937bb75
BV
185{
186 uint32_t out;
187
a803c0db
BV
188 out = (in & 0xff) << 8;
189 out |= (in & 0xff00) >> 8;
190 out |= (in & 0xff0000) << 8;
191 out |= (in & 0xff000000) >> 8;
192
193 return out;
194}
195
196static uint32_t reverse32(uint32_t in)
197{
198 uint32_t out;
199
200 out = (in & 0xff) << 24;
201 out |= (in & 0xff00) << 8;
202 out |= (in & 0xff0000) >> 8;
203 out |= (in & 0xff000000) >> 24;
204
205 return out;
6937bb75
BV
206}
207
ea9cfed7 208static struct context *ols_dev_new(void)
4fe9a6da 209{
ea9cfed7 210 struct context *ctx;
4fe9a6da 211
ea9cfed7
UH
212 /* TODO: Is 'ctx' ever g_free()'d? */
213 if (!(ctx = g_try_malloc0(sizeof(struct context)))) {
214 sr_err("ols: %s: ctx malloc failed", __func__);
b53738ba
UH
215 return NULL;
216 }
217
ea9cfed7
UH
218 ctx->trigger_at = -1;
219 ctx->probe_mask = 0xffffffff;
220 ctx->cur_samplerate = SR_KHZ(200);
221 ctx->serial = NULL;
4fe9a6da 222
ea9cfed7 223 return ctx;
4fe9a6da
BV
224}
225
d68e2d1a 226static struct sr_dev_inst *get_metadata(int fd)
4fe9a6da 227{
d68e2d1a 228 struct sr_dev_inst *sdi;
ea9cfed7 229 struct context *ctx;
10e5cbed
BV
230 struct sr_probe *probe;
231 uint32_t tmp_int, ui;
4fe9a6da 232 uint8_t key, type, token;
bb7ef793 233 GString *tmp_str, *devname, *version;
10e5cbed 234 guchar tmp_c;
4fe9a6da 235
d3683c42 236 sdi = sr_dev_inst_new(0, SR_ST_INACTIVE, NULL, NULL, NULL);
2efc5948 237 sdi->driver = odi;
ea9cfed7
UH
238 ctx = ols_dev_new();
239 sdi->priv = ctx;
4fe9a6da 240
bb7ef793 241 devname = g_string_new("");
4fe9a6da
BV
242 version = g_string_new("");
243
244 key = 0xff;
245 while (key) {
246 if (serial_read(fd, &key, 1) != 1 || key == 0x00)
247 break;
248 type = key >> 5;
249 token = key & 0x1f;
250 switch (type) {
251 case 0:
252 /* NULL-terminated string */
253 tmp_str = g_string_new("");
254 while (serial_read(fd, &tmp_c, 1) == 1 && tmp_c != '\0')
255 g_string_append_c(tmp_str, tmp_c);
b08024a8
UH
256 sr_dbg("ols: got metadata key 0x%.2x value '%s'",
257 key, tmp_str->str);
4fe9a6da
BV
258 switch (token) {
259 case 0x01:
260 /* Device name */
bb7ef793 261 devname = g_string_append(devname, tmp_str->str);
4fe9a6da
BV
262 break;
263 case 0x02:
264 /* FPGA firmware version */
265 if (version->len)
266 g_string_append(version, ", ");
267 g_string_append(version, "FPGA version ");
268 g_string_append(version, tmp_str->str);
269 break;
270 case 0x03:
271 /* Ancillary version */
272 if (version->len)
273 g_string_append(version, ", ");
274 g_string_append(version, "Ancillary version ");
275 g_string_append(version, tmp_str->str);
276 break;
277 default:
b08024a8
UH
278 sr_info("ols: unknown token 0x%.2x: '%s'",
279 token, tmp_str->str);
4fe9a6da
BV
280 break;
281 }
282 g_string_free(tmp_str, TRUE);
283 break;
284 case 1:
285 /* 32-bit unsigned integer */
286 if (serial_read(fd, &tmp_int, 4) != 4)
287 break;
288 tmp_int = reverse32(tmp_int);
b08024a8
UH
289 sr_dbg("ols: got metadata key 0x%.2x value 0x%.8x",
290 key, tmp_int);
4fe9a6da
BV
291 switch (token) {
292 case 0x00:
293 /* Number of usable probes */
10e5cbed
BV
294 for (ui = 0; ui < tmp_int; ui++) {
295 if (!(probe = sr_probe_new(ui, SR_PROBE_LOGIC, TRUE,
296 probe_names[ui])))
297 return 0;
298 sdi->probes = g_slist_append(sdi->probes, probe);
299 }
4fe9a6da
BV
300 break;
301 case 0x01:
302 /* Amount of sample memory available (bytes) */
ea9cfed7 303 ctx->max_samples = tmp_int;
4fe9a6da
BV
304 break;
305 case 0x02:
306 /* Amount of dynamic memory available (bytes) */
307 /* what is this for? */
308 break;
309 case 0x03:
310 /* Maximum sample rate (hz) */
ea9cfed7 311 ctx->max_samplerate = tmp_int;
4fe9a6da
BV
312 break;
313 case 0x04:
314 /* protocol version */
ea9cfed7 315 ctx->protocol_version = tmp_int;
4fe9a6da
BV
316 break;
317 default:
b08024a8
UH
318 sr_info("ols: unknown token 0x%.2x: 0x%.8x",
319 token, tmp_int);
4fe9a6da
BV
320 break;
321 }
322 break;
323 case 2:
324 /* 8-bit unsigned integer */
325 if (serial_read(fd, &tmp_c, 1) != 1)
326 break;
b08024a8
UH
327 sr_dbg("ols: got metadata key 0x%.2x value 0x%.2x",
328 key, tmp_c);
4fe9a6da
BV
329 switch (token) {
330 case 0x00:
331 /* Number of usable probes */
10e5cbed
BV
332 for (ui = 0; ui < tmp_c; ui++) {
333 if (!(probe = sr_probe_new(ui, SR_PROBE_LOGIC, TRUE,
334 probe_names[ui])))
335 return 0;
336 sdi->probes = g_slist_append(sdi->probes, probe);
337 }
4fe9a6da
BV
338 break;
339 case 0x01:
340 /* protocol version */
ea9cfed7 341 ctx->protocol_version = tmp_c;
4fe9a6da
BV
342 break;
343 default:
b08024a8
UH
344 sr_info("ols: unknown token 0x%.2x: 0x%.2x",
345 token, tmp_c);
4fe9a6da
BV
346 break;
347 }
348 break;
349 default:
350 /* unknown type */
351 break;
352 }
353 }
354
bb7ef793 355 sdi->model = devname->str;
4fe9a6da 356 sdi->version = version->str;
bb7ef793 357 g_string_free(devname, FALSE);
4fe9a6da
BV
358 g_string_free(version, FALSE);
359
360 return sdi;
361}
362
40dda2c3 363static int hw_init(void)
61136ea6
BV
364{
365
366 /* Nothing to do. */
367
368 return SR_OK;
369}
370
10e5cbed 371static GSList *hw_scan(GSList *options)
a1bb33af 372{
d68e2d1a 373 struct sr_dev_inst *sdi;
ea9cfed7 374 struct context *ctx;
10e5cbed
BV
375 struct sr_probe *probe;
376 GSList *devices, *ports, *l;
4fe9a6da 377 GPollFD *fds, probefd;
10e5cbed 378 int devcnt, final_devcnt, num_ports, fd, ret, i, j;
bb7ef793 379 char buf[8], **dev_names, **serial_params;
a1bb33af 380
10e5cbed 381 (void)options;
c0a4b971 382 final_devcnt = 0;
10e5cbed 383 devices = NULL;
c0a4b971 384
40dda2c3
BV
385 /* Scan all serial ports. */
386 ports = list_serial_ports();
a1bb33af 387 num_ports = g_slist_length(ports);
c0a4b971
UH
388
389 if (!(fds = g_try_malloc0(num_ports * sizeof(GPollFD)))) {
390 sr_err("ols: %s: fds malloc failed", __func__);
391 goto hw_init_free_ports; /* TODO: SR_ERR_MALLOC. */
392 }
393
bb7ef793
UH
394 if (!(dev_names = g_try_malloc(num_ports * sizeof(char *)))) {
395 sr_err("ols: %s: dev_names malloc failed", __func__);
c0a4b971
UH
396 goto hw_init_free_fds; /* TODO: SR_ERR_MALLOC. */
397 }
398
399 if (!(serial_params = g_try_malloc(num_ports * sizeof(char *)))) {
400 sr_err("ols: %s: serial_params malloc failed", __func__);
bb7ef793 401 goto hw_init_free_dev_names; /* TODO: SR_ERR_MALLOC. */
c0a4b971
UH
402 }
403
a1bb33af 404 devcnt = 0;
43fc7885
UH
405 for (l = ports; l; l = l->next) {
406 /* The discovery procedure is like this: first send the Reset
407 * command (0x00) 5 times, since the device could be anywhere
408 * in a 5-byte command. Then send the ID command (0x02).
409 * If the device responds with 4 bytes ("OLS1" or "SLA1"), we
410 * have a match.
411 *
412 * Since it may take the device a while to respond at 115Kb/s,
413 * we do all the sending first, then wait for all of them to
414 * respond with g_poll().
a1bb33af 415 */
b08024a8 416 sr_info("ols: probing %s...", (char *)l->data);
d02a535e 417 fd = serial_open(l->data, O_RDWR | O_NONBLOCK);
43fc7885 418 if (fd != -1) {
d02a535e 419 serial_params[devcnt] = serial_backup_params(fd);
f8c1fcda 420 serial_set_params(fd, 115200, 8, SERIAL_PARITY_NONE, 1, 2);
e46b8fb1 421 ret = SR_OK;
43fc7885
UH
422 for (i = 0; i < 5; i++) {
423 if ((ret = send_shortcommand(fd,
e46b8fb1 424 CMD_RESET)) != SR_OK) {
43fc7885 425 /* Serial port is not writable. */
6937bb75
BV
426 break;
427 }
a1bb33af 428 }
e46b8fb1 429 if (ret != SR_OK) {
43fc7885
UH
430 serial_restore_params(fd,
431 serial_params[devcnt]);
d02a535e 432 serial_close(fd);
6937bb75 433 continue;
d02a535e 434 }
6937bb75
BV
435 send_shortcommand(fd, CMD_ID);
436 fds[devcnt].fd = fd;
437 fds[devcnt].events = G_IO_IN;
bb7ef793 438 dev_names[devcnt] = g_strdup(l->data);
6937bb75 439 devcnt++;
a1bb33af 440 }
133a37bf 441 g_free(l->data);
a1bb33af
UH
442 }
443
5b15b41e
PS
444 /* 2ms isn't enough for reliable transfer with pl2303, let's try 10 */
445 usleep(10000);
a1bb33af 446
a1bb33af 447 g_poll(fds, devcnt, 1);
4fe9a6da 448
43fc7885 449 for (i = 0; i < devcnt; i++) {
4fe9a6da
BV
450 if (fds[i].revents != G_IO_IN)
451 continue;
452 if (serial_read(fds[i].fd, buf, 4) != 4)
453 continue;
454 if (strncmp(buf, "1SLO", 4) && strncmp(buf, "1ALS", 4))
455 continue;
456
457 /* definitely using the OLS protocol, check if it supports
458 * the metadata command
459 */
460 send_shortcommand(fds[i].fd, CMD_METADATA);
461 probefd.fd = fds[i].fd;
462 probefd.events = G_IO_IN;
463 if (g_poll(&probefd, 1, 10) > 0) {
464 /* got metadata */
465 sdi = get_metadata(fds[i].fd);
466 sdi->index = final_devcnt;
13d0d269 467 ctx = sdi->priv;
4fe9a6da
BV
468 } else {
469 /* not an OLS -- some other board that uses the sump protocol */
d3683c42 470 sdi = sr_dev_inst_new(final_devcnt, SR_ST_INACTIVE,
4fe9a6da 471 "Sump", "Logic Analyzer", "v1.0");
2efc5948 472 sdi->driver = odi;
ea9cfed7 473 ctx = ols_dev_new();
10e5cbed
BV
474 for (j = 0; j < 32; j++) {
475 if (!(probe = sr_probe_new(j, SR_PROBE_LOGIC, TRUE,
476 probe_names[j])))
477 return 0;
478 sdi->probes = g_slist_append(sdi->probes, probe);
479 }
ea9cfed7 480 sdi->priv = ctx;
a1bb33af 481 }
ea9cfed7 482 ctx->serial = sr_serial_dev_inst_new(dev_names[i], -1);
e5e81856
BV
483 odi->instances = g_slist_append(odi->instances, sdi);
484 devices = g_slist_append(devices, sdi);
485
4fe9a6da
BV
486 final_devcnt++;
487 serial_close(fds[i].fd);
488 fds[i].fd = 0;
4fe9a6da
BV
489 }
490
491 /* clean up after all the probing */
492 for (i = 0; i < devcnt; i++) {
43fc7885 493 if (fds[i].fd != 0) {
d02a535e
BV
494 serial_restore_params(fds[i].fd, serial_params[i]);
495 serial_close(fds[i].fd);
6937bb75 496 }
133a37bf 497 g_free(serial_params[i]);
bb7ef793 498 g_free(dev_names[i]);
a1bb33af
UH
499 }
500
c0a4b971 501 g_free(serial_params);
bb7ef793
UH
502hw_init_free_dev_names:
503 g_free(dev_names);
c0a4b971
UH
504hw_init_free_fds:
505 g_free(fds);
506hw_init_free_ports:
a1bb33af
UH
507 g_slist_free(ports);
508
10e5cbed 509 return devices;
a1bb33af
UH
510}
511
25a0f108 512static int hw_dev_open(struct sr_dev_inst *sdi)
a1bb33af 513{
ea9cfed7 514 struct context *ctx;
a1bb33af 515
ea9cfed7 516 ctx = sdi->priv;
69890f73 517
ea9cfed7
UH
518 ctx->serial->fd = serial_open(ctx->serial->port, O_RDWR);
519 if (ctx->serial->fd == -1)
e46b8fb1 520 return SR_ERR;
a1bb33af 521
5a2326a7 522 sdi->status = SR_ST_ACTIVE;
a1bb33af 523
e46b8fb1 524 return SR_OK;
a1bb33af
UH
525}
526
25a0f108 527static int hw_dev_close(struct sr_dev_inst *sdi)
a1bb33af 528{
ea9cfed7 529 struct context *ctx;
a1bb33af 530
ea9cfed7 531 ctx = sdi->priv;
69890f73 532
ea9cfed7
UH
533 if (ctx->serial->fd != -1) {
534 serial_close(ctx->serial->fd);
535 ctx->serial->fd = -1;
5a2326a7 536 sdi->status = SR_ST_INACTIVE;
a1bb33af 537 }
697785d1
UH
538
539 return SR_OK;
a1bb33af
UH
540}
541
57ab7d9f 542static int hw_cleanup(void)
a1bb33af
UH
543{
544 GSList *l;
d68e2d1a 545 struct sr_dev_inst *sdi;
ea9cfed7 546 struct context *ctx;
57ab7d9f 547 int ret = SR_OK;
a1bb33af 548
8722c31e 549 /* Properly close and free all devices. */
e5e81856 550 for (l = odi->instances; l; l = l->next) {
57ab7d9f
UH
551 if (!(sdi = l->data)) {
552 /* Log error, but continue cleaning up the rest. */
553 sr_err("ols: %s: sdi was NULL, continuing", __func__);
554 ret = SR_ERR_BUG;
555 continue;
556 }
ea9cfed7 557 if (!(ctx = sdi->priv)) {
57ab7d9f
UH
558 /* Log error, but continue cleaning up the rest. */
559 sr_err("ols: %s: sdi->priv was NULL, continuing",
560 __func__);
561 ret = SR_ERR_BUG;
562 continue;
563 }
564 /* TODO: Check for serial != NULL. */
ea9cfed7
UH
565 if (ctx->serial->fd != -1)
566 serial_close(ctx->serial->fd);
567 sr_serial_dev_inst_free(ctx->serial);
d3683c42 568 sr_dev_inst_free(sdi);
a1bb33af 569 }
e5e81856
BV
570 g_slist_free(odi->instances);
571 odi->instances = NULL;
57ab7d9f
UH
572
573 return ret;
a1bb33af
UH
574}
575
dddfb3db
BV
576static int hw_info_get(int info_id, const void **data,
577 const struct sr_dev_inst *sdi)
a1bb33af 578{
ea9cfed7 579 struct context *ctx;
a1bb33af 580
dddfb3db 581 switch (info_id) {
2ca4465b
BV
582 case SR_DI_HWCAPS:
583 *data = hwcaps;
584 break;
5a2326a7 585 case SR_DI_NUM_PROBES:
dddfb3db 586 *data = GINT_TO_POINTER(1);
a1bb33af 587 break;
464d12c7 588 case SR_DI_PROBE_NAMES:
dddfb3db 589 *data = probe_names;
464d12c7 590 break;
5a2326a7 591 case SR_DI_SAMPLERATES:
dddfb3db 592 *data = &samplerates;
a1bb33af 593 break;
5a2326a7 594 case SR_DI_TRIGGER_TYPES:
dddfb3db 595 *data = (char *)TRIGGER_TYPES;
a1bb33af 596 break;
5a2326a7 597 case SR_DI_CUR_SAMPLERATE:
dddfb3db
BV
598 if (sdi) {
599 ctx = sdi->priv;
600 *data = &ctx->cur_samplerate;
601 } else
602 return SR_ERR;
a1bb33af 603 break;
dddfb3db
BV
604 default:
605 return SR_ERR_ARG;
a1bb33af
UH
606 }
607
dddfb3db 608 return SR_OK;
a1bb33af
UH
609}
610
6f4b1868 611static int set_samplerate(const struct sr_dev_inst *sdi, uint64_t samplerate)
a1bb33af 612{
ea9cfed7 613 struct context *ctx;
a1bb33af 614
ea9cfed7
UH
615 ctx = sdi->priv;
616 if (ctx->max_samplerate) {
617 if (samplerate > ctx->max_samplerate)
4fe9a6da
BV
618 return SR_ERR_SAMPLERATE;
619 } else if (samplerate < samplerates.low || samplerate > samplerates.high)
e46b8fb1 620 return SR_ERR_SAMPLERATE;
a1bb33af 621
43fc7885 622 if (samplerate > CLOCK_RATE) {
ea9cfed7
UH
623 ctx->flag_reg |= FLAG_DEMUX;
624 ctx->cur_samplerate_divider = (CLOCK_RATE * 2 / samplerate) - 1;
43fc7885 625 } else {
ea9cfed7
UH
626 ctx->flag_reg &= ~FLAG_DEMUX;
627 ctx->cur_samplerate_divider = (CLOCK_RATE / samplerate) - 1;
a1bb33af 628 }
a1bb33af 629
7583b99d
GM
630 /* Calculate actual samplerate used and complain if it is different
631 * from the requested.
632 */
ea9cfed7
UH
633 ctx->cur_samplerate = CLOCK_RATE / (ctx->cur_samplerate_divider + 1);
634 if (ctx->flag_reg & FLAG_DEMUX)
635 ctx->cur_samplerate *= 2;
636 if (ctx->cur_samplerate != samplerate)
133a37bf 637 sr_err("ols: can't match samplerate %" PRIu64 ", using %"
ea9cfed7 638 PRIu64, samplerate, ctx->cur_samplerate);
7583b99d 639
e46b8fb1 640 return SR_OK;
a1bb33af
UH
641}
642
6f4b1868
BV
643static int hw_dev_config_set(const struct sr_dev_inst *sdi, int hwcap,
644 const void *value)
a1bb33af 645{
ea9cfed7 646 struct context *ctx;
a1bb33af 647 int ret;
1b79df2f 648 const uint64_t *tmp_u64;
a1bb33af 649
ea9cfed7 650 ctx = sdi->priv;
a1bb33af 651
5a2326a7 652 if (sdi->status != SR_ST_ACTIVE)
e46b8fb1 653 return SR_ERR;
a1bb33af 654
ffedd0bf 655 switch (hwcap) {
5a2326a7 656 case SR_HWCAP_SAMPLERATE:
1b79df2f 657 ret = set_samplerate(sdi, *(const uint64_t *)value);
a803c0db 658 break;
5a2326a7 659 case SR_HWCAP_PROBECONFIG:
1b79df2f 660 ret = configure_probes(ctx, (const GSList *)value);
a803c0db 661 break;
5a2326a7 662 case SR_HWCAP_LIMIT_SAMPLES:
2458ea65 663 tmp_u64 = value;
574ce498 664 if (*tmp_u64 < MIN_NUM_SAMPLES)
e46b8fb1 665 return SR_ERR;
ea9cfed7 666 if (*tmp_u64 > ctx->max_samples)
133a37bf 667 sr_err("ols: sample limit exceeds hw max");
ea9cfed7
UH
668 ctx->limit_samples = *tmp_u64;
669 sr_info("ols: sample limit %" PRIu64, ctx->limit_samples);
e46b8fb1 670 ret = SR_OK;
a803c0db 671 break;
5a2326a7 672 case SR_HWCAP_CAPTURE_RATIO:
1b79df2f 673 ctx->capture_ratio = *(const uint64_t *)value;
ea9cfed7
UH
674 if (ctx->capture_ratio < 0 || ctx->capture_ratio > 100) {
675 ctx->capture_ratio = 0;
e46b8fb1 676 ret = SR_ERR;
43fc7885 677 } else
e46b8fb1 678 ret = SR_OK;
a803c0db 679 break;
3a4d09c0 680 case SR_HWCAP_RLE:
4d436e71 681 if (GPOINTER_TO_INT(value)) {
3a4d09c0 682 sr_info("ols: enabling RLE");
ea9cfed7 683 ctx->flag_reg |= FLAG_RLE;
3a4d09c0
GM
684 }
685 ret = SR_OK;
686 break;
a803c0db 687 default:
e46b8fb1 688 ret = SR_ERR;
43fc7885 689 }
a1bb33af
UH
690
691 return ret;
692}
693
1f9813eb 694static int receive_data(int fd, int revents, void *cb_data)
a1bb33af 695{
b9c735a2 696 struct sr_datafeed_packet packet;
9c939c51 697 struct sr_datafeed_logic logic;
d68e2d1a 698 struct sr_dev_inst *sdi;
ea9cfed7 699 struct context *ctx;
4fe9a6da 700 GSList *l;
3a4d09c0
GM
701 int num_channels, offset, i, j;
702 unsigned char byte;
a1bb33af 703
ea9cfed7
UH
704 /* Find this device's ctx struct by its fd. */
705 ctx = NULL;
e5e81856 706 for (l = odi->instances; l; l = l->next) {
4fe9a6da 707 sdi = l->data;
13d0d269 708 ctx = sdi->priv;
ea9cfed7 709 if (ctx->serial->fd == fd) {
4fe9a6da
BV
710 break;
711 }
13d0d269 712 ctx = NULL;
4fe9a6da 713 }
ea9cfed7
UH
714 if (!ctx)
715 /* Shouldn't happen. */
4fe9a6da
BV
716 return TRUE;
717
ea9cfed7 718 if (ctx->num_transfers++ == 0) {
43fc7885
UH
719 /*
720 * First time round, means the device started sending data,
721 * and will not stop until done. If it stops sending for
722 * longer than it takes to send a byte, that means it's
723 * finished. We'll double that to 30ms to be sure...
a1bb33af 724 */
6f1be0a2 725 sr_source_remove(fd);
1f9813eb 726 sr_source_add(fd, G_IO_IN, 30, receive_data, cb_data);
ea9cfed7
UH
727 ctx->raw_sample_buf = g_try_malloc(ctx->limit_samples * 4);
728 if (!ctx->raw_sample_buf) {
729 sr_err("ols: %s: ctx->raw_sample_buf malloc failed",
c0a4b971
UH
730 __func__);
731 return FALSE;
732 }
a803c0db 733 /* fill with 1010... for debugging */
ea9cfed7 734 memset(ctx->raw_sample_buf, 0x82, ctx->limit_samples * 4);
a1bb33af
UH
735 }
736
6937bb75 737 num_channels = 0;
43fc7885 738 for (i = 0x20; i > 0x02; i /= 2) {
ea9cfed7 739 if ((ctx->flag_reg & i) == 0)
6937bb75 740 num_channels++;
43fc7885 741 }
6937bb75 742
3a4d09c0 743 if (revents == G_IO_IN) {
2119ab03 744 if (serial_read(fd, &byte, 1) != 1)
a1bb33af
UH
745 return FALSE;
746
baf1d714 747 /* Ignore it if we've read enough. */
ea9cfed7 748 if (ctx->num_samples >= ctx->limit_samples)
baf1d714 749 return TRUE;
3a4d09c0 750
ea9cfed7 751 ctx->sample[ctx->num_bytes++] = byte;
b08024a8 752 sr_dbg("ols: received byte 0x%.2x", byte);
ea9cfed7 753 if (ctx->num_bytes == num_channels) {
43fc7885 754 /* Got a full sample. */
b08024a8 755 sr_dbg("ols: received sample 0x%.*x",
ea9cfed7
UH
756 ctx->num_bytes * 2, *(int *)ctx->sample);
757 if (ctx->flag_reg & FLAG_RLE) {
43fc7885
UH
758 /*
759 * In RLE mode -1 should never come in as a
760 * sample, because bit 31 is the "count" flag.
43fc7885 761 */
ea9cfed7
UH
762 if (ctx->sample[ctx->num_bytes - 1] & 0x80) {
763 ctx->sample[ctx->num_bytes - 1] &= 0x7f;
baf1d714
UH
764 /*
765 * FIXME: This will only work on
766 * little-endian systems.
a1bb33af 767 */
ea9cfed7
UH
768 ctx->rle_count = *(int *)(ctx->sample);
769 sr_dbg("ols: RLE count = %d", ctx->rle_count);
770 ctx->num_bytes = 0;
3a4d09c0 771 return TRUE;
baf1d714 772 }
3a4d09c0 773 }
ea9cfed7
UH
774 ctx->num_samples += ctx->rle_count + 1;
775 if (ctx->num_samples > ctx->limit_samples) {
baf1d714 776 /* Save us from overrunning the buffer. */
ea9cfed7
UH
777 ctx->rle_count -= ctx->num_samples - ctx->limit_samples;
778 ctx->num_samples = ctx->limit_samples;
a1bb33af
UH
779 }
780
43fc7885
UH
781 if (num_channels < 4) {
782 /*
783 * Some channel groups may have been turned
784 * off, to speed up transfer between the
785 * hardware and the PC. Expand that here before
786 * submitting it over the session bus --
787 * whatever is listening on the bus will be
788 * expecting a full 32-bit sample, based on
789 * the number of probes.
6937bb75
BV
790 */
791 j = 0;
ea9cfed7 792 memset(ctx->tmp_sample, 0, 4);
43fc7885 793 for (i = 0; i < 4; i++) {
ea9cfed7 794 if (((ctx->flag_reg >> 2) & (1 << i)) == 0) {
43fc7885
UH
795 /*
796 * This channel group was
797 * enabled, copy from received
798 * sample.
799 */
ea9cfed7 800 ctx->tmp_sample[i] = ctx->sample[j++];
6937bb75
BV
801 }
802 }
ea9cfed7
UH
803 memcpy(ctx->sample, ctx->tmp_sample, 4);
804 sr_dbg("ols: full sample 0x%.8x", *(int *)ctx->sample);
6937bb75
BV
805 }
806
a803c0db
BV
807 /* the OLS sends its sample buffer backwards.
808 * store it in reverse order here, so we can dump
809 * this on the session bus later.
810 */
ea9cfed7
UH
811 offset = (ctx->limit_samples - ctx->num_samples) * 4;
812 for (i = 0; i <= ctx->rle_count; i++) {
813 memcpy(ctx->raw_sample_buf + offset + (i * 4),
814 ctx->sample, 4);
baf1d714 815 }
ea9cfed7
UH
816 memset(ctx->sample, 0, 4);
817 ctx->num_bytes = 0;
818 ctx->rle_count = 0;
a1bb33af 819 }
43fc7885
UH
820 } else {
821 /*
822 * This is the main loop telling us a timeout was reached, or
823 * we've acquired all the samples we asked for -- we're done.
a803c0db 824 * Send the (properly-ordered) buffer to the frontend.
43fc7885 825 */
ea9cfed7 826 if (ctx->trigger_at != -1) {
a803c0db
BV
827 /* a trigger was set up, so we need to tell the frontend
828 * about it.
829 */
ea9cfed7 830 if (ctx->trigger_at > 0) {
a803c0db 831 /* there are pre-trigger samples, send those first */
5a2326a7 832 packet.type = SR_DF_LOGIC;
9c939c51 833 packet.payload = &logic;
ea9cfed7 834 logic.length = ctx->trigger_at * 4;
9c939c51 835 logic.unitsize = 4;
ea9cfed7
UH
836 logic.data = ctx->raw_sample_buf +
837 (ctx->limit_samples - ctx->num_samples) * 4;
1f9813eb 838 sr_session_send(cb_data, &packet);
a803c0db
BV
839 }
840
9c939c51 841 /* send the trigger */
5a2326a7 842 packet.type = SR_DF_TRIGGER;
1f9813eb 843 sr_session_send(cb_data, &packet);
a803c0db 844
9c939c51 845 /* send post-trigger samples */
5a2326a7 846 packet.type = SR_DF_LOGIC;
9c939c51 847 packet.payload = &logic;
ea9cfed7 848 logic.length = (ctx->num_samples * 4) - (ctx->trigger_at * 4);
9c939c51 849 logic.unitsize = 4;
ea9cfed7
UH
850 logic.data = ctx->raw_sample_buf + ctx->trigger_at * 4 +
851 (ctx->limit_samples - ctx->num_samples) * 4;
1f9813eb 852 sr_session_send(cb_data, &packet);
a803c0db 853 } else {
9c939c51 854 /* no trigger was used */
5a2326a7 855 packet.type = SR_DF_LOGIC;
9c939c51 856 packet.payload = &logic;
ea9cfed7 857 logic.length = ctx->num_samples * 4;
9c939c51 858 logic.unitsize = 4;
ea9cfed7
UH
859 logic.data = ctx->raw_sample_buf +
860 (ctx->limit_samples - ctx->num_samples) * 4;
1f9813eb 861 sr_session_send(cb_data, &packet);
a803c0db 862 }
ea9cfed7 863 g_free(ctx->raw_sample_buf);
a803c0db 864
06d64eb8 865 serial_flush(fd);
d02a535e 866 serial_close(fd);
5a2326a7 867 packet.type = SR_DF_END;
1f9813eb 868 sr_session_send(cb_data, &packet);
a1bb33af
UH
869 }
870
871 return TRUE;
872}
873
5d9ed643
BV
874static int hw_dev_acquisition_start(const struct sr_dev_inst *sdi,
875 void *cb_data)
a1bb33af 876{
b9c735a2
UH
877 struct sr_datafeed_packet *packet;
878 struct sr_datafeed_header *header;
f366e86c 879 struct sr_datafeed_meta_logic meta;
ea9cfed7 880 struct context *ctx;
a803c0db 881 uint32_t trigger_config[4];
a1bb33af 882 uint32_t data;
6937bb75
BV
883 uint16_t readcount, delaycount;
884 uint8_t changrp_mask;
22130421 885 int num_channels;
4fe9a6da 886 int i;
a1bb33af 887
ea9cfed7 888 ctx = sdi->priv;
a1bb33af 889
5a2326a7 890 if (sdi->status != SR_ST_ACTIVE)
e46b8fb1 891 return SR_ERR;
a1bb33af 892
22130421
GM
893 /*
894 * Enable/disable channel groups in the flag register according to the
baf1d714 895 * probe mask. Calculate this here, because num_channels is needed
22130421
GM
896 * to limit readcount.
897 */
898 changrp_mask = 0;
899 num_channels = 0;
900 for (i = 0; i < 4; i++) {
ea9cfed7 901 if (ctx->probe_mask & (0xff << (i * 8))) {
22130421
GM
902 changrp_mask |= (1 << i);
903 num_channels++;
904 }
905 }
906
baf1d714
UH
907 /*
908 * Limit readcount to prevent reading past the end of the hardware
22130421
GM
909 * buffer.
910 */
ea9cfed7 911 readcount = MIN(ctx->max_samples / num_channels, ctx->limit_samples) / 4;
a803c0db
BV
912
913 memset(trigger_config, 0, 16);
ea9cfed7
UH
914 trigger_config[ctx->num_stages - 1] |= 0x08;
915 if (ctx->trigger_mask[0]) {
916 delaycount = readcount * (1 - ctx->capture_ratio / 100.0);
917 ctx->trigger_at = (readcount - delaycount) * 4 - ctx->num_stages;
a803c0db 918
ea9cfed7
UH
919 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_MASK_0,
920 reverse32(ctx->trigger_mask[0])) != SR_OK)
e46b8fb1 921 return SR_ERR;
ea9cfed7
UH
922 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_VALUE_0,
923 reverse32(ctx->trigger_value[0])) != SR_OK)
e46b8fb1 924 return SR_ERR;
ea9cfed7 925 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_CONFIG_0,
e46b8fb1
UH
926 trigger_config[0]) != SR_OK)
927 return SR_ERR;
6937bb75 928
ea9cfed7
UH
929 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_MASK_1,
930 reverse32(ctx->trigger_mask[1])) != SR_OK)
e46b8fb1 931 return SR_ERR;
ea9cfed7
UH
932 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_VALUE_1,
933 reverse32(ctx->trigger_value[1])) != SR_OK)
e46b8fb1 934 return SR_ERR;
ea9cfed7 935 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_CONFIG_1,
e46b8fb1
UH
936 trigger_config[1]) != SR_OK)
937 return SR_ERR;
6937bb75 938
ea9cfed7
UH
939 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_MASK_2,
940 reverse32(ctx->trigger_mask[2])) != SR_OK)
e46b8fb1 941 return SR_ERR;
ea9cfed7
UH
942 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_VALUE_2,
943 reverse32(ctx->trigger_value[2])) != SR_OK)
e46b8fb1 944 return SR_ERR;
ea9cfed7 945 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_CONFIG_2,
e46b8fb1
UH
946 trigger_config[2]) != SR_OK)
947 return SR_ERR;
a803c0db 948
ea9cfed7
UH
949 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_MASK_3,
950 reverse32(ctx->trigger_mask[3])) != SR_OK)
e46b8fb1 951 return SR_ERR;
ea9cfed7
UH
952 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_VALUE_3,
953 reverse32(ctx->trigger_value[3])) != SR_OK)
e46b8fb1 954 return SR_ERR;
ea9cfed7 955 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_CONFIG_3,
e46b8fb1
UH
956 trigger_config[3]) != SR_OK)
957 return SR_ERR;
6937bb75 958 } else {
ea9cfed7
UH
959 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_MASK_0,
960 ctx->trigger_mask[0]) != SR_OK)
e46b8fb1 961 return SR_ERR;
ea9cfed7
UH
962 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_VALUE_0,
963 ctx->trigger_value[0]) != SR_OK)
e46b8fb1 964 return SR_ERR;
ea9cfed7 965 if (send_longcommand(ctx->serial->fd, CMD_SET_TRIGGER_CONFIG_0,
e46b8fb1
UH
966 0x00000008) != SR_OK)
967 return SR_ERR;
a803c0db 968 delaycount = readcount;
6937bb75 969 }
a1bb33af 970
b08024a8 971 sr_info("ols: setting samplerate to %" PRIu64 " Hz (divider %u, "
ea9cfed7
UH
972 "demux %s)", ctx->cur_samplerate, ctx->cur_samplerate_divider,
973 ctx->flag_reg & FLAG_DEMUX ? "on" : "off");
974 if (send_longcommand(ctx->serial->fd, CMD_SET_DIVIDER,
975 reverse32(ctx->cur_samplerate_divider)) != SR_OK)
4fe9a6da 976 return SR_ERR;
a1bb33af 977
43fc7885 978 /* Send sample limit and pre/post-trigger capture ratio. */
a803c0db
BV
979 data = ((readcount - 1) & 0xffff) << 16;
980 data |= (delaycount - 1) & 0xffff;
ea9cfed7 981 if (send_longcommand(ctx->serial->fd, CMD_CAPTURE_SIZE, reverse16(data)) != SR_OK)
e46b8fb1 982 return SR_ERR;
a1bb33af 983
43fc7885 984 /* The flag register wants them here, and 1 means "disable channel". */
ea9cfed7
UH
985 ctx->flag_reg |= ~(changrp_mask << 2) & 0x3c;
986 ctx->flag_reg |= FLAG_FILTER;
987 ctx->rle_count = 0;
988 data = (ctx->flag_reg << 24) | ((ctx->flag_reg << 8) & 0xff0000);
989 if (send_longcommand(ctx->serial->fd, CMD_SET_FLAGS, data) != SR_OK)
e46b8fb1 990 return SR_ERR;
a1bb33af 991
43fc7885 992 /* Start acquisition on the device. */
ea9cfed7 993 if (send_shortcommand(ctx->serial->fd, CMD_RUN) != SR_OK)
e46b8fb1 994 return SR_ERR;
a1bb33af 995
ea9cfed7 996 sr_source_add(ctx->serial->fd, G_IO_IN, -1, receive_data,
3cd3a20b 997 cb_data);
a1bb33af 998
b53738ba
UH
999 if (!(packet = g_try_malloc(sizeof(struct sr_datafeed_packet)))) {
1000 sr_err("ols: %s: packet malloc failed", __func__);
1001 return SR_ERR_MALLOC;
1002 }
1003
1004 if (!(header = g_try_malloc(sizeof(struct sr_datafeed_header)))) {
1005 sr_err("ols: %s: header malloc failed", __func__);
c0a4b971 1006 g_free(packet);
b53738ba
UH
1007 return SR_ERR_MALLOC;
1008 }
1009
43fc7885 1010 /* Send header packet to the session bus. */
5a2326a7 1011 packet->type = SR_DF_HEADER;
43fc7885 1012 packet->payload = (unsigned char *)header;
a1bb33af
UH
1013 header->feed_version = 1;
1014 gettimeofday(&header->starttime, NULL);
f366e86c
BV
1015 sr_session_send(cb_data, packet);
1016
1017 /* Send metadata about the SR_DF_LOGIC packets to come. */
1018 packet->type = SR_DF_META_LOGIC;
1019 packet->payload = &meta;
1020 meta.samplerate = ctx->cur_samplerate;
1021 meta.num_probes = NUM_PROBES;
3cd3a20b 1022 sr_session_send(cb_data, packet);
c0a4b971 1023
a1bb33af
UH
1024 g_free(header);
1025 g_free(packet);
1026
e46b8fb1 1027 return SR_OK;
a1bb33af
UH
1028}
1029
3cd3a20b 1030/* TODO: This stops acquisition on ALL devices, ignoring dev_index. */
5d9ed643
BV
1031static int hw_dev_acquisition_stop(const struct sr_dev_inst *sdi,
1032 void *cb_data)
a1bb33af 1033{
b9c735a2 1034 struct sr_datafeed_packet packet;
a1bb33af 1035
17e1afcb 1036 /* Avoid compiler warnings. */
5d9ed643 1037 (void)sdi;
afc8e4de 1038
5a2326a7 1039 packet.type = SR_DF_END;
3cd3a20b 1040 sr_session_send(cb_data, &packet);
3010f21c
UH
1041
1042 return SR_OK;
a1bb33af
UH
1043}
1044
c09f0b57 1045SR_PRIV struct sr_dev_driver ols_driver_info = {
e519ba86
UH
1046 .name = "ols",
1047 .longname = "Openbench Logic Sniffer",
1048 .api_version = 1,
1049 .init = hw_init,
1050 .cleanup = hw_cleanup,
61136ea6 1051 .scan = hw_scan,
e7eb703f
UH
1052 .dev_open = hw_dev_open,
1053 .dev_close = hw_dev_close,
dddfb3db 1054 .info_get = hw_info_get,
a9a245b4 1055 .dev_config_set = hw_dev_config_set,
69040b7c
UH
1056 .dev_acquisition_start = hw_dev_acquisition_start,
1057 .dev_acquisition_stop = hw_dev_acquisition_stop,
e5e81856 1058 .instances = NULL,
a1bb33af 1059};