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Constify some more 'char *' parameters.
[libsigrok.git] / hardware / openbench-logic-sniffer / ols.c
CommitLineData
a1bb33af
UH
1/*
2 * This file is part of the sigrok project.
3 *
4 * Copyright (C) 2010 Bert Vermeulen <bert@biot.com>
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include <stdio.h>
21#include <stdint.h>
22#include <stdlib.h>
23#include <sys/types.h>
24#include <sys/stat.h>
25#include <fcntl.h>
26#include <unistd.h>
a9f54bcd
UH
27#ifdef _WIN32
28#include <windows.h>
29#else
a1bb33af 30#include <termios.h>
926b866c 31#endif
a1bb33af
UH
32#include <string.h>
33#include <sys/time.h>
34#include <inttypes.h>
926b866c
UH
35#ifdef _WIN32
36/* TODO */
37#else
6937bb75 38#include <arpa/inet.h>
926b866c 39#endif
a1bb33af 40#include <glib.h>
43fc7885 41#include <sigrok.h>
1483577e 42#include <sigrok-internal.h>
a1bb33af 43
1fdb75e1
UH
44#ifdef _WIN32
45#define O_NONBLOCK FIONBIO
46#endif
47
574ce498
BV
48#define NUM_PROBES 32
49#define NUM_TRIGGER_STAGES 4
50#define TRIGGER_TYPES "01"
51#define SERIAL_SPEED B115200
52#define CLOCK_RATE MHZ(100)
53#define MIN_NUM_SAMPLES 4
a1bb33af 54
43fc7885 55/* Command opcodes */
574ce498
BV
56#define CMD_RESET 0x00
57#define CMD_ID 0x02
58#define CMD_SET_FLAGS 0x82
59#define CMD_SET_DIVIDER 0x80
60#define CMD_RUN 0x01
61#define CMD_CAPTURE_SIZE 0x81
62#define CMD_SET_TRIGGER_MASK_0 0xc0
63#define CMD_SET_TRIGGER_MASK_1 0xc4
64#define CMD_SET_TRIGGER_MASK_2 0xc8
65#define CMD_SET_TRIGGER_MASK_3 0xcc
66#define CMD_SET_TRIGGER_VALUE_0 0xc1
67#define CMD_SET_TRIGGER_VALUE_1 0xc5
68#define CMD_SET_TRIGGER_VALUE_2 0xc9
69#define CMD_SET_TRIGGER_VALUE_3 0xcd
70#define CMD_SET_TRIGGER_CONFIG_0 0xc2
71#define CMD_SET_TRIGGER_CONFIG_1 0xc6
72#define CMD_SET_TRIGGER_CONFIG_2 0xca
73#define CMD_SET_TRIGGER_CONFIG_3 0xce
a1bb33af 74
43fc7885 75/* Bitmasks for CMD_FLAGS */
574ce498
BV
76#define FLAG_DEMUX 0x01
77#define FLAG_FILTER 0x02
78#define FLAG_CHANNELGROUP_1 0x04
79#define FLAG_CHANNELGROUP_2 0x08
80#define FLAG_CHANNELGROUP_3 0x10
81#define FLAG_CHANNELGROUP_4 0x20
82#define FLAG_CLOCK_EXTERNAL 0x40
83#define FLAG_CLOCK_INVERTED 0x80
84#define FLAG_RLE 0x0100
a1bb33af
UH
85
86static int capabilities[] = {
5a2326a7
UH
87 SR_HWCAP_LOGIC_ANALYZER,
88 SR_HWCAP_SAMPLERATE,
89 SR_HWCAP_CAPTURE_RATIO,
90 SR_HWCAP_LIMIT_SAMPLES,
43fc7885 91 0,
a1bb33af
UH
92};
93
60679b18 94static struct sr_samplerates samplerates = {
6937bb75 95 10,
a1bb33af
UH
96 MHZ(200),
97 1,
43fc7885 98 0,
a1bb33af
UH
99};
100
6c290072 101/* List of struct sr_serial_device_instance */
a1bb33af
UH
102static GSList *device_instances = NULL;
103
43fc7885 104/* Current state of the flag register */
6937bb75 105static uint32_t flag_reg = 0;
a1bb33af
UH
106
107static uint64_t cur_samplerate = 0;
108static uint64_t limit_samples = 0;
43fc7885
UH
109/*
110 * Pre/post trigger capture ratio, in percentage.
111 * 0 means no pre-trigger data.
112 */
6937bb75 113static int capture_ratio = 0;
a803c0db 114static int trigger_at = -1;
43fc7885
UH
115static uint32_t probe_mask = 0xffffffff;
116static uint32_t trigger_mask[4] = { 0, 0, 0, 0 };
117static uint32_t trigger_value[4] = { 0, 0, 0, 0 };
a803c0db 118static int num_stages = 0;
a1bb33af 119
6937bb75 120static int send_shortcommand(int fd, uint8_t command)
a1bb33af
UH
121{
122 char buf[1];
123
edc508d4 124 g_debug("ols: sending cmd 0x%.2x", command);
a1bb33af 125 buf[0] = command;
2119ab03 126 if (serial_write(fd, buf, 1) != 1)
e46b8fb1 127 return SR_ERR;
a1bb33af 128
e46b8fb1 129 return SR_OK;
a1bb33af
UH
130}
131
6937bb75 132static int send_longcommand(int fd, uint8_t command, uint32_t data)
a1bb33af
UH
133{
134 char buf[5];
135
edc508d4 136 g_debug("ols: sending cmd 0x%.2x data 0x%.8x", command, data);
a1bb33af 137 buf[0] = command;
6937bb75
BV
138 buf[1] = (data & 0xff000000) >> 24;
139 buf[2] = (data & 0xff0000) >> 16;
140 buf[3] = (data & 0xff00) >> 8;
141 buf[4] = data & 0xff;
2119ab03 142 if (serial_write(fd, buf, 5) != 5)
e46b8fb1 143 return SR_ERR;
a1bb33af 144
e46b8fb1 145 return SR_OK;
a1bb33af
UH
146}
147
148static int configure_probes(GSList *probes)
149{
1afe8989 150 struct sr_probe *probe;
a1bb33af 151 GSList *l;
6937bb75 152 int probe_bit, stage, i;
a1bb33af
UH
153 char *tc;
154
155 probe_mask = 0;
43fc7885 156 for (i = 0; i < NUM_TRIGGER_STAGES; i++) {
a1bb33af
UH
157 trigger_mask[i] = 0;
158 trigger_value[i] = 0;
159 }
160
a803c0db 161 num_stages = 0;
43fc7885 162 for (l = probes; l; l = l->next) {
1afe8989 163 probe = (struct sr_probe *)l->data;
43fc7885 164 if (!probe->enabled)
6937bb75
BV
165 continue;
166
43fc7885
UH
167 /*
168 * Set up the probe mask for later configuration into the
169 * flag register.
170 */
a1bb33af
UH
171 probe_bit = 1 << (probe->index - 1);
172 probe_mask |= probe_bit;
6937bb75 173
a803c0db 174 if (!probe->trigger)
6937bb75
BV
175 continue;
176
43fc7885 177 /* Configure trigger mask and value. */
6937bb75 178 stage = 0;
43fc7885 179 for (tc = probe->trigger; tc && *tc; tc++) {
6937bb75 180 trigger_mask[stage] |= probe_bit;
43fc7885 181 if (*tc == '1')
6937bb75
BV
182 trigger_value[stage] |= probe_bit;
183 stage++;
43fc7885
UH
184 if (stage > 3)
185 /*
186 * TODO: Only supporting parallel mode, with
187 * up to 4 stages.
188 */
e46b8fb1 189 return SR_ERR;
a1bb33af 190 }
a803c0db
BV
191 if (stage > num_stages)
192 num_stages = stage;
a1bb33af
UH
193 }
194
e46b8fb1 195 return SR_OK;
a1bb33af
UH
196}
197
a803c0db 198static uint32_t reverse16(uint32_t in)
6937bb75
BV
199{
200 uint32_t out;
201
a803c0db
BV
202 out = (in & 0xff) << 8;
203 out |= (in & 0xff00) >> 8;
204 out |= (in & 0xff0000) << 8;
205 out |= (in & 0xff000000) >> 8;
206
207 return out;
208}
209
210static uint32_t reverse32(uint32_t in)
211{
212 uint32_t out;
213
214 out = (in & 0xff) << 24;
215 out |= (in & 0xff00) << 8;
216 out |= (in & 0xff0000) >> 8;
217 out |= (in & 0xff000000) >> 24;
218
219 return out;
6937bb75
BV
220}
221
54ac5277 222static int hw_init(const char *deviceinfo)
a1bb33af 223{
a00ba012 224 struct sr_device_instance *sdi;
a1bb33af
UH
225 GSList *ports, *l;
226 GPollFD *fds;
6937bb75 227 int devcnt, final_devcnt, num_ports, fd, ret, i;
d02a535e 228 char buf[8], **device_names, **serial_params;
a1bb33af 229
43fc7885 230 if (deviceinfo)
6937bb75 231 ports = g_slist_append(NULL, strdup(deviceinfo));
a1bb33af 232 else
43fc7885 233 /* No specific device given, so scan all serial ports. */
a1bb33af
UH
234 ports = list_serial_ports();
235
236 num_ports = g_slist_length(ports);
6937bb75 237 fds = calloc(1, num_ports * sizeof(GPollFD));
43fc7885
UH
238 device_names = malloc(num_ports * sizeof(char *));
239 serial_params = malloc(num_ports * sizeof(char *));
a1bb33af 240 devcnt = 0;
43fc7885
UH
241 for (l = ports; l; l = l->next) {
242 /* The discovery procedure is like this: first send the Reset
243 * command (0x00) 5 times, since the device could be anywhere
244 * in a 5-byte command. Then send the ID command (0x02).
245 * If the device responds with 4 bytes ("OLS1" or "SLA1"), we
246 * have a match.
247 *
248 * Since it may take the device a while to respond at 115Kb/s,
249 * we do all the sending first, then wait for all of them to
250 * respond with g_poll().
a1bb33af 251 */
e6ac9ac8 252 g_message("ols: probing %s...", (char *)l->data);
d02a535e 253 fd = serial_open(l->data, O_RDWR | O_NONBLOCK);
43fc7885 254 if (fd != -1) {
d02a535e
BV
255 serial_params[devcnt] = serial_backup_params(fd);
256 serial_set_params(fd, 115200, 8, 0, 1, 2);
e46b8fb1 257 ret = SR_OK;
43fc7885
UH
258 for (i = 0; i < 5; i++) {
259 if ((ret = send_shortcommand(fd,
e46b8fb1 260 CMD_RESET)) != SR_OK) {
43fc7885 261 /* Serial port is not writable. */
6937bb75
BV
262 break;
263 }
a1bb33af 264 }
e46b8fb1 265 if (ret != SR_OK) {
43fc7885
UH
266 serial_restore_params(fd,
267 serial_params[devcnt]);
d02a535e 268 serial_close(fd);
6937bb75 269 continue;
d02a535e 270 }
6937bb75
BV
271 send_shortcommand(fd, CMD_ID);
272 fds[devcnt].fd = fd;
273 fds[devcnt].events = G_IO_IN;
274 device_names[devcnt] = strdup(l->data);
275 devcnt++;
a1bb33af 276 }
6937bb75 277 free(l->data);
a1bb33af
UH
278 }
279
5b15b41e
PS
280 /* 2ms isn't enough for reliable transfer with pl2303, let's try 10 */
281 usleep(10000);
a1bb33af
UH
282
283 final_devcnt = 0;
284 g_poll(fds, devcnt, 1);
43fc7885
UH
285 for (i = 0; i < devcnt; i++) {
286 if (fds[i].revents == G_IO_IN) {
2119ab03 287 if (serial_read(fds[i].fd, buf, 4) == 4) {
43fc7885
UH
288 if (!strncmp(buf, "1SLO", 4)
289 || !strncmp(buf, "1ALS", 4)) {
290 if (!strncmp(buf, "1SLO", 4))
a00ba012 291 sdi = sr_device_instance_new
5a2326a7 292 (final_devcnt, SR_ST_INACTIVE,
43fc7885
UH
293 "Openbench",
294 "Logic Sniffer", "v1.0");
a1bb33af 295 else
a00ba012 296 sdi = sr_device_instance_new
5a2326a7 297 (final_devcnt, SR_ST_INACTIVE,
e6ac9ac8 298 "Openbench", "Logic Sniffer",
43fc7885 299 "v1.0");
6c290072 300 sdi->serial = sr_serial_device_instance_new
43fc7885
UH
301 (device_names[i], -1);
302 device_instances =
303 g_slist_append(device_instances, sdi);
a1bb33af 304 final_devcnt++;
d02a535e 305 serial_close(fds[i].fd);
a1bb33af
UH
306 fds[i].fd = 0;
307 }
308 }
6937bb75 309 free(device_names[i]);
a1bb33af
UH
310 }
311
43fc7885 312 if (fds[i].fd != 0) {
d02a535e
BV
313 serial_restore_params(fds[i].fd, serial_params[i]);
314 serial_close(fds[i].fd);
6937bb75 315 }
d02a535e 316 free(serial_params[i]);
a1bb33af
UH
317 }
318
6937bb75
BV
319 free(fds);
320 free(device_names);
d02a535e 321 free(serial_params);
a1bb33af
UH
322 g_slist_free(ports);
323
904e0b58 324 cur_samplerate = KHZ(200);
6937bb75 325
a1bb33af
UH
326 return final_devcnt;
327}
328
a1bb33af
UH
329static int hw_opendev(int device_index)
330{
a00ba012 331 struct sr_device_instance *sdi;
a1bb33af 332
d32d961d 333 if (!(sdi = sr_get_device_instance(device_instances, device_index)))
e46b8fb1 334 return SR_ERR;
a1bb33af 335
d02a535e 336 sdi->serial->fd = serial_open(sdi->serial->port, O_RDWR);
43fc7885 337 if (sdi->serial->fd == -1)
e46b8fb1 338 return SR_ERR;
a1bb33af 339
5a2326a7 340 sdi->status = SR_ST_ACTIVE;
a1bb33af 341
e46b8fb1 342 return SR_OK;
a1bb33af
UH
343}
344
a1bb33af
UH
345static void hw_closedev(int device_index)
346{
a00ba012 347 struct sr_device_instance *sdi;
a1bb33af 348
d32d961d 349 if (!(sdi = sr_get_device_instance(device_instances, device_index)))
a1bb33af
UH
350 return;
351
43fc7885 352 if (sdi->serial->fd != -1) {
d02a535e 353 serial_close(sdi->serial->fd);
a1bb33af 354 sdi->serial->fd = -1;
5a2326a7 355 sdi->status = SR_ST_INACTIVE;
a1bb33af 356 }
a1bb33af
UH
357}
358
a1bb33af
UH
359static void hw_cleanup(void)
360{
361 GSList *l;
a00ba012 362 struct sr_device_instance *sdi;
a1bb33af 363
43fc7885
UH
364 /* Properly close all devices. */
365 for (l = device_instances; l; l = l->next) {
a1bb33af 366 sdi = l->data;
43fc7885 367 if (sdi->serial->fd != -1)
d02a535e 368 serial_close(sdi->serial->fd);
a00ba012 369 sr_device_instance_free(sdi);
a1bb33af
UH
370 }
371 g_slist_free(device_instances);
372 device_instances = NULL;
a1bb33af
UH
373}
374
a1bb33af
UH
375static void *hw_get_device_info(int device_index, int device_info_id)
376{
a00ba012 377 struct sr_device_instance *sdi;
a1bb33af
UH
378 void *info;
379
d32d961d 380 if (!(sdi = sr_get_device_instance(device_instances, device_index)))
a1bb33af
UH
381 return NULL;
382
383 info = NULL;
43fc7885 384 switch (device_info_id) {
5a2326a7 385 case SR_DI_INSTANCE:
a1bb33af
UH
386 info = sdi;
387 break;
5a2326a7 388 case SR_DI_NUM_PROBES:
a1bb33af
UH
389 info = GINT_TO_POINTER(NUM_PROBES);
390 break;
5a2326a7 391 case SR_DI_SAMPLERATES:
a1bb33af
UH
392 info = &samplerates;
393 break;
5a2326a7 394 case SR_DI_TRIGGER_TYPES:
43fc7885 395 info = (char *)TRIGGER_TYPES;
a1bb33af 396 break;
5a2326a7 397 case SR_DI_CUR_SAMPLERATE:
a1bb33af
UH
398 info = &cur_samplerate;
399 break;
400 }
401
402 return info;
403}
404
a1bb33af
UH
405static int hw_get_status(int device_index)
406{
a00ba012 407 struct sr_device_instance *sdi;
a1bb33af 408
d32d961d 409 if (!(sdi = sr_get_device_instance(device_instances, device_index)))
5a2326a7 410 return SR_ST_NOT_FOUND;
a1bb33af
UH
411
412 return sdi->status;
413}
414
a1bb33af
UH
415static int *hw_get_capabilities(void)
416{
a1bb33af
UH
417 return capabilities;
418}
419
a00ba012 420static int set_configuration_samplerate(struct sr_device_instance *sdi,
43fc7885 421 uint64_t samplerate)
a1bb33af
UH
422{
423 uint32_t divider;
424
43fc7885 425 if (samplerate < samplerates.low || samplerate > samplerates.high)
e46b8fb1 426 return SR_ERR_SAMPLERATE;
a1bb33af 427
43fc7885 428 if (samplerate > CLOCK_RATE) {
a1bb33af 429 flag_reg |= FLAG_DEMUX;
6937bb75 430 divider = (CLOCK_RATE * 2 / samplerate) - 1;
43fc7885 431 } else {
6937bb75
BV
432 flag_reg &= ~FLAG_DEMUX;
433 divider = (CLOCK_RATE / samplerate) - 1;
a1bb33af 434 }
a1bb33af 435
e6ac9ac8 436 g_message("ols: setting samplerate to %" PRIu64 " Hz (divider %u, demux %s)",
a803c0db 437 samplerate, divider, flag_reg & FLAG_DEMUX ? "on" : "off");
43fc7885 438
e46b8fb1
UH
439 if (send_longcommand(sdi->serial->fd, CMD_SET_DIVIDER, reverse32(divider)) != SR_OK)
440 return SR_ERR;
a1bb33af
UH
441 cur_samplerate = samplerate;
442
e46b8fb1 443 return SR_OK;
a1bb33af
UH
444}
445
a1bb33af
UH
446static int hw_set_configuration(int device_index, int capability, void *value)
447{
a00ba012 448 struct sr_device_instance *sdi;
a1bb33af
UH
449 int ret;
450 uint64_t *tmp_u64;
451
d32d961d 452 if (!(sdi = sr_get_device_instance(device_instances, device_index)))
e46b8fb1 453 return SR_ERR;
a1bb33af 454
5a2326a7 455 if (sdi->status != SR_ST_ACTIVE)
e46b8fb1 456 return SR_ERR;
a1bb33af 457
a803c0db 458 switch (capability) {
5a2326a7 459 case SR_HWCAP_SAMPLERATE:
a1bb33af
UH
460 tmp_u64 = value;
461 ret = set_configuration_samplerate(sdi, *tmp_u64);
a803c0db 462 break;
5a2326a7 463 case SR_HWCAP_PROBECONFIG:
43fc7885 464 ret = configure_probes((GSList *) value);
a803c0db 465 break;
5a2326a7 466 case SR_HWCAP_LIMIT_SAMPLES:
2458ea65 467 tmp_u64 = value;
574ce498 468 if (*tmp_u64 < MIN_NUM_SAMPLES)
e46b8fb1 469 return SR_ERR;
2458ea65 470 limit_samples = *tmp_u64;
e6ac9ac8 471 g_message("ols: sample limit %" PRIu64, limit_samples);
e46b8fb1 472 ret = SR_OK;
a803c0db 473 break;
5a2326a7 474 case SR_HWCAP_CAPTURE_RATIO:
a803c0db
BV
475 tmp_u64 = value;
476 capture_ratio = *tmp_u64;
43fc7885 477 if (capture_ratio < 0 || capture_ratio > 100) {
a1bb33af 478 capture_ratio = 0;
e46b8fb1 479 ret = SR_ERR;
43fc7885 480 } else
e46b8fb1 481 ret = SR_OK;
a803c0db
BV
482 break;
483 default:
e46b8fb1 484 ret = SR_ERR;
43fc7885 485 }
a1bb33af
UH
486
487 return ret;
488}
489
a1bb33af
UH
490static int receive_data(int fd, int revents, void *user_data)
491{
afc8e4de 492 static unsigned int num_transfers = 0;
a1bb33af 493 static int num_bytes = 0;
43fc7885
UH
494 static char last_sample[4] = { 0xff, 0xff, 0xff, 0xff };
495 static unsigned char sample[4] = { 0, 0, 0, 0 };
496 static unsigned char tmp_sample[4];
a803c0db
BV
497 static unsigned char *raw_sample_buf = NULL;
498 int count, buflen, num_channels, offset, i, j;
b9c735a2 499 struct sr_datafeed_packet packet;
a1bb33af
UH
500 unsigned char byte, *buffer;
501
43fc7885
UH
502 if (num_transfers++ == 0) {
503 /*
504 * First time round, means the device started sending data,
505 * and will not stop until done. If it stops sending for
506 * longer than it takes to send a byte, that means it's
507 * finished. We'll double that to 30ms to be sure...
a1bb33af 508 */
6f1be0a2
UH
509 sr_source_remove(fd);
510 sr_source_add(fd, G_IO_IN, 30, receive_data, user_data);
a803c0db
BV
511 raw_sample_buf = malloc(limit_samples * 4);
512 /* fill with 1010... for debugging */
513 memset(raw_sample_buf, 0x82, limit_samples * 4);
a1bb33af
UH
514 }
515
6937bb75 516 num_channels = 0;
43fc7885
UH
517 for (i = 0x20; i > 0x02; i /= 2) {
518 if ((flag_reg & i) == 0)
6937bb75 519 num_channels++;
43fc7885 520 }
6937bb75 521
43fc7885
UH
522 if (revents == G_IO_IN
523 && num_transfers / num_channels <= limit_samples) {
2119ab03 524 if (serial_read(fd, &byte, 1) != 1)
a1bb33af
UH
525 return FALSE;
526
527 sample[num_bytes++] = byte;
e6ac9ac8 528 g_debug("ols: received byte 0x%.2x", byte);
43fc7885 529 if (num_bytes == num_channels) {
e6ac9ac8 530 g_debug("ols: received sample 0x%.*x", num_bytes * 2, (int) *sample);
43fc7885
UH
531 /* Got a full sample. */
532 if (flag_reg & FLAG_RLE) {
533 /*
534 * In RLE mode -1 should never come in as a
535 * sample, because bit 31 is the "count" flag.
536 * TODO: Endianness may be wrong here, could be
537 * sample[3].
538 */
539 if (sample[0] & 0x80
540 && !(last_sample[0] & 0x80)) {
541 count = (int)(*sample) & 0x7fffffff;
a1bb33af
UH
542 buffer = g_malloc(count);
543 buflen = 0;
43fc7885 544 for (i = 0; i < count; i++) {
a803c0db 545 memcpy(buffer + buflen, last_sample, 4);
a1bb33af
UH
546 buflen += 4;
547 }
43fc7885
UH
548 } else {
549 /*
550 * Just a single sample, next sample
551 * will probably be a count referring
552 * to this -- but this one is still a
553 * part of the stream.
a1bb33af
UH
554 */
555 buffer = sample;
556 buflen = 4;
557 }
43fc7885
UH
558 } else {
559 /* No compression. */
a1bb33af
UH
560 buffer = sample;
561 buflen = 4;
562 }
563
43fc7885
UH
564 if (num_channels < 4) {
565 /*
566 * Some channel groups may have been turned
567 * off, to speed up transfer between the
568 * hardware and the PC. Expand that here before
569 * submitting it over the session bus --
570 * whatever is listening on the bus will be
571 * expecting a full 32-bit sample, based on
572 * the number of probes.
6937bb75
BV
573 */
574 j = 0;
575 memset(tmp_sample, 0, 4);
43fc7885 576 for (i = 0; i < 4; i++) {
a803c0db 577 if (((flag_reg >> 2) & (1 << i)) == 0) {
43fc7885
UH
578 /*
579 * This channel group was
580 * enabled, copy from received
581 * sample.
582 */
6937bb75
BV
583 tmp_sample[i] = sample[j++];
584 }
585 }
586 memcpy(sample, tmp_sample, 4);
e6ac9ac8 587 g_debug("ols: full sample 0x%.8x", (int) *sample);
6937bb75
BV
588 }
589
a803c0db
BV
590 /* the OLS sends its sample buffer backwards.
591 * store it in reverse order here, so we can dump
592 * this on the session bus later.
593 */
f0d1b53e 594 offset = (limit_samples - num_transfers / num_channels) * 4;
a803c0db
BV
595 memcpy(raw_sample_buf + offset, sample, 4);
596
43fc7885 597 if (buffer == sample)
6937bb75 598 memcpy(last_sample, buffer, num_channels);
a1bb33af
UH
599 else
600 g_free(buffer);
601
6937bb75 602 memset(sample, 0, 4);
a1bb33af
UH
603 num_bytes = 0;
604 }
43fc7885
UH
605 } else {
606 /*
607 * This is the main loop telling us a timeout was reached, or
608 * we've acquired all the samples we asked for -- we're done.
a803c0db 609 * Send the (properly-ordered) buffer to the frontend.
43fc7885 610 */
a803c0db
BV
611 if (trigger_at != -1) {
612 /* a trigger was set up, so we need to tell the frontend
613 * about it.
614 */
615 if (trigger_at > 0) {
616 /* there are pre-trigger samples, send those first */
5a2326a7 617 packet.type = SR_DF_LOGIC;
a803c0db 618 packet.length = trigger_at * 4;
4c046c6b 619 packet.unitsize = 4;
a803c0db 620 packet.payload = raw_sample_buf;
8a2efef2 621 sr_session_bus(user_data, &packet);
a803c0db
BV
622 }
623
5a2326a7 624 packet.type = SR_DF_TRIGGER;
a803c0db 625 packet.length = 0;
8a2efef2 626 sr_session_bus(user_data, &packet);
a803c0db 627
5a2326a7 628 packet.type = SR_DF_LOGIC;
a803c0db 629 packet.length = (limit_samples * 4) - (trigger_at * 4);
4c046c6b 630 packet.unitsize = 4;
a803c0db 631 packet.payload = raw_sample_buf + trigger_at * 4;
8a2efef2 632 sr_session_bus(user_data, &packet);
a803c0db 633 } else {
5a2326a7 634 packet.type = SR_DF_LOGIC;
a803c0db 635 packet.length = limit_samples * 4;
4c046c6b 636 packet.unitsize = 4;
a803c0db 637 packet.payload = raw_sample_buf;
8a2efef2 638 sr_session_bus(user_data, &packet);
a803c0db
BV
639 }
640 free(raw_sample_buf);
641
06d64eb8 642 serial_flush(fd);
d02a535e 643 serial_close(fd);
5a2326a7 644 packet.type = SR_DF_END;
a1bb33af 645 packet.length = 0;
8a2efef2 646 sr_session_bus(user_data, &packet);
a1bb33af
UH
647 }
648
649 return TRUE;
650}
651
a1bb33af
UH
652static int hw_start_acquisition(int device_index, gpointer session_device_id)
653{
43fc7885 654 int i;
b9c735a2
UH
655 struct sr_datafeed_packet *packet;
656 struct sr_datafeed_header *header;
a00ba012 657 struct sr_device_instance *sdi;
a803c0db 658 uint32_t trigger_config[4];
a1bb33af 659 uint32_t data;
6937bb75
BV
660 uint16_t readcount, delaycount;
661 uint8_t changrp_mask;
a1bb33af 662
d32d961d 663 if (!(sdi = sr_get_device_instance(device_instances, device_index)))
e46b8fb1 664 return SR_ERR;
a1bb33af 665
5a2326a7 666 if (sdi->status != SR_ST_ACTIVE)
e46b8fb1 667 return SR_ERR;
a1bb33af 668
a803c0db
BV
669 readcount = limit_samples / 4;
670
671 memset(trigger_config, 0, 16);
672 trigger_config[num_stages-1] |= 0x08;
43fc7885 673 if (trigger_mask[0]) {
a803c0db
BV
674 delaycount = readcount * (1 - capture_ratio / 100.0);
675 trigger_at = (readcount - delaycount) * 4 - num_stages;
a803c0db 676
43fc7885 677 if (send_longcommand(sdi->serial->fd, CMD_SET_TRIGGER_MASK_0,
e46b8fb1
UH
678 reverse32(trigger_mask[0])) != SR_OK)
679 return SR_ERR;
a803c0db 680 if (send_longcommand(sdi->serial->fd, CMD_SET_TRIGGER_VALUE_0,
e46b8fb1
UH
681 reverse32(trigger_value[0])) != SR_OK)
682 return SR_ERR;
a803c0db 683 if (send_longcommand(sdi->serial->fd, CMD_SET_TRIGGER_CONFIG_0,
e46b8fb1
UH
684 trigger_config[0]) != SR_OK)
685 return SR_ERR;
6937bb75 686
a803c0db 687 if (send_longcommand(sdi->serial->fd, CMD_SET_TRIGGER_MASK_1,
e46b8fb1
UH
688 reverse32(trigger_mask[1])) != SR_OK)
689 return SR_ERR;
43fc7885 690 if (send_longcommand(sdi->serial->fd, CMD_SET_TRIGGER_VALUE_1,
e46b8fb1
UH
691 reverse32(trigger_value[1])) != SR_OK)
692 return SR_ERR;
a803c0db 693 if (send_longcommand(sdi->serial->fd, CMD_SET_TRIGGER_CONFIG_1,
e46b8fb1
UH
694 trigger_config[1]) != SR_OK)
695 return SR_ERR;
6937bb75 696
a803c0db 697 if (send_longcommand(sdi->serial->fd, CMD_SET_TRIGGER_MASK_2,
e46b8fb1
UH
698 reverse32(trigger_mask[2])) != SR_OK)
699 return SR_ERR;
a803c0db 700 if (send_longcommand(sdi->serial->fd, CMD_SET_TRIGGER_VALUE_2,
e46b8fb1
UH
701 reverse32(trigger_value[2])) != SR_OK)
702 return SR_ERR;
43fc7885 703 if (send_longcommand(sdi->serial->fd, CMD_SET_TRIGGER_CONFIG_2,
e46b8fb1
UH
704 trigger_config[2]) != SR_OK)
705 return SR_ERR;
a803c0db
BV
706
707 if (send_longcommand(sdi->serial->fd, CMD_SET_TRIGGER_MASK_3,
e46b8fb1
UH
708 reverse32(trigger_mask[3])) != SR_OK)
709 return SR_ERR;
a803c0db 710 if (send_longcommand(sdi->serial->fd, CMD_SET_TRIGGER_VALUE_3,
e46b8fb1
UH
711 reverse32(trigger_value[3])) != SR_OK)
712 return SR_ERR;
43fc7885 713 if (send_longcommand(sdi->serial->fd, CMD_SET_TRIGGER_CONFIG_3,
e46b8fb1
UH
714 trigger_config[3]) != SR_OK)
715 return SR_ERR;
6937bb75 716 } else {
43fc7885 717 if (send_longcommand(sdi->serial->fd, CMD_SET_TRIGGER_MASK_0,
e46b8fb1
UH
718 trigger_mask[0]) != SR_OK)
719 return SR_ERR;
43fc7885 720 if (send_longcommand(sdi->serial->fd, CMD_SET_TRIGGER_VALUE_0,
e46b8fb1
UH
721 trigger_value[0]) != SR_OK)
722 return SR_ERR;
43fc7885 723 if (send_longcommand(sdi->serial->fd, CMD_SET_TRIGGER_CONFIG_0,
e46b8fb1
UH
724 0x00000008) != SR_OK)
725 return SR_ERR;
a803c0db 726 delaycount = readcount;
6937bb75 727 }
a1bb33af 728
6937bb75 729 set_configuration_samplerate(sdi, cur_samplerate);
a1bb33af 730
43fc7885 731 /* Send sample limit and pre/post-trigger capture ratio. */
a803c0db
BV
732 data = ((readcount - 1) & 0xffff) << 16;
733 data |= (delaycount - 1) & 0xffff;
e46b8fb1
UH
734 if (send_longcommand(sdi->serial->fd, CMD_CAPTURE_SIZE, reverse16(data)) != SR_OK)
735 return SR_ERR;
a1bb33af 736
43fc7885
UH
737 /*
738 * Enable/disable channel groups in the flag register according to the
a803c0db 739 * probe mask.
6937bb75
BV
740 */
741 changrp_mask = 0;
43fc7885
UH
742 for (i = 0; i < 4; i++) {
743 if (probe_mask & (0xff << (i * 8)))
a803c0db 744 changrp_mask |= (1 << i);
6937bb75 745 }
43fc7885
UH
746
747 /* The flag register wants them here, and 1 means "disable channel". */
6937bb75 748 flag_reg |= ~(changrp_mask << 2) & 0x3c;
a803c0db 749 flag_reg |= FLAG_FILTER;
6937bb75 750 data = flag_reg << 24;
e46b8fb1
UH
751 if (send_longcommand(sdi->serial->fd, CMD_SET_FLAGS, data) != SR_OK)
752 return SR_ERR;
a1bb33af 753
43fc7885 754 /* Start acquisition on the device. */
e46b8fb1
UH
755 if (send_shortcommand(sdi->serial->fd, CMD_RUN) != SR_OK)
756 return SR_ERR;
a1bb33af 757
6f1be0a2
UH
758 sr_source_add(sdi->serial->fd, G_IO_IN, -1, receive_data,
759 session_device_id);
a1bb33af 760
43fc7885 761 /* Send header packet to the session bus. */
b9c735a2
UH
762 packet = g_malloc(sizeof(struct sr_datafeed_packet));
763 header = g_malloc(sizeof(struct sr_datafeed_header));
43fc7885 764 if (!packet || !header)
e46b8fb1 765 return SR_ERR;
5a2326a7 766 packet->type = SR_DF_HEADER;
b9c735a2 767 packet->length = sizeof(struct sr_datafeed_header);
43fc7885 768 packet->payload = (unsigned char *)header;
a1bb33af
UH
769 header->feed_version = 1;
770 gettimeofday(&header->starttime, NULL);
4c100f32 771 header->samplerate = cur_samplerate;
5a2326a7 772 header->protocol_id = SR_PROTO_RAW;
c2616fb9
DR
773 header->num_logic_probes = NUM_PROBES;
774 header->num_analog_probes = 0;
8a2efef2 775 sr_session_bus(session_device_id, packet);
a1bb33af
UH
776 g_free(header);
777 g_free(packet);
778
e46b8fb1 779 return SR_OK;
a1bb33af
UH
780}
781
a1bb33af
UH
782static void hw_stop_acquisition(int device_index, gpointer session_device_id)
783{
b9c735a2 784 struct sr_datafeed_packet packet;
a1bb33af 785
17e1afcb 786 /* Avoid compiler warnings. */
afc8e4de
UH
787 device_index = device_index;
788
5a2326a7 789 packet.type = SR_DF_END;
a1bb33af 790 packet.length = 0;
8a2efef2 791 sr_session_bus(session_device_id, &packet);
a1bb33af
UH
792}
793
5c2d46d1 794struct sr_device_plugin ols_plugin_info = {
e6ac9ac8 795 "ols",
9f8274a5 796 "Openbench Logic Sniffer",
a1bb33af
UH
797 1,
798 hw_init,
799 hw_cleanup,
a1bb33af
UH
800 hw_opendev,
801 hw_closedev,
802 hw_get_device_info,
803 hw_get_status,
804 hw_get_capabilities,
805 hw_set_configuration,
806 hw_start_acquisition,
43fc7885 807 hw_stop_acquisition,
a1bb33af 808};