#include <extdef.h>
-#include <assert.h>
-#include <string.h>
-#include <stdlib.h>
+#include <cassert>
+#include <cstring>
+#include <cstdlib>
#include <cmath>
#include "logic.hpp"
using std::min;
using std::pair;
using std::shared_ptr;
+using std::vector;
using sigrok::Logic;
return get_raw_samples(start_sample, (end_sample-start_sample));
}
-SegmentLogicDataIterator* LogicSegment::begin_sample_iteration(uint64_t start) const
+SegmentLogicDataIterator* LogicSegment::begin_sample_iteration(uint64_t start)
{
return (SegmentLogicDataIterator*)begin_raw_sample_iteration(start);
}
-void LogicSegment::continue_sample_iteration(SegmentLogicDataIterator* it, uint64_t increase) const
+void LogicSegment::continue_sample_iteration(SegmentLogicDataIterator* it, uint64_t increase)
{
Segment::continue_raw_sample_iteration((SegmentRawDataIterator*)it, increase);
}
-void LogicSegment::end_sample_iteration(SegmentLogicDataIterator* it) const
+void LogicSegment::end_sample_iteration(SegmentLogicDataIterator* it)
{
Segment::end_raw_sample_iteration((SegmentRawDataIterator*)it);
}
}
void LogicSegment::get_subsampled_edges(
- std::vector<EdgePair> &edges,
+ vector<EdgePair> &edges,
uint64_t start, uint64_t end,
float min_length, int sig_index)
{
// Store the initial state
last_sample = (get_unpacked_sample(start) & sig_mask) != 0;
- edges.push_back(pair<int64_t, bool>(index++, last_sample));
+ edges.emplace_back(index++, last_sample);
while (index + block_length <= end) {
//----- Continue to search -----//
// Slide right and zoom out at the beginnings of mip-map
// blocks until we encounter a change
- while (1) {
+ while (true) {
const int level_scale_power =
(level + 1) * MipMapScalePower;
const uint64_t offset =
// Zoom in, and slide right until we encounter a change,
// and repeat until we reach min_level
- while (1) {
+ while (true) {
assert(mip_map_[level].data);
const int level_scale_power =
// Store the final state
const bool final_sample =
(get_unpacked_sample(final_index - 1) & sig_mask) != 0;
- edges.push_back(pair<int64_t, bool>(index, final_sample));
+ edges.emplace_back(index, final_sample);
index = final_index;
last_sample = final_sample;
// Add the final state
const bool end_sample = get_unpacked_sample(end) & sig_mask;
if (last_sample != end_sample)
- edges.push_back(pair<int64_t, bool>(end, end_sample));
- edges.push_back(pair<int64_t, bool>(end + 1, end_sample));
+ edges.emplace_back(end, end_sample);
+ edges.emplace_back(end + 1, end_sample);
}
uint64_t LogicSegment::get_subsample(int level, uint64_t offset) const