1 -------------------------------------------------------------------------------
2 Arbitrary LPC (low pin count) traffic
3 -------------------------------------------------------------------------------
5 These captures are the identification and programming with random data of a LPC
6 (low pin count) interface flash chip. The LPC bus is emulated with an ARM
7 Cortex-M microcontroller, and does not run at the standard 33MHz clock. Although
8 the clock contains significant jitter, the connected chips respond and
9 communicate as expected.
12 http://en.wikipedia.org/wiki/Low_Pin_Count
13 http://www.intel.com/design/chipsets/industry/25128901.pdf
19 A VultureProg daughterboard was attached to a TI Stellaris Launcphad board. A
20 SST49LF080A flash chip was installed in the PLCC socket. The core clock of the
21 CPU was reduced from 80MHz to 16MHz to permit the logic analyzer to capture all
22 details of the waveform.
24 Hardware: http://github.com/mrnuke/vultureprog-hardware
25 Firmware + SW: http://git.qiprog.org/
27 The logic analyzer used was a MCU123 USBee AX Pro clone. It was connected to the
28 "LPC probe" header of the VultureProg daughterboard. All captures were run at
46 VultureProg BIOS chip programmer programming random data to a SST49LF080A.
47 The bus clock was intentionally reduced to allow capture with an FX2-based
50 This data is released into the public domain.