[sigrok-dumps.git] / lpc / README

-------------------------------------------------------------------------------
Arbitrary LPC (low pin count) traffic
-------------------------------------------------------------------------------

These captures are the identification and programming with random data of a LPC
(low pin count) interface flash chip. The LPC bus is emulated with an ARM
Cortex-M microcontroller, and does not run at the standard 33MHz clock. Although
the clock contains significant jitter, the connected chips respond and
communicate as expected.

Details:
http://en.wikipedia.org/wiki/Low_Pin_Count
http://www.intel.com/design/chipsets/industry/25128901.pdf


Hardware Setup
--------------

A VultureProg daughterboard was attached to a TI Stellaris Launcphad board. A
SST49LF080A flash chip was installed in the PLCC socket. The core clock of the
CPU was reduced from 80MHz to 16MHz to permit the logic analyzer to capture all
details of the waveform.

Hardware: http://github.com/mrnuke/vultureprog-hardware
Firmware + SW: http://git.qiprog.org/

The logic analyzer used was a MCU123 USBee AX Pro clone. It was connected to the
"LPC probe" header of the VultureProg daughterboard. All captures were run at
24MHz sampling rate.

Hookup
------
P0: LAD0
P1: LAD1
P2: LAD2
P3: LAD3
P4: LCLK
P5: #LFRAME
P6: NC
P7: NC

Data
----

- lpc_vultureprog.sr
  VultureProg BIOS chip programmer programming random data to a SST49LF080A.
  The bus clock was intentionally reduced to allow capture with an FX2-based
  logic analyzer.

This data is released into the public domain.
Commit	Line	Data
e06e8eca AG	1	-------------------------------------------------------------------------------
	2	Arbitrary LPC (low pin count) traffic
	3	-------------------------------------------------------------------------------
	4
	5	These captures are the identification and programming with random data of a LPC
	6	(low pin count) interface flash chip. The LPC bus is emulated with an ARM
	7	Cortex-M microcontroller, and does not run at the standard 33MHz clock. Although
	8	the clock contains significant jitter, the connected chips respond and
	9	communicate as expected.
	10
	11	Details:
	12	http://en.wikipedia.org/wiki/Low_Pin_Count
	13	http://www.intel.com/design/chipsets/industry/25128901.pdf
	14
	15
	16	Hardware Setup
	17	--------------
	18
	19	A VultureProg daughterboard was attached to a TI Stellaris Launcphad board. A
	20	SST49LF080A flash chip was installed in the PLCC socket. The core clock of the
	21	CPU was reduced from 80MHz to 16MHz to permit the logic analyzer to capture all
	22	details of the waveform.
	23
	24	Hardware: http://github.com/mrnuke/vultureprog-hardware
	25	Firmware + SW: http://git.qiprog.org/
	26
	27	The logic analyzer used was a MCU123 USBee AX Pro clone. It was connected to the
	28	"LPC probe" header of the VultureProg daughterboard. All captures were run at
	29	24MHz sampling rate.
	30
	31	Hookup
	32	------
	33	P0: LAD0
	34	P1: LAD1
	35	P2: LAD2
	36	P3: LAD3
	37	P4: LCLK
	38	P5: #LFRAME
	39	P6: NC
	40	P7: NC
	41
	42	Data
	43	----
	44
	45	- lpc_vultureprog.sr
	46	VultureProg BIOS chip programmer programming random data to a SST49LF080A.
	47	The bus clock was intentionally reduced to allow capture with an FX2-based
	48	logic analyzer.
	49
	50	This data is released into the public domain.