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1 | ## | |
2 | ## This file is part of the libsigrokdecode project. | |
3 | ## | |
4 | ## Copyright (C) 2012 Uwe Hermann <uwe@hermann-uwe.de> | |
5 | ## | |
6 | ## This program is free software; you can redistribute it and/or modify | |
7 | ## it under the terms of the GNU General Public License as published by | |
8 | ## the Free Software Foundation; either version 2 of the License, or | |
9 | ## (at your option) any later version. | |
10 | ## | |
11 | ## This program is distributed in the hope that it will be useful, | |
12 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | ## GNU General Public License for more details. | |
15 | ## | |
16 | ## You should have received a copy of the GNU General Public License | |
17 | ## along with this program; if not, write to the Free Software | |
18 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
19 | ## | |
20 | ||
21 | # Texas Instruments TLC5620 protocol decoder | |
22 | ||
23 | import sigrokdecode as srd | |
24 | ||
25 | dacs = { | |
26 | 0: 'DACA', | |
27 | 1: 'DACB', | |
28 | 2: 'DACC', | |
29 | 3: 'DACD', | |
30 | } | |
31 | ||
32 | class Decoder(srd.Decoder): | |
33 | api_version = 1 | |
34 | id = 'tlc5620' | |
35 | name = 'TI TLC5620' | |
36 | longname = 'Texas Instruments TLC5620' | |
37 | desc = 'Texas Instruments TLC5620 8-bit quad DAC.' | |
38 | license = 'gplv2+' | |
39 | inputs = ['logic'] | |
40 | outputs = ['tlc5620'] | |
41 | probes = [ | |
42 | {'id': 'clk', 'name': 'CLK', 'desc': 'Serial interface clock'}, | |
43 | {'id': 'data', 'name': 'DATA', 'desc': 'Serial interface data'}, | |
44 | ] | |
45 | optional_probes = [ | |
46 | {'id': 'load', 'name': 'LOAD', 'desc': 'Serial interface load control'}, | |
47 | {'id': 'ldac', 'name': 'LDAC', 'desc': 'Load DAC'}, | |
48 | ] | |
49 | options = {} | |
50 | annotations = [ | |
51 | ['dac_select', 'DAC select'], | |
52 | ['gain', 'Gain'], | |
53 | ['value', 'DAC value'], | |
54 | ['data_latch', 'Data latch point'], | |
55 | ['ldac_fall', 'LDAC falling edge'], | |
56 | ] | |
57 | ||
58 | def __init__(self, **kwargs): | |
59 | self.oldpins = self.oldclk = self.oldload = self.oldldac = None | |
60 | self.datapin = None | |
61 | self.bits = [] | |
62 | self.ss_dac = self.es_dac = 0 | |
63 | self.ss_gain = self.es_gain = 0 | |
64 | self.ss_value = self.es_value = 0 | |
65 | self.dac_select = self.gain = self.dac_value = None | |
66 | ||
67 | def start(self): | |
68 | # self.out_proto = self.register(srd.OUTPUT_PYTHON) | |
69 | self.out_ann = self.register(srd.OUTPUT_ANN) | |
70 | ||
71 | def handle_11bits(self): | |
72 | s = "".join(str(i) for i in self.bits[:2]) | |
73 | self.dac_select = s = dacs[int(s, 2)] | |
74 | self.put(self.ss_dac, self.es_dac, self.out_ann, | |
75 | [0, ['DAC select: %s' % s, 'DAC sel: %s' % s, | |
76 | 'DAC: %s' % s, 'D: %s' % s, s, s[3]]]) | |
77 | ||
78 | self.gain = g = 1 + self.bits[2] | |
79 | self.put(self.ss_gain, self.es_gain, self.out_ann, | |
80 | [1, ['Gain: x%d' % g, 'G: x%d' % g, 'x%d' % g]]) | |
81 | ||
82 | s = "".join(str(i) for i in self.bits[3:]) | |
83 | self.dac_value = v = int(s, 2) | |
84 | self.put(self.ss_value, self.es_value, self.out_ann, | |
85 | [2, ['DAC value: %d' % v, 'Value: %d' % v, 'Val: %d' % v, | |
86 | 'V: %d' % v, '%d' % v]]) | |
87 | ||
88 | def handle_falling_edge_load(self): | |
89 | s, v, g = self.dac_select, self.dac_value, self.gain | |
90 | self.put(self.samplenum, self.samplenum, self.out_ann, | |
91 | [3, ['Setting %s value to %d (x%d gain)' % (s, v, g), | |
92 | '%s=%d (x%d gain)' % (s, v, g)]]) | |
93 | ||
94 | def handle_falling_edge_ldac(self): | |
95 | self.put(self.samplenum, self.samplenum, self.out_ann, | |
96 | [4, ['Falling edge on LDAC pin', 'LDAC fall', 'LDAC']]) | |
97 | ||
98 | def handle_new_dac_bit(self): | |
99 | self.bits.append(self.datapin) | |
100 | ||
101 | # Wait until we have read 11 bits, then parse them. | |
102 | l, s = len(self.bits), self.samplenum | |
103 | if l == 1: | |
104 | self.ss_dac = s | |
105 | elif l == 2: | |
106 | self.es_dac = self.ss_gain = s | |
107 | elif l == 3: | |
108 | self.es_gain = self.ss_value = s | |
109 | elif l == 11: | |
110 | self.es_value = s | |
111 | self.handle_11bits() | |
112 | self.bits = [] | |
113 | ||
114 | def decode(self, ss, es, data): | |
115 | for (self.samplenum, pins) in data: | |
116 | ||
117 | # Ignore identical samples early on (for performance reasons). | |
118 | if self.oldpins == pins: | |
119 | continue | |
120 | self.oldpins, (clk, self.datapin, load, ldac) = pins, pins | |
121 | ||
122 | # DATA is shifted in the DAC on the falling CLK edge (MSB-first). | |
123 | # A falling edge of LOAD will latch the data. | |
124 | ||
125 | if self.oldload == 1 and load == 0: | |
126 | self.handle_falling_edge_load() | |
127 | if self.oldldac == 1 and ldac == 0: | |
128 | self.handle_falling_edge_ldac() | |
129 | if self.oldclk == 1 and clk == 0: | |
130 | self.handle_new_dac_bit() | |
131 | ||
132 | self.oldclk = clk | |
133 | self.oldload = load | |
134 | self.oldldac = ldac | |
135 |