]>
Commit | Line | Data |
---|---|---|
1 | ## | |
2 | ## This file is part of the libsigrokdecode project. | |
3 | ## | |
4 | ## Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz> | |
5 | ## Copyright (C) 2012-2013 Uwe Hermann <uwe@hermann-uwe.de> | |
6 | ## | |
7 | ## This program is free software; you can redistribute it and/or modify | |
8 | ## it under the terms of the GNU General Public License as published by | |
9 | ## the Free Software Foundation; either version 2 of the License, or | |
10 | ## (at your option) any later version. | |
11 | ## | |
12 | ## This program is distributed in the hope that it will be useful, | |
13 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | ## GNU General Public License for more details. | |
16 | ## | |
17 | ## You should have received a copy of the GNU General Public License | |
18 | ## along with this program; if not, write to the Free Software | |
19 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
20 | ## | |
21 | ||
22 | # SPI protocol decoder | |
23 | ||
24 | import sigrokdecode as srd | |
25 | ||
26 | ''' | |
27 | Protocol output format: | |
28 | ||
29 | SPI packet: | |
30 | [<cmd>, <data1>, <data2>] | |
31 | ||
32 | Commands: | |
33 | - 'DATA': <data1> contains the MISO data, <data2> contains the MOSI data. | |
34 | The data is _usually_ 8 bits (but can also be fewer or more bits). | |
35 | Both data items are Python numbers, not strings. | |
36 | - 'CS CHANGE': <data1> is the old CS# pin value, <data2> is the new value. | |
37 | Both data items are Python numbers (0/1), not strings. | |
38 | ||
39 | Examples: | |
40 | ['CS-CHANGE', 1, 0] | |
41 | ['DATA', 0xff, 0x3a] | |
42 | ['DATA', 0x65, 0x00] | |
43 | ['CS-CHANGE', 0, 1] | |
44 | ''' | |
45 | ||
46 | # Key: (CPOL, CPHA). Value: SPI mode. | |
47 | # Clock polarity (CPOL) = 0/1: Clock is low/high when inactive. | |
48 | # Clock phase (CPHA) = 0/1: Data is valid on the leading/trailing clock edge. | |
49 | spi_mode = { | |
50 | (0, 0): 0, # Mode 0 | |
51 | (0, 1): 1, # Mode 1 | |
52 | (1, 0): 2, # Mode 2 | |
53 | (1, 1): 3, # Mode 3 | |
54 | } | |
55 | ||
56 | class Decoder(srd.Decoder): | |
57 | api_version = 1 | |
58 | id = 'spi' | |
59 | name = 'SPI' | |
60 | longname = 'Serial Peripheral Interface' | |
61 | desc = 'Full-duplex, synchronous, serial bus.' | |
62 | license = 'gplv2+' | |
63 | inputs = ['logic'] | |
64 | outputs = ['spi'] | |
65 | probes = [ | |
66 | {'id': 'miso', 'name': 'MISO', | |
67 | 'desc': 'SPI MISO line (Master in, slave out)'}, | |
68 | {'id': 'mosi', 'name': 'MOSI', | |
69 | 'desc': 'SPI MOSI line (Master out, slave in)'}, | |
70 | {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'}, | |
71 | ] | |
72 | optional_probes = [ | |
73 | {'id': 'cs', 'name': 'CS#', 'desc': 'SPI chip-select line'}, | |
74 | ] | |
75 | options = { | |
76 | 'cs_polarity': ['CS# polarity', 'active-low'], | |
77 | 'cpol': ['Clock polarity', 0], | |
78 | 'cpha': ['Clock phase', 0], | |
79 | 'bitorder': ['Bit order within the SPI data', 'msb-first'], | |
80 | 'wordsize': ['Word size of SPI data', 8], # 1-64? | |
81 | 'format': ['Data format', 'hex'], | |
82 | } | |
83 | annotations = [ | |
84 | ['MISO/MOSI data', 'MISO/MOSI SPI data'], | |
85 | ['MISO data', 'MISO SPI data'], | |
86 | ['MOSI data', 'MOSI SPI data'], | |
87 | ['Warnings', 'Human-readable warnings'], | |
88 | ] | |
89 | ||
90 | def __init__(self): | |
91 | self.samplerate = None | |
92 | self.oldsck = 1 | |
93 | self.bitcount = 0 | |
94 | self.mosidata = 0 | |
95 | self.misodata = 0 | |
96 | self.startsample = -1 | |
97 | self.samplenum = -1 | |
98 | self.cs_was_deasserted_during_data_word = 0 | |
99 | self.oldcs = -1 | |
100 | self.oldpins = None | |
101 | self.state = 'IDLE' | |
102 | ||
103 | def metadata(self, key, value): | |
104 | if key == srd.SRD_CONF_SAMPLERATE: | |
105 | self.samplerate = value | |
106 | ||
107 | def start(self): | |
108 | self.out_proto = self.register(srd.OUTPUT_PYTHON) | |
109 | self.out_ann = self.register(srd.OUTPUT_ANN) | |
110 | self.out_bitrate = self.register(srd.OUTPUT_META, | |
111 | meta=(int, 'Bitrate', 'Bitrate during transfers')) | |
112 | ||
113 | def putpw(self, data): | |
114 | self.put(self.startsample, self.samplenum, self.out_proto, data) | |
115 | ||
116 | def putw(self, data): | |
117 | self.put(self.startsample, self.samplenum, self.out_ann, data) | |
118 | ||
119 | def handle_bit(self, miso, mosi, sck, cs): | |
120 | # If this is the first bit, save its sample number. | |
121 | if self.bitcount == 0: | |
122 | self.startsample = self.samplenum | |
123 | if self.have_cs: | |
124 | active_low = (self.options['cs_polarity'] == 'active-low') | |
125 | deasserted = cs if active_low else not cs | |
126 | if deasserted: | |
127 | self.cs_was_deasserted_during_data_word = 1 | |
128 | ||
129 | ws = self.options['wordsize'] | |
130 | ||
131 | # Receive MOSI bit into our shift register. | |
132 | if self.options['bitorder'] == 'msb-first': | |
133 | self.mosidata |= mosi << (ws - 1 - self.bitcount) | |
134 | else: | |
135 | self.mosidata |= mosi << self.bitcount | |
136 | ||
137 | # Receive MISO bit into our shift register. | |
138 | if self.options['bitorder'] == 'msb-first': | |
139 | self.misodata |= miso << (ws - 1 - self.bitcount) | |
140 | else: | |
141 | self.misodata |= miso << self.bitcount | |
142 | ||
143 | self.bitcount += 1 | |
144 | ||
145 | # Continue to receive if not enough bits were received, yet. | |
146 | if self.bitcount != ws: | |
147 | return | |
148 | ||
149 | # Pass MOSI and MISO to the next PD up the stack | |
150 | self.putpw(['DATA', self.mosidata, self.misodata]) | |
151 | ||
152 | # Annotations | |
153 | self.putw([0, ['%02X/%02X' % (self.mosidata, self.misodata)]]) | |
154 | self.putw([1, ['%02X' % self.misodata]]) | |
155 | self.putw([2, ['%02X' % self.mosidata]]) | |
156 | ||
157 | # Meta bitrate | |
158 | elapsed = 1 / float(self.samplerate) * (self.samplenum - self.startsample + 1) | |
159 | bitrate = int(1 / elapsed * self.options['wordsize']) | |
160 | self.put(self.startsample, self.samplenum, self.out_bitrate, bitrate) | |
161 | ||
162 | if self.cs_was_deasserted_during_data_word: | |
163 | self.putw([3, ['CS# was deasserted during this data word!']]) | |
164 | ||
165 | # Reset decoder state. | |
166 | self.mosidata = self.misodata = self.bitcount = 0 | |
167 | ||
168 | def find_clk_edge(self, miso, mosi, sck, cs): | |
169 | if self.have_cs and self.oldcs != cs: | |
170 | # Send all CS# pin value changes. | |
171 | self.put(self.samplenum, self.samplenum, self.out_proto, | |
172 | ['CS-CHANGE', self.oldcs, cs]) | |
173 | self.oldcs = cs | |
174 | # Reset decoder state when CS# changes (and the CS# pin is used). | |
175 | self.mosidata = self.misodata = self.bitcount= 0 | |
176 | ||
177 | # Ignore sample if the clock pin hasn't changed. | |
178 | if sck == self.oldsck: | |
179 | return | |
180 | ||
181 | self.oldsck = sck | |
182 | ||
183 | # Sample data on rising/falling clock edge (depends on mode). | |
184 | mode = spi_mode[self.options['cpol'], self.options['cpha']] | |
185 | if mode == 0 and sck == 0: # Sample on rising clock edge | |
186 | return | |
187 | elif mode == 1 and sck == 1: # Sample on falling clock edge | |
188 | return | |
189 | elif mode == 2 and sck == 1: # Sample on falling clock edge | |
190 | return | |
191 | elif mode == 3 and sck == 0: # Sample on rising clock edge | |
192 | return | |
193 | ||
194 | # Found the correct clock edge, now get the SPI bit(s). | |
195 | self.handle_bit(miso, mosi, sck, cs) | |
196 | ||
197 | def decode(self, ss, es, data): | |
198 | if self.samplerate is None: | |
199 | raise Exception("Cannot decode without samplerate.") | |
200 | # TODO: Either MISO or MOSI could be optional. CS# is optional. | |
201 | for (self.samplenum, pins) in data: | |
202 | ||
203 | # Ignore identical samples early on (for performance reasons). | |
204 | if self.oldpins == pins: | |
205 | continue | |
206 | self.oldpins, (miso, mosi, sck, cs) = pins, pins | |
207 | self.have_cs = (cs in (0, 1)) | |
208 | ||
209 | # State machine. | |
210 | if self.state == 'IDLE': | |
211 | self.find_clk_edge(miso, mosi, sck, cs) | |
212 | else: | |
213 | raise Exception('Invalid state: %s' % self.state) | |
214 |