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Commit | Line | Data |
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1 | test incremental_8ch_short_noclock | |
2 | protocol-decoder parallel channel d0=0 channel d1=1 channel d2=2 channel d3=3 channel d4=4 channel d5=5 channel d6=6 channel d7=7 initial_pin d0=0 initial_pin d1=1 initial_pin d2=2 | |
3 | input misc/demo/incremental_8ch_short.sr | |
4 | output parallel annotation match incremental_8ch_short_noclock.output | |
5 | output parallel python match incremental_8ch_short_noclock.python | |
6 | ||
7 | test incremental_8ch_short_clock | |
8 | protocol-decoder parallel channel clk=0 channel d0=0 channel d1=1 channel d2=2 channel d3=3 channel d4=4 channel d5=5 channel d6=6 channel d7=7 | |
9 | input misc/demo/incremental_8ch_short.sr | |
10 | output parallel annotation match incremental_8ch_short_clock.output | |
11 | output parallel python match incremental_8ch_short_clock.python | |
12 | ||
13 | test incremental_8ch_long_noclock | |
14 | protocol-decoder parallel channel d0=0 channel d1=1 channel d2=2 channel d3=3 channel d4=4 channel d5=5 channel d6=6 channel d7=7 initial_pin d0=0 initial_pin d1=1 initial_pin d2=2 | |
15 | input misc/demo/incremental_8ch_long.sr | |
16 | output parallel annotation match incremental_8ch_long_noclock.output | |
17 | output parallel python match incremental_8ch_long_noclock.python | |
18 | ||
19 | test incremental_8ch_long_clock | |
20 | protocol-decoder parallel channel clk=0 channel d0=0 channel d1=1 channel d2=2 channel d3=3 channel d4=4 channel d5=5 channel d6=6 channel d7=7 | |
21 | input misc/demo/incremental_8ch_long.sr | |
22 | output parallel annotation match incremental_8ch_long_clock.output | |
23 | output parallel python match incremental_8ch_long_clock.python | |
24 | ||
25 | test hd44780_word_demux | |
26 | protocol-decoder parallel channel clk=3 channel d0=4 channel d1=5 channel d2=6 channel d3=7 option clock_edge=falling option wordsize=2 option endianness=big | |
27 | input display/hd44780/hd44780-reset-init-hello.sr | |
28 | output parallel annotation match hd44780_word_demux.output |