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rigol-ds: properly set encoding digits
[libsigrok.git] / src / hardware / rigol-ds / api.c
CommitLineData
f4816ac6
ML		 1/*
2 * This file is part of the libsigrok project.
3 *
4 * Copyright (C) 2012 Martin Ling <martin-git@earth.li>
88e429c9 5 * Copyright (C) 2013 Bert Vermeulen <bert@biot.com>
bafd4890 6 * Copyright (C) 2013 Mathias Grimmberger <mgri@zaphod.sax.de>
f4816ac6
ML		 7 *
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation, either version 3 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
6ec6c43b 22#include <config.h>
e0b7d23c
ML		 23#include <fcntl.h>
24#include <unistd.h>
25#include <stdlib.h>
26#include <string.h>
ba464a12 27#include <strings.h>
2b0e4a46 28#include <math.h>
f4816ac6 29#include <glib.h>
c1aae900 30#include <libsigrok/libsigrok.h>
f4816ac6 31#include "libsigrok-internal.h"
5a1afc09 32#include "scpi.h"
f4816ac6
ML		 33#include "protocol.h"
34
a0e0bb41 35static const uint32_t scanopts[] = {
ca55277c 36 SR_CONF_CONN,
0dc7b43e 37 SR_CONF_SERIALCOMM
ca55277c
ML		 38};
39
f254bc4b 40static const uint32_t devopts[] = {
1953564a 41 SR_CONF_OSCILLOSCOPE,
5827f61b
BV		 42 SR_CONF_LIMIT_FRAMES | SR_CONF_SET,
43 SR_CONF_TIMEBASE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
44 SR_CONF_TRIGGER_SOURCE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
b0c9d1d1 45 SR_CONF_TRIGGER_SLOPE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
9ea62f2e 46 SR_CONF_TRIGGER_LEVEL | SR_CONF_GET | SR_CONF_SET,
5827f61b 47 SR_CONF_HORIZ_TRIGGERPOS | SR_CONF_SET,
bf622e6d 48 SR_CONF_NUM_HDIV | SR_CONF_GET,
5827f61b 49 SR_CONF_SAMPLERATE | SR_CONF_GET,
f579d08b 50 SR_CONF_DATA_SOURCE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
f48e0249
ML		 51};
52
f254bc4b 53static const uint32_t analog_devopts[] = {
5827f61b
BV		 54 SR_CONF_NUM_VDIV | SR_CONF_GET,
55 SR_CONF_VDIV | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
56 SR_CONF_COUPLING | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
934cf6cf 57 SR_CONF_PROBE_FACTOR | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
e0b7d23c
ML		 58};
59
f6a0ac9f 60static const uint64_t timebases[][2] = {
e0b7d23c 61 /* nanoseconds */
8e06edf5 62 { 1, 1000000000 },
e0b7d23c
ML		 63 { 2, 1000000000 },
64 { 5, 1000000000 },
65 { 10, 1000000000 },
66 { 20, 1000000000 },
67 { 50, 1000000000 },
68 { 100, 1000000000 },
69 { 500, 1000000000 },
70 /* microseconds */
71 { 1, 1000000 },
72 { 2, 1000000 },
73 { 5, 1000000 },
74 { 10, 1000000 },
75 { 20, 1000000 },
76 { 50, 1000000 },
77 { 100, 1000000 },
78 { 200, 1000000 },
79 { 500, 1000000 },
80 /* milliseconds */
81 { 1, 1000 },
82 { 2, 1000 },
83 { 5, 1000 },
84 { 10, 1000 },
85 { 20, 1000 },
86 { 50, 1000 },
87 { 100, 1000 },
88 { 200, 1000 },
89 { 500, 1000 },
90 /* seconds */
91 { 1, 1 },
92 { 2, 1 },
93 { 5, 1 },
94 { 10, 1 },
95 { 20, 1 },
96 { 50, 1 },
bafd4890
ML		 97 { 100, 1 },
98 { 200, 1 },
99 { 500, 1 },
8e06edf5 100 { 1000, 1 },
e0b7d23c
ML		 101};
102
f6a0ac9f 103static const uint64_t vdivs[][2] = {
bafd4890
ML		 104 /* microvolts */
105 { 500, 1000000 },
e0b7d23c 106 /* millivolts */
bafd4890 107 { 1, 1000 },
e0b7d23c
ML		 108 { 2, 1000 },
109 { 5, 1000 },
110 { 10, 1000 },
111 { 20, 1000 },
112 { 50, 1000 },
113 { 100, 1000 },
114 { 200, 1000 },
115 { 500, 1000 },
116 /* volts */
117 { 1, 1 },
118 { 2, 1 },
119 { 5, 1 },
120 { 10, 1 },
d50725e0
UH		 121 { 20, 1 },
122 { 50, 1 },
123 { 100, 1 },
e0b7d23c
ML		 124};
125
bafd4890
ML		 126#define NUM_TIMEBASE ARRAY_SIZE(timebases)
127#define NUM_VDIV ARRAY_SIZE(vdivs)
128
e0b7d23c
ML		 129static const char *trigger_sources[] = {
130 "CH1",
131 "CH2",
821fbcad
ML		 132 "CH3",
133 "CH4",
e0b7d23c
ML		 134 "EXT",
135 "AC Line",
6bb192bc
ML		 136 "D0",
137 "D1",
138 "D2",
139 "D3",
140 "D4",
141 "D5",
142 "D6",
143 "D7",
144 "D8",
145 "D9",
146 "D10",
147 "D11",
148 "D12",
149 "D13",
150 "D14",
151 "D15",
e0b7d23c
ML		 152};
153
5d336f11
AJ		 154static const char *trigger_slopes[] = {
155 "r",
156 "f",
157};
158
e0b7d23c
ML		 159static const char *coupling[] = {
160 "AC",
161 "DC",
162 "GND",
e0b7d23c
ML		 163};
164
934cf6cf
AJ		 165static const uint64_t probe_factor[] = {
166 1,
167 2,
168 5,
169 10,
170 20,
171 50,
172 100,
173 200,
174 500,
175 1000,
176};
177
babab622
ML		 178/* Do not change the order of entries */
179static const char *data_sources[] = {
180 "Live",
181 "Memory",
182 "Segmented",
183};
184
569d4dbd
ML		 185enum vendor {
186 RIGOL,
187 AGILENT,
188};
189
190enum series {
191 VS5000,
192 DS1000,
193 DS2000,
194 DS2000A,
195 DSO1000,
702f42e8 196 DS1000Z,
569d4dbd 197};
10afee13 198
569d4dbd
ML		 199/* short name, full name */
200static const struct rigol_ds_vendor supported_vendors[] = {
201 [RIGOL] = {"Rigol", "Rigol Technologies"},
14e1aa6d 202 [AGILENT] = {"Agilent", "Agilent Technologies"},
569d4dbd
ML		 203};
204
205#define VENDOR(x) &supported_vendors[x]
206/* vendor, series, protocol, max timebase, min vdiv, number of horizontal divs,
207 * live waveform samples, memory buffer samples */
208static const struct rigol_ds_series supported_series[] = {
209 [VS5000] = {VENDOR(RIGOL), "VS5000", PROTOCOL_V1, FORMAT_RAW,
210 {50, 1}, {2, 1000}, 14, 2048, 0},
211 [DS1000] = {VENDOR(RIGOL), "DS1000", PROTOCOL_V2, FORMAT_IEEE488_2,
212 {50, 1}, {2, 1000}, 12, 600, 1048576},
213 [DS2000] = {VENDOR(RIGOL), "DS2000", PROTOCOL_V3, FORMAT_IEEE488_2,
96cb7faa 214 {500, 1}, {500, 1000000}, 14, 1400, 14000},
569d4dbd
ML		 215 [DS2000A] = {VENDOR(RIGOL), "DS2000A", PROTOCOL_V3, FORMAT_IEEE488_2,
216 {1000, 1}, {500, 1000000}, 14, 1400, 14000},
217 [DSO1000] = {VENDOR(AGILENT), "DSO1000", PROTOCOL_V3, FORMAT_IEEE488_2,
218 {50, 1}, {2, 1000}, 12, 600, 20480},
702f42e8
ML		 219 [DS1000Z] = {VENDOR(RIGOL), "DS1000Z", PROTOCOL_V4, FORMAT_IEEE488_2,
220 {50, 1}, {1, 1000}, 12, 1200, 12000000},
569d4dbd 221};
10afee13 222
569d4dbd
ML		 223#define SERIES(x) &supported_series[x]
224/* series, model, min timebase, analog channels, digital */
bafd4890 225static const struct rigol_ds_model supported_models[] = {
569d4dbd
ML		 226 {SERIES(VS5000), "VS5022", {20, 1000000000}, 2, false},
227 {SERIES(VS5000), "VS5042", {10, 1000000000}, 2, false},
228 {SERIES(VS5000), "VS5062", {5, 1000000000}, 2, false},
229 {SERIES(VS5000), "VS5102", {2, 1000000000}, 2, false},
230 {SERIES(VS5000), "VS5202", {2, 1000000000}, 2, false},
231 {SERIES(VS5000), "VS5022D", {20, 1000000000}, 2, true},
232 {SERIES(VS5000), "VS5042D", {10, 1000000000}, 2, true},
233 {SERIES(VS5000), "VS5062D", {5, 1000000000}, 2, true},
234 {SERIES(VS5000), "VS5102D", {2, 1000000000}, 2, true},
235 {SERIES(VS5000), "VS5202D", {2, 1000000000}, 2, true},
236 {SERIES(DS1000), "DS1052E", {5, 1000000000}, 2, false},
237 {SERIES(DS1000), "DS1102E", {2, 1000000000}, 2, false},
238 {SERIES(DS1000), "DS1152E", {2, 1000000000}, 2, false},
239 {SERIES(DS1000), "DS1052D", {5, 1000000000}, 2, true},
240 {SERIES(DS1000), "DS1102D", {2, 1000000000}, 2, true},
241 {SERIES(DS1000), "DS1152D", {2, 1000000000}, 2, true},
242 {SERIES(DS2000), "DS2072", {5, 1000000000}, 2, false},
243 {SERIES(DS2000), "DS2102", {5, 1000000000}, 2, false},
244 {SERIES(DS2000), "DS2202", {2, 1000000000}, 2, false},
245 {SERIES(DS2000), "DS2302", {1, 1000000000}, 2, false},
246 {SERIES(DS2000A), "DS2072A", {5, 1000000000}, 2, false},
247 {SERIES(DS2000A), "DS2102A", {5, 1000000000}, 2, false},
248 {SERIES(DS2000A), "DS2202A", {2, 1000000000}, 2, false},
249 {SERIES(DS2000A), "DS2302A", {1, 1000000000}, 2, false},
250 {SERIES(DSO1000), "DSO1002A", {5, 1000000000}, 2, false},
251 {SERIES(DSO1000), "DSO1004A", {5, 1000000000}, 4, false},
252 {SERIES(DSO1000), "DSO1012A", {2, 1000000000}, 2, false},
253 {SERIES(DSO1000), "DSO1014A", {2, 1000000000}, 4, false},
254 {SERIES(DSO1000), "DSO1022A", {2, 1000000000}, 2, false},
255 {SERIES(DSO1000), "DSO1024A", {2, 1000000000}, 4, false},
702f42e8
ML		 256 {SERIES(DS1000Z), "DS1054Z", {5, 1000000000}, 4, false},
257 {SERIES(DS1000Z), "DS1074Z", {5, 1000000000}, 4, false},
258 {SERIES(DS1000Z), "DS1104Z", {5, 1000000000}, 4, false},
259 {SERIES(DS1000Z), "DS1074Z-S", {5, 1000000000}, 4, false},
260 {SERIES(DS1000Z), "DS1104Z-S", {5, 1000000000}, 4, false},
261 {SERIES(DS1000Z), "MSO1074Z", {5, 1000000000}, 4, true},
262 {SERIES(DS1000Z), "MSO1104Z", {5, 1000000000}, 4, true},
263 {SERIES(DS1000Z), "MSO1074Z-S", {5, 1000000000}, 4, true},
264 {SERIES(DS1000Z), "MSO1104Z-S", {5, 1000000000}, 4, true},
512bb890
BV		 265};
266
dd5c48a6 267static struct sr_dev_driver rigol_ds_driver_info;
f4816ac6 268
fa85f376 269static void clear_helper(void *priv)
f4816ac6 270{
f4816ac6 271 struct dev_context *devc;
effb9dd1 272 unsigned int i;
f4816ac6 273
ba358ffd 274 devc = priv;
babab622
ML		 275 g_free(devc->data);
276 g_free(devc->buffer);
effb9dd1
AJ		 277 for (i = 0; i < ARRAY_SIZE(devc->coupling); i++)
278 g_free(devc->coupling[i]);
fa85f376
UH		 279 g_free(devc->trigger_source);
280 g_free(devc->trigger_slope);
562b7ae5 281 g_free(devc->analog_groups);
562b7ae5 282 g_free(devc);
fa85f376 283}
f4816ac6 284
4f840ce9 285static int dev_clear(const struct sr_dev_driver *di)
fa85f376
UH		 286{
287 return std_dev_clear(di, clear_helper);
f4816ac6
ML		 288}
289
9d3ae01b 290static struct sr_dev_inst *probe_device(struct sr_scpi_dev_inst *scpi)
f4816ac6 291{
cc9fd2d2
BV		 292 struct dev_context *devc;
293 struct sr_dev_inst *sdi;
ae1bc1cc 294 struct sr_scpi_hw_info *hw_info;
ba7dd8bb 295 struct sr_channel *ch;
8dd0b290 296 long n[3];
f6a0ac9f 297 unsigned int i;
bafd4890 298 const struct rigol_ds_model *model = NULL;
569d4dbd 299 gchar *channel_name, **version;
fb6e5ba8 300
ae1bc1cc 301 if (sr_scpi_get_hw_id(scpi, &hw_info) != SR_OK) {
05238d28
ML		 302 sr_info("Couldn't get IDN response, retrying.");
303 sr_scpi_close(scpi);
304 sr_scpi_open(scpi);
305 if (sr_scpi_get_hw_id(scpi, &hw_info) != SR_OK) {
306 sr_info("Couldn't get IDN response.");
307 return NULL;
308 }
ca55277c 309 }
e0b7d23c 310
ca55277c 311 for (i = 0; i < ARRAY_SIZE(supported_models); i++) {
34577da6 312 if (!g_ascii_strcasecmp(hw_info->manufacturer,
569d4dbd 313 supported_models[i].series->vendor->full_name) &&
10afee13 314 !strcmp(hw_info->model, supported_models[i].name)) {
bafd4890 315 model = &supported_models[i];
ca55277c 316 break;
fb6e5ba8 317 }
ca55277c 318 }
fb6e5ba8 319
0af636be 320 if (!model) {
ae1bc1cc 321 sr_scpi_hw_info_free(hw_info);
9d3ae01b 322 return NULL;
ca55277c 323 }
fb6e5ba8 324
aac29cc1 325 sdi = g_malloc0(sizeof(struct sr_dev_inst));
0af636be
UH		 326 sdi->vendor = g_strdup(model->series->vendor->name);
327 sdi->model = g_strdup(model->name);
328 sdi->version = g_strdup(hw_info->firmware_version);
ae1bc1cc 329 sdi->conn = scpi;
4f840ce9 330 sdi->driver = &rigol_ds_driver_info;
ae1bc1cc 331 sdi->inst_type = SR_INST_SCPI;
b3fccc85 332 sdi->serial_num = g_strdup(hw_info->serial_number);
f57d8ffe 333 devc = g_malloc0(sizeof(struct dev_context));
cc9fd2d2 334 devc->limit_frames = 0;
bafd4890 335 devc->model = model;
569d4dbd 336 devc->format = model->series->format;
8dd0b290 337
569d4dbd
ML		 338 /* DS1000 models with firmware before 0.2.4 used the old data format. */
339 if (model->series == SERIES(DS1000)) {
8dd0b290
BV		 340 version = g_strsplit(hw_info->firmware_version, ".", 0);
341 do {
342 if (!version[0] || !version[1] || !version[2])
343 break;
344 if (version[0][0] == 0 || version[1][0] == 0 || version[2][0] == 0)
345 break;
346 for (i = 0; i < 3; i++) {
347 if (sr_atol(version[i], &n[i]) != SR_OK)
348 break;
349 }
350 if (i != 3)
351 break;
de285cce
BV		 352 scpi->firmware_version = n[0] * 100 + n[1] * 10 + n[2];
353 if (scpi->firmware_version < 24) {
354 sr_dbg("Found DS1000 firmware < 0.2.4, using raw data format.");
355 devc->format = FORMAT_RAW;
356 }
357 break;
0c5f2abc 358 } while (0);
8dd0b290
BV		 359 g_strfreev(version);
360 }
361
362 sr_scpi_hw_info_free(hw_info);
512bb890 363
562b7ae5
SA		 364 devc->analog_groups = g_malloc0(sizeof(struct sr_channel_group*) *
365 model->analog_channels);
366
821fbcad 367 for (i = 0; i < model->analog_channels; i++) {
eac0c613 368 channel_name = g_strdup_printf("CH%d", i + 1);
5e23fcab 369 ch = sr_channel_new(sdi, i, SR_CHANNEL_ANALOG, TRUE, channel_name);
562b7ae5
SA		 370
371 devc->analog_groups[i] = g_malloc0(sizeof(struct sr_channel_group));
372
373 devc->analog_groups[i]->name = channel_name;
374 devc->analog_groups[i]->channels = g_slist_append(NULL, ch);
660e398f 375 sdi->channel_groups = g_slist_append(sdi->channel_groups,
562b7ae5 376 devc->analog_groups[i]);
ca55277c 377 }
512bb890 378
bafd4890 379 if (devc->model->has_digital) {
16aca766 380 devc->digital_group = g_malloc0(sizeof(struct sr_channel_group));
562b7ae5 381
effb9dd1 382 for (i = 0; i < ARRAY_SIZE(devc->digital_channels); i++) {
eac0c613 383 channel_name = g_strdup_printf("D%d", i);
5e23fcab 384 ch = sr_channel_new(sdi, i, SR_CHANNEL_LOGIC, TRUE, channel_name);
ca55277c 385 g_free(channel_name);
562b7ae5
SA		 386 devc->digital_group->channels = g_slist_append(
387 devc->digital_group->channels, ch);
512bb890 388 }
562b7ae5 389 devc->digital_group->name = g_strdup("LA");
660e398f 390 sdi->channel_groups = g_slist_append(sdi->channel_groups,
562b7ae5 391 devc->digital_group);
ca55277c 392 }
bafd4890
ML		 393
394 for (i = 0; i < NUM_TIMEBASE; i++) {
395 if (!memcmp(&devc->model->min_timebase, &timebases[i], sizeof(uint64_t[2])))
396 devc->timebases = &timebases[i];
569d4dbd 397 if (!memcmp(&devc->model->series->max_timebase, &timebases[i], sizeof(uint64_t[2])))
bafd4890
ML		 398 devc->num_timebases = &timebases[i] - devc->timebases + 1;
399 }
400
a95f142e
UH		 401 for (i = 0; i < NUM_VDIV; i++) {
402 if (!memcmp(&devc->model->series->min_vdiv,
403 &vdivs[i], sizeof(uint64_t[2]))) {
6ff1394e 404 devc->vdivs = &vdivs[i];
81b85663
AJ		 405 devc->num_vdivs = NUM_VDIV - i;
406 }
a95f142e 407 }
bafd4890 408
a95f142e
UH		 409 devc->buffer = g_malloc(ACQ_BUFFER_SIZE);
410 devc->data = g_malloc(ACQ_BUFFER_SIZE * sizeof(float));
babab622
ML		 411
412 devc->data_source = DATA_SOURCE_LIVE;
413
cc9fd2d2
BV		 414 sdi->priv = devc;
415
9d3ae01b 416 return sdi;
ca55277c 417}
512bb890 418
4f840ce9 419static GSList *scan(struct sr_dev_driver *di, GSList *options)
ca55277c 420{
41812aca 421 return sr_scpi_scan(di->context, options, probe_device);
f4816ac6
ML		 422}
423
6078d2c9 424static int dev_open(struct sr_dev_inst *sdi)
f4816ac6 425{
e1b5b7e7 426 int ret;
ae1bc1cc 427 struct sr_scpi_dev_inst *scpi = sdi->conn;
9bd4c956 428
e1b5b7e7
UH		 429 if ((ret = sr_scpi_open(scpi)) < 0) {
430 sr_err("Failed to open SCPI device: %s.", sr_strerror(ret));
e0b7d23c 431 return SR_ERR;
e1b5b7e7 432 }
e0b7d23c 433
e1b5b7e7
UH		 434 if ((ret = rigol_ds_get_dev_cfg(sdi)) < 0) {
435 sr_err("Failed to get device config: %s.", sr_strerror(ret));
254dd102 436 return SR_ERR;
e1b5b7e7 437 }
f4816ac6 438
46a743c1 439 sdi->status = SR_ST_ACTIVE;
cc9fd2d2 440
f4816ac6
ML		 441 return SR_OK;
442}
443
6078d2c9 444static int dev_close(struct sr_dev_inst *sdi)
f4816ac6 445{
ae1bc1cc 446 struct sr_scpi_dev_inst *scpi;
22c19688 447 struct dev_context *devc;
ae1bc1cc 448
83dbd9f0
AJ		 449 if (sdi->status != SR_ST_ACTIVE)
450 return SR_ERR_DEV_CLOSED;
464d4936 451
ae1bc1cc 452 scpi = sdi->conn;
22c19688
ML		 453 devc = sdi->priv;
454
6e94eb41 455 if (devc->model->series->protocol == PROTOCOL_V2)
38354d9d 456 rigol_ds_config_set(sdi, ":KEY:LOCK DISABLE");
e0b7d23c 457
ae1bc1cc
ML		 458 if (scpi) {
459 if (sr_scpi_close(scpi) < 0)
460 return SR_ERR;
cc9fd2d2
BV		 461 sdi->status = SR_ST_INACTIVE;
462 }
f4816ac6
ML		 463
464 return SR_OK;
465}
466
5415e602
ML		 467static int analog_frame_size(const struct sr_dev_inst *sdi)
468{
469 struct dev_context *devc = sdi->priv;
ba7dd8bb
UH		 470 struct sr_channel *ch;
471 int analog_channels = 0;
5415e602
ML		 472 GSList *l;
473
ba7dd8bb
UH		 474 for (l = sdi->channels; l; l = l->next) {
475 ch = l->data;
3f239f08 476 if (ch->type == SR_CHANNEL_ANALOG && ch->enabled)
ba7dd8bb 477 analog_channels++;
569d4dbd
ML		 478 }
479
ba7dd8bb 480 if (analog_channels == 0)
824eb2ac
ML		 481 return 0;
482
569d4dbd
ML		 483 switch (devc->data_source) {
484 case DATA_SOURCE_LIVE:
485 return devc->model->series->live_samples;
486 case DATA_SOURCE_MEMORY:
ba7dd8bb 487 return devc->model->series->buffer_samples / analog_channels;
470140fc 488 default:
569d4dbd 489 return 0;
5415e602
ML		 490 }
491}
492
d22250a9
ML		 493static int digital_frame_size(const struct sr_dev_inst *sdi)
494{
495 struct dev_context *devc = sdi->priv;
496
569d4dbd
ML		 497 switch (devc->data_source) {
498 case DATA_SOURCE_LIVE:
499 return devc->model->series->live_samples * 2;
500 case DATA_SOURCE_MEMORY:
501 return devc->model->series->buffer_samples * 2;
d22250a9
ML		 502 default:
503 return 0;
504 }
505}
506
584560f1 507static int config_get(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi,
53b4680f 508 const struct sr_channel_group *cg)
d62d7ad1 509{
e43fdd8d 510 struct dev_context *devc;
ba7dd8bb 511 struct sr_channel *ch;
2b0e4a46 512 const char *tmp_str;
c2b394d5 513 uint64_t samplerate;
2b0e4a46 514 int analog_channel = -1;
c33ff377 515 float smallest_diff = INFINITY;
2b0e4a46
AJ		 516 int idx = -1;
517 unsigned i;
d62d7ad1 518
709468ba 519 if (!sdi)
e43fdd8d
BV		 520 return SR_ERR_ARG;
521
709468ba
UH		 522 devc = sdi->priv;
523
660e398f 524 /* If a channel group is specified, it must be a valid one. */
53b4680f 525 if (cg && !g_slist_find(sdi->channel_groups, cg)) {
660e398f 526 sr_err("Invalid channel group specified.");
969edf63 527 return SR_ERR;
be60a9e4
BV		 528 }
529
53b4680f 530 if (cg) {
ba7dd8bb
UH		 531 ch = g_slist_nth_data(cg->channels, 0);
532 if (!ch)
2b0e4a46 533 return SR_ERR;
3f239f08 534 if (ch->type == SR_CHANNEL_ANALOG) {
ba7dd8bb 535 if (ch->name[2] < '1' || ch->name[2] > '4')
2b0e4a46 536 return SR_ERR;
ba7dd8bb 537 analog_channel = ch->name[2] - '1';
2b0e4a46
AJ		 538 }
539 }
540
584560f1 541 switch (key) {
bf622e6d 542 case SR_CONF_NUM_HDIV:
569d4dbd 543 *data = g_variant_new_int32(devc->model->series->num_horizontal_divs);
d62d7ad1
BV		 544 break;
545 case SR_CONF_NUM_VDIV:
81b85663 546 *data = g_variant_new_int32(devc->num_vdivs);
f44f7e61 547 break;
babab622
ML		 548 case SR_CONF_DATA_SOURCE:
549 if (devc->data_source == DATA_SOURCE_LIVE)
550 *data = g_variant_new_string("Live");
551 else if (devc->data_source == DATA_SOURCE_MEMORY)
552 *data = g_variant_new_string("Memory");
553 else
554 *data = g_variant_new_string("Segmented");
555 break;
4914dd4b
ML		 556 case SR_CONF_SAMPLERATE:
557 if (devc->data_source == DATA_SOURCE_LIVE) {
c2b394d5 558 samplerate = analog_frame_size(sdi) /
569d4dbd 559 (devc->timebase * devc->model->series->num_horizontal_divs);
4914dd4b 560 *data = g_variant_new_uint64(samplerate);
c2b394d5 561 } else {
e1b5b7e7 562 sr_dbg("Unknown data source: %d.", devc->data_source);
4914dd4b 563 return SR_ERR_NA;
c2b394d5 564 }
4914dd4b 565 break;
2b0e4a46
AJ		 566 case SR_CONF_TRIGGER_SOURCE:
567 if (!strcmp(devc->trigger_source, "ACL"))
568 tmp_str = "AC Line";
569 else if (!strcmp(devc->trigger_source, "CHAN1"))
570 tmp_str = "CH1";
571 else if (!strcmp(devc->trigger_source, "CHAN2"))
572 tmp_str = "CH2";
573 else if (!strcmp(devc->trigger_source, "CHAN3"))
574 tmp_str = "CH3";
575 else if (!strcmp(devc->trigger_source, "CHAN4"))
576 tmp_str = "CH4";
577 else
578 tmp_str = devc->trigger_source;
579 *data = g_variant_new_string(tmp_str);
580 break;
5d336f11 581 case SR_CONF_TRIGGER_SLOPE:
e1b5b7e7 582 if (!strncmp(devc->trigger_slope, "POS", 3)) {
5d336f11 583 tmp_str = "r";
e1b5b7e7 584 } else if (!strncmp(devc->trigger_slope, "NEG", 3)) {
5d336f11 585 tmp_str = "f";
e1b5b7e7
UH		 586 } else {
587 sr_dbg("Unknown trigger slope: '%s'.", devc->trigger_slope);
5d336f11 588 return SR_ERR_NA;
e1b5b7e7 589 }
5d336f11
AJ		 590 *data = g_variant_new_string(tmp_str);
591 break;
9ea62f2e
AJ		 592 case SR_CONF_TRIGGER_LEVEL:
593 *data = g_variant_new_double(devc->trigger_level);
594 break;
2b0e4a46
AJ		 595 case SR_CONF_TIMEBASE:
596 for (i = 0; i < devc->num_timebases; i++) {
597 float tb = (float)devc->timebases[i][0] / devc->timebases[i][1];
598 float diff = fabs(devc->timebase - tb);
599 if (diff < smallest_diff) {
600 smallest_diff = diff;
601 idx = i;
602 }
603 }
e1b5b7e7
UH		 604 if (idx < 0) {
605 sr_dbg("Negative timebase index: %d.", idx);
2b0e4a46 606 return SR_ERR_NA;
e1b5b7e7 607 }
2b0e4a46
AJ		 608 *data = g_variant_new("(tt)", devc->timebases[idx][0],
609 devc->timebases[idx][1]);
610 break;
611 case SR_CONF_VDIV:
e1b5b7e7
UH		 612 if (analog_channel < 0) {
613 sr_dbg("Negative analog channel: %d.", analog_channel);
2b0e4a46 614 return SR_ERR_NA;
e1b5b7e7 615 }
2b0e4a46
AJ		 616 for (i = 0; i < ARRAY_SIZE(vdivs); i++) {
617 float vdiv = (float)vdivs[i][0] / vdivs[i][1];
618 float diff = fabs(devc->vdiv[analog_channel] - vdiv);
619 if (diff < smallest_diff) {
620 smallest_diff = diff;
621 idx = i;
622 }
623 }
e1b5b7e7
UH		 624 if (idx < 0) {
625 sr_dbg("Negative vdiv index: %d.", idx);
2b0e4a46 626 return SR_ERR_NA;
e1b5b7e7 627 }
2b0e4a46
AJ		 628 *data = g_variant_new("(tt)", vdivs[idx][0], vdivs[idx][1]);
629 break;
630 case SR_CONF_COUPLING:
e1b5b7e7
UH		 631 if (analog_channel < 0) {
632 sr_dbg("Negative analog channel: %d.", analog_channel);
2b0e4a46 633 return SR_ERR_NA;
e1b5b7e7 634 }
2b0e4a46
AJ		 635 *data = g_variant_new_string(devc->coupling[analog_channel]);
636 break;
934cf6cf
AJ		 637 case SR_CONF_PROBE_FACTOR:
638 if (analog_channel < 0) {
639 sr_dbg("Negative analog channel: %d.", analog_channel);
640 return SR_ERR_NA;
641 }
642 *data = g_variant_new_uint64(devc->attenuation[analog_channel]);
643 break;
d62d7ad1 644 default:
bd6fbf62 645 return SR_ERR_NA;
d62d7ad1
BV		 646 }
647
648 return SR_OK;
649}
650
584560f1 651static int config_set(uint32_t key, GVariant *data, const struct sr_dev_inst *sdi,
53b4680f 652 const struct sr_channel_group *cg)
f4816ac6 653{
29d957ce 654 struct dev_context *devc;
ca9b9f48 655 uint64_t p, q;
254dd102 656 double t_dbl;
f48e0249 657 unsigned int i, j;
254dd102
BV		 658 int ret;
659 const char *tmp_str;
889ef4a0 660 char buffer[16];
f4816ac6 661
b0baddef 662 devc = sdi->priv;
29d957ce 663
e73ffd42
BV		 664 if (sdi->status != SR_ST_ACTIVE)
665 return SR_ERR_DEV_CLOSED;
f4816ac6 666
660e398f 667 /* If a channel group is specified, it must be a valid one. */
53b4680f 668 if (cg && !g_slist_find(sdi->channel_groups, cg)) {
660e398f 669 sr_err("Invalid channel group specified.");
969edf63 670 return SR_ERR;
be60a9e4
BV		 671 }
672
f4816ac6 673 ret = SR_OK;
584560f1 674 switch (key) {
1953564a 675 case SR_CONF_LIMIT_FRAMES:
f6a0ac9f 676 devc->limit_frames = g_variant_get_uint64(data);
e0b7d23c 677 break;
1953564a 678 case SR_CONF_TRIGGER_SLOPE:
ca9b9f48
DE		 679 tmp_str = g_variant_get_string(data, NULL);
680
e1b5b7e7
UH		 681 if (!tmp_str || !(tmp_str[0] == 'f' || tmp_str[0] == 'r')) {
682 sr_err("Unknown trigger slope: '%s'.",
683 (tmp_str) ? tmp_str : "NULL");
ca9b9f48 684 return SR_ERR_ARG;
e1b5b7e7 685 }
ca9b9f48 686
254dd102 687 g_free(devc->trigger_slope);
ca9b9f48 688 devc->trigger_slope = g_strdup((tmp_str[0] == 'r') ? "POS" : "NEG");
38354d9d 689 ret = rigol_ds_config_set(sdi, ":TRIG:EDGE:SLOP %s", devc->trigger_slope);
e0b7d23c 690 break;
1953564a 691 case SR_CONF_HORIZ_TRIGGERPOS:
254dd102 692 t_dbl = g_variant_get_double(data);
e1b5b7e7
UH		 693 if (t_dbl < 0.0 || t_dbl > 1.0) {
694 sr_err("Invalid horiz. trigger position: %g.", t_dbl);
254dd102 695 return SR_ERR;
e1b5b7e7 696 }
254dd102
BV		 697 devc->horiz_triggerpos = t_dbl;
698 /* We have the trigger offset as a percentage of the frame, but
699 * need to express this in seconds. */
bafd4890 700 t_dbl = -(devc->horiz_triggerpos - 0.5) * devc->timebase * devc->num_timebases;
889ef4a0 701 g_ascii_formatd(buffer, sizeof(buffer), "%.6f", t_dbl);
38354d9d 702 ret = rigol_ds_config_set(sdi, ":TIM:OFFS %s", buffer);
e0b7d23c 703 break;
9ea62f2e
AJ		 704 case SR_CONF_TRIGGER_LEVEL:
705 t_dbl = g_variant_get_double(data);
706 g_ascii_formatd(buffer, sizeof(buffer), "%.3f", t_dbl);
707 ret = rigol_ds_config_set(sdi, ":TRIG:EDGE:LEV %s", buffer);
708 if (ret == SR_OK)
709 devc->trigger_level = t_dbl;
710 break;
1953564a 711 case SR_CONF_TIMEBASE:
f6a0ac9f 712 g_variant_get(data, "(tt)", &p, &q);
bafd4890
ML		 713 for (i = 0; i < devc->num_timebases; i++) {
714 if (devc->timebases[i][0] == p && devc->timebases[i][1] == q) {
254dd102 715 devc->timebase = (float)p / q;
889ef4a0
AJ		 716 g_ascii_formatd(buffer, sizeof(buffer), "%.9f",
717 devc->timebase);
38354d9d 718 ret = rigol_ds_config_set(sdi, ":TIM:SCAL %s", buffer);
f6a0ac9f
BV		 719 break;
720 }
721 }
e1b5b7e7
UH		 722 if (i == devc->num_timebases) {
723 sr_err("Invalid timebase index: %d.", i);
254dd102 724 ret = SR_ERR_ARG;
e1b5b7e7 725 }
e0b7d23c 726 break;
1953564a 727 case SR_CONF_TRIGGER_SOURCE:
f6a0ac9f 728 tmp_str = g_variant_get_string(data, NULL);
254dd102
BV		 729 for (i = 0; i < ARRAY_SIZE(trigger_sources); i++) {
730 if (!strcmp(trigger_sources[i], tmp_str)) {
731 g_free(devc->trigger_source);
732 devc->trigger_source = g_strdup(trigger_sources[i]);
733 if (!strcmp(devc->trigger_source, "AC Line"))
734 tmp_str = "ACL";
735 else if (!strcmp(devc->trigger_source, "CH1"))
736 tmp_str = "CHAN1";
737 else if (!strcmp(devc->trigger_source, "CH2"))
738 tmp_str = "CHAN2";
821fbcad
ML		 739 else if (!strcmp(devc->trigger_source, "CH3"))
740 tmp_str = "CHAN3";
741 else if (!strcmp(devc->trigger_source, "CH4"))
742 tmp_str = "CHAN4";
254dd102
BV		 743 else
744 tmp_str = (char *)devc->trigger_source;
38354d9d 745 ret = rigol_ds_config_set(sdi, ":TRIG:EDGE:SOUR %s", tmp_str);
254dd102
BV		 746 break;
747 }
4e108ace 748 }
e1b5b7e7
UH		 749 if (i == ARRAY_SIZE(trigger_sources)) {
750 sr_err("Invalid trigger source index: %d.", i);
254dd102 751 ret = SR_ERR_ARG;
e1b5b7e7 752 }
e0b7d23c 753 break;
1953564a 754 case SR_CONF_VDIV:
53b4680f 755 if (!cg) {
660e398f
UH		 756 sr_err("No channel group specified.");
757 return SR_ERR_CHANNEL_GROUP;
be60a9e4 758 }
f6a0ac9f 759 g_variant_get(data, "(tt)", &p, &q);
effb9dd1 760 for (i = 0; i < devc->model->analog_channels; i++) {
562b7ae5 761 if (cg == devc->analog_groups[i]) {
78bcc55a 762 for (j = 0; j < ARRAY_SIZE(vdivs); j++) {
f48e0249
ML		 763 if (vdivs[j][0] != p || vdivs[j][1] != q)
764 continue;
765 devc->vdiv[i] = (float)p / q;
889ef4a0
AJ		 766 g_ascii_formatd(buffer, sizeof(buffer), "%.3f",
767 devc->vdiv[i]);
38354d9d 768 return rigol_ds_config_set(sdi, ":CHAN%d:SCAL %s", i + 1,
889ef4a0 769 buffer);
f48e0249 770 }
e1b5b7e7 771 sr_err("Invalid vdiv index: %d.", j);
f48e0249
ML		 772 return SR_ERR_ARG;
773 }
e0b7d23c 774 }
e1b5b7e7 775 sr_dbg("Didn't set vdiv, unknown channel(group).");
f48e0249 776 return SR_ERR_NA;
1953564a 777 case SR_CONF_COUPLING:
53b4680f 778 if (!cg) {
660e398f
UH		 779 sr_err("No channel group specified.");
780 return SR_ERR_CHANNEL_GROUP;
78bcc55a 781 }
f6a0ac9f 782 tmp_str = g_variant_get_string(data, NULL);
effb9dd1 783 for (i = 0; i < devc->model->analog_channels; i++) {
562b7ae5 784 if (cg == devc->analog_groups[i]) {
78bcc55a
BV		 785 for (j = 0; j < ARRAY_SIZE(coupling); j++) {
786 if (!strcmp(tmp_str, coupling[j])) {
f48e0249
ML		 787 g_free(devc->coupling[i]);
788 devc->coupling[i] = g_strdup(coupling[j]);
38354d9d 789 return rigol_ds_config_set(sdi, ":CHAN%d:COUP %s", i + 1,
f48e0249
ML		 790 devc->coupling[i]);
791 }
792 }
e1b5b7e7 793 sr_err("Invalid coupling index: %d.", j);
f48e0249 794 return SR_ERR_ARG;
e0b7d23c
ML		 795 }
796 }
e1b5b7e7 797 sr_dbg("Didn't set coupling, unknown channel(group).");
f48e0249 798 return SR_ERR_NA;
934cf6cf
AJ		 799 case SR_CONF_PROBE_FACTOR:
800 if (!cg) {
801 sr_err("No channel group specified.");
802 return SR_ERR_CHANNEL_GROUP;
803 }
804 p = g_variant_get_uint64(data);
805 for (i = 0; i < devc->model->analog_channels; i++) {
806 if (cg == devc->analog_groups[i]) {
807 for (j = 0; j < ARRAY_SIZE(probe_factor); j++) {
808 if (p == probe_factor[j]) {
809 devc->attenuation[i] = p;
810 ret = rigol_ds_config_set(sdi, ":CHAN%d:PROB %"PRIu64,
811 i + 1, p);
812 if (ret == SR_OK)
813 rigol_ds_get_dev_cfg_vertical(sdi);
814 return ret;
815 }
816 }
817 sr_err("Invalid probe factor: %"PRIu64".", p);
818 return SR_ERR_ARG;
819 }
820 }
821 sr_dbg("Didn't set probe factor, unknown channel(group).");
822 return SR_ERR_NA;
babab622
ML		 823 case SR_CONF_DATA_SOURCE:
824 tmp_str = g_variant_get_string(data, NULL);
825 if (!strcmp(tmp_str, "Live"))
826 devc->data_source = DATA_SOURCE_LIVE;
569d4dbd
ML		 827 else if (devc->model->series->protocol >= PROTOCOL_V2
828 && !strcmp(tmp_str, "Memory"))
babab622 829 devc->data_source = DATA_SOURCE_MEMORY;
569d4dbd 830 else if (devc->model->series->protocol >= PROTOCOL_V3
babab622
ML		 831 && !strcmp(tmp_str, "Segmented"))
832 devc->data_source = DATA_SOURCE_SEGMENTED;
e1b5b7e7
UH		 833 else {
834 sr_err("Unknown data source: '%s'.", tmp_str);
babab622 835 return SR_ERR;
e1b5b7e7 836 }
babab622 837 break;
f4816ac6 838 default:
dcd438ee 839 return SR_ERR_NA;
f4816ac6
ML		 840 }
841
842 return ret;
843}
844
584560f1 845static int config_list(uint32_t key, GVariant **data, const struct sr_dev_inst *sdi,
53b4680f 846 const struct sr_channel_group *cg)
a1c743fc 847{
861c447b
BV		 848 GVariant *tuple, *rational[2];
849 GVariantBuilder gvb;
850 unsigned int i;
7cc1a550
ML		 851 struct dev_context *devc = NULL;
852
e43fdd8d 853 if (key == SR_CONF_SCAN_OPTIONS) {
584560f1 854 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
a0e0bb41 855 scanopts, ARRAY_SIZE(scanopts), sizeof(uint32_t));
e43fdd8d 856 return SR_OK;
0c5f2abc 857 } else if (key == SR_CONF_DEVICE_OPTIONS && !cg) {
584560f1 858 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
f254bc4b 859 devopts, ARRAY_SIZE(devopts), sizeof(uint32_t));
e43fdd8d
BV		 860 return SR_OK;
861 }
862
863 /* Every other option requires a valid device instance. */
4d399734 864 if (!sdi)
e43fdd8d 865 return SR_ERR_ARG;
4d399734 866 devc = sdi->priv;
e43fdd8d 867
660e398f 868 /* If a channel group is specified, it must be a valid one. */
40c2c915
ML		 869 if (cg && !g_slist_find(sdi->channel_groups, cg)) {
870 sr_err("Invalid channel group specified.");
871 return SR_ERR;
be60a9e4
BV		 872 }
873
e43fdd8d 874 switch (key) {
9a6517d1 875 case SR_CONF_DEVICE_OPTIONS:
53b4680f 876 if (!cg) {
660e398f
UH		 877 sr_err("No channel group specified.");
878 return SR_ERR_CHANNEL_GROUP;
be60a9e4 879 }
562b7ae5 880 if (cg == devc->digital_group) {
584560f1
BV		 881 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
882 NULL, 0, sizeof(uint32_t));
f48e0249
ML		 883 return SR_OK;
884 } else {
effb9dd1 885 for (i = 0; i < devc->model->analog_channels; i++) {
562b7ae5 886 if (cg == devc->analog_groups[i]) {
584560f1 887 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT32,
f254bc4b 888 analog_devopts, ARRAY_SIZE(analog_devopts), sizeof(uint32_t));
f48e0249
ML		 889 return SR_OK;
890 }
891 }
892 return SR_ERR_NA;
893 }
5f77dffc 894 break;
2a7b113d 895 case SR_CONF_COUPLING:
53b4680f 896 if (!cg) {
660e398f
UH		 897 sr_err("No channel group specified.");
898 return SR_ERR_CHANNEL_GROUP;
f48e0249 899 }
58f43369
BV		 900 *data = g_variant_new_strv(coupling, ARRAY_SIZE(coupling));
901 break;
934cf6cf
AJ		 902 case SR_CONF_PROBE_FACTOR:
903 if (!cg) {
904 sr_err("No channel group specified.");
905 return SR_ERR_CHANNEL_GROUP;
906 }
907 *data = g_variant_new_fixed_array(G_VARIANT_TYPE_UINT64,
908 probe_factor, ARRAY_SIZE(probe_factor), sizeof(uint64_t));
909 break;
e4f2b2ad 910 case SR_CONF_VDIV:
7cc1a550
ML		 911 if (!devc)
912 /* Can't know this until we have the exact model. */
913 return SR_ERR_ARG;
53b4680f 914 if (!cg) {
660e398f
UH		 915 sr_err("No channel group specified.");
916 return SR_ERR_CHANNEL_GROUP;
861c447b 917 }
58f43369 918 g_variant_builder_init(&gvb, G_VARIANT_TYPE_ARRAY);
81b85663 919 for (i = 0; i < devc->num_vdivs; i++) {
bafd4890
ML		 920 rational[0] = g_variant_new_uint64(devc->vdivs[i][0]);
921 rational[1] = g_variant_new_uint64(devc->vdivs[i][1]);
58f43369
BV		 922 tuple = g_variant_new_tuple(rational, 2);
923 g_variant_builder_add_value(&gvb, tuple);
924 }
925 *data = g_variant_builder_end(&gvb);
926 break;
41f5bd09 927 case SR_CONF_TIMEBASE:
7cc1a550
ML		 928 if (!devc)
929 /* Can't know this until we have the exact model. */
930 return SR_ERR_ARG;
a31b2ccb
AJ		 931 if (devc->num_timebases <= 0)
932 return SR_ERR_NA;
861c447b 933 g_variant_builder_init(&gvb, G_VARIANT_TYPE_ARRAY);
bafd4890
ML		 934 for (i = 0; i < devc->num_timebases; i++) {
935 rational[0] = g_variant_new_uint64(devc->timebases[i][0]);
936 rational[1] = g_variant_new_uint64(devc->timebases[i][1]);
861c447b
BV		 937 tuple = g_variant_new_tuple(rational, 2);
938 g_variant_builder_add_value(&gvb, tuple);
939 }
940 *data = g_variant_builder_end(&gvb);
41f5bd09 941 break;
328bafab 942 case SR_CONF_TRIGGER_SOURCE:
7cc1a550
ML		 943 if (!devc)
944 /* Can't know this until we have the exact model. */
945 return SR_ERR_ARG;
f6a0ac9f 946 *data = g_variant_new_strv(trigger_sources,
bafd4890 947 devc->model->has_digital ? ARRAY_SIZE(trigger_sources) : 4);
328bafab 948 break;
5d336f11
AJ		 949 case SR_CONF_TRIGGER_SLOPE:
950 *data = g_variant_new_strv(trigger_slopes, ARRAY_SIZE(trigger_slopes));
951 break;
babab622
ML		 952 case SR_CONF_DATA_SOURCE:
953 if (!devc)
954 /* Can't know this until we have the exact model. */
955 return SR_ERR_ARG;
569d4dbd
ML		 956 switch (devc->model->series->protocol) {
957 case PROTOCOL_V1:
958 *data = g_variant_new_strv(data_sources, ARRAY_SIZE(data_sources) - 2);
959 break;
960 case PROTOCOL_V2:
babab622 961 *data = g_variant_new_strv(data_sources, ARRAY_SIZE(data_sources) - 1);
569d4dbd
ML		 962 break;
963 default:
964 *data = g_variant_new_strv(data_sources, ARRAY_SIZE(data_sources));
965 break;
966 }
babab622 967 break;
a1c743fc 968 default:
bd6fbf62 969 return SR_ERR_NA;
a1c743fc
BV		 970 }
971
972 return SR_OK;
973}
974
695dc859 975static int dev_acquisition_start(const struct sr_dev_inst *sdi)
f4816ac6 976{
ae1bc1cc 977 struct sr_scpi_dev_inst *scpi;
29d957ce 978 struct dev_context *devc;
ba7dd8bb 979 struct sr_channel *ch;
f76c24f6 980 struct sr_datafeed_packet packet;
702f42e8 981 gboolean some_digital;
254dd102 982 GSList *l;
29d957ce 983
e73ffd42
BV		 984 if (sdi->status != SR_ST_ACTIVE)
985 return SR_ERR_DEV_CLOSED;
e0b7d23c 986
ae1bc1cc 987 scpi = sdi->conn;
29d957ce
UH		 988 devc = sdi->priv;
989
51b294cd
ML		 990 devc->num_frames = 0;
991
702f42e8 992 some_digital = FALSE;
ba7dd8bb
UH		 993 for (l = sdi->channels; l; l = l->next) {
994 ch = l->data;
995 sr_dbg("handling channel %s", ch->name);
3f239f08 996 if (ch->type == SR_CHANNEL_ANALOG) {
ba7dd8bb 997 if (ch->enabled)
702f42e8
ML		 998 devc->enabled_channels = g_slist_append(
999 devc->enabled_channels, ch);
ba7dd8bb 1000 if (ch->enabled != devc->analog_channels[ch->index]) {
6bb192bc 1001 /* Enabled channel is currently disabled, or vice versa. */
ba7dd8bb
UH		 1002 if (rigol_ds_config_set(sdi, ":CHAN%d:DISP %s", ch->index + 1,
1003 ch->enabled ? "ON" : "OFF") != SR_OK)
6bb192bc 1004 return SR_ERR;
ba7dd8bb 1005 devc->analog_channels[ch->index] = ch->enabled;
6bb192bc 1006 }
3f239f08 1007 } else if (ch->type == SR_CHANNEL_LOGIC) {
702f42e8
ML		 1008 /* Only one list entry for DS1000D series. All channels are retrieved
1009 * together when this entry is processed. */
1010 if (ch->enabled && (
1011 devc->model->series->protocol > PROTOCOL_V2 ||
1012 !some_digital))
1013 devc->enabled_channels = g_slist_append(
1014 devc->enabled_channels, ch);
ba7dd8bb 1015 if (ch->enabled) {
702f42e8 1016 some_digital = TRUE;
04e8e01e
ML		 1017 /* Turn on LA module if currently off. */
1018 if (!devc->la_enabled) {
702f42e8
ML		 1019 if (rigol_ds_config_set(sdi,
1020 devc->model->series->protocol >= PROTOCOL_V4 ?
1021 ":LA:STAT ON" : ":LA:DISP ON") != SR_OK)
04e8e01e
ML		 1022 return SR_ERR;
1023 devc->la_enabled = TRUE;
1024 }
1025 }
ba7dd8bb 1026 if (ch->enabled != devc->digital_channels[ch->index]) {
6bb192bc 1027 /* Enabled channel is currently disabled, or vice versa. */
702f42e8
ML		 1028 if (rigol_ds_config_set(sdi,
1029 devc->model->series->protocol >= PROTOCOL_V4 ?
1030 ":LA:DIG%d:DISP %s" : ":DIG%d:TURN %s", ch->index,
ba7dd8bb 1031 ch->enabled ? "ON" : "OFF") != SR_OK)
6bb192bc 1032 return SR_ERR;
ba7dd8bb 1033 devc->digital_channels[ch->index] = ch->enabled;
6bb192bc 1034 }
254dd102
BV		 1035 }
1036 }
1fed20cb 1037
702f42e8 1038 if (!devc->enabled_channels)
254dd102 1039 return SR_ERR;
e0b7d23c 1040
ba7dd8bb 1041 /* Turn off LA module if on and no digital channels selected. */
702f42e8
ML		 1042 if (devc->la_enabled && !some_digital)
1043 if (rigol_ds_config_set(sdi,
1044 devc->model->series->protocol >= PROTOCOL_V4 ?
1045 ":LA:STAT OFF" : ":LA:DISP OFF") != SR_OK)
04e8e01e
ML		 1046 return SR_ERR;
1047
e086b750
ML		 1048 /* Set memory mode. */
1049 if (devc->data_source == DATA_SOURCE_SEGMENTED) {
1050 sr_err("Data source 'Segmented' not yet supported");
1051 return SR_ERR;
1052 }
1053
1054 devc->analog_frame_size = analog_frame_size(sdi);
1055 devc->digital_frame_size = digital_frame_size(sdi);
1056
569d4dbd
ML		 1057 switch (devc->model->series->protocol) {
1058 case PROTOCOL_V2:
99af83b7 1059 if (rigol_ds_config_set(sdi, ":ACQ:MEMD LONG") != SR_OK)
e086b750 1060 return SR_ERR;
569d4dbd
ML		 1061 break;
1062 case PROTOCOL_V3:
e086b750
ML		 1063 /* Apparently for the DS2000 the memory
1064 * depth can only be set in Running state -
1065 * this matches the behaviour of the UI. */
38354d9d 1066 if (rigol_ds_config_set(sdi, ":RUN") != SR_OK)
1fed20cb 1067 return SR_ERR;
e086b750
ML		 1068 if (rigol_ds_config_set(sdi, ":ACQ:MDEP %d",
1069 devc->analog_frame_size) != SR_OK)
1070 return SR_ERR;
1071 if (rigol_ds_config_set(sdi, ":STOP") != SR_OK)
1fed20cb 1072 return SR_ERR;
569d4dbd
ML		 1073 break;
1074 default:
1075 break;
1fed20cb
ML		 1076 }
1077
e086b750
ML		 1078 if (devc->data_source == DATA_SOURCE_LIVE)
1079 if (rigol_ds_config_set(sdi, ":RUN") != SR_OK)
1080 return SR_ERR;
1081
102f1239
BV		 1082 sr_scpi_source_add(sdi->session, scpi, G_IO_IN, 50,
1083 rigol_ds_receive, (void *)sdi);
e0b7d23c 1084
bee2b016 1085 std_session_send_df_header(sdi);
e0b7d23c 1086
702f42e8 1087 devc->channel_entry = devc->enabled_channels;
821fbcad 1088
e086b750
ML		 1089 if (rigol_ds_capture_start(sdi) != SR_OK)
1090 return SR_ERR;
f4816ac6 1091
f76c24f6
ML		 1092 /* Start of first frame. */
1093 packet.type = SR_DF_FRAME_BEGIN;
695dc859 1094 sr_session_send(sdi, &packet);
f76c24f6 1095
f4816ac6
ML		 1096 return SR_OK;
1097}
1098
695dc859 1099static int dev_acquisition_stop(struct sr_dev_inst *sdi)
f4816ac6 1100{
29d957ce 1101 struct dev_context *devc;
ae1bc1cc 1102 struct sr_scpi_dev_inst *scpi;
29d957ce 1103
29d957ce
UH		 1104 devc = sdi->priv;
1105
f4816ac6
ML		 1106 if (sdi->status != SR_ST_ACTIVE) {
1107 sr_err("Device inactive, can't stop acquisition.");
1108 return SR_ERR;
1109 }
1110
bee2b016 1111 std_session_send_df_end(sdi);
b751cf7a 1112
702f42e8
ML		 1113 g_slist_free(devc->enabled_channels);
1114 devc->enabled_channels = NULL;
ae1bc1cc 1115 scpi = sdi->conn;
102f1239 1116 sr_scpi_source_remove(sdi->session, scpi);
f4816ac6
ML		 1117
1118 return SR_OK;
1119}
1120
dd5c48a6 1121static struct sr_dev_driver rigol_ds_driver_info = {
3086efdd
ML		 1122 .name = "rigol-ds",
1123 .longname = "Rigol DS",
f4816ac6 1124 .api_version = 1,
c2fdcc25 1125 .init = std_init,
700d6b64 1126 .cleanup = std_cleanup,
6078d2c9 1127 .scan = scan,
c01bf34c 1128 .dev_list = std_dev_list,
3b412e3a 1129 .dev_clear = dev_clear,
d62d7ad1 1130 .config_get = config_get,
035a1078 1131 .config_set = config_set,
a1c743fc 1132 .config_list = config_list,
6078d2c9
UH		 1133 .dev_open = dev_open,
1134 .dev_close = dev_close,
254dd102
BV		 1135 .dev_acquisition_start = dev_acquisition_start,
1136 .dev_acquisition_stop = dev_acquisition_stop,
41812aca 1137 .context = NULL,
f4816ac6 1138};
dd5c48a6 1139SR_REGISTER_DEV_DRIVER(rigol_ds_driver_info);
Hardware access and backend lib