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f2cd2deb FS |
1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2020 Florian Schmidt <schmidt_florian@gmx.de> | |
5 | * Copyright (C) 2013 Marcus Comstedt <marcus@mc.pp.se> | |
6 | * Copyright (C) 2013 Bert Vermeulen <bert@biot.com> | |
7 | * Copyright (C) 2012 Joel Holdsworth <joel@airwebreathe.org.uk> | |
8 | * | |
9 | * This program is free software: you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation, either version 3 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #include <config.h> | |
a7740b06 | 24 | |
f2cd2deb | 25 | #include <libsigrok/libsigrok.h> |
a7740b06 GS |
26 | #include <string.h> |
27 | ||
f2cd2deb FS |
28 | #include "libsigrok-internal.h" |
29 | #include "protocol.h" | |
30 | ||
f2cd2deb | 31 | #define UC_FIRMWARE "kingst-la-%04x.fw" |
9de389b1 KG |
32 | #define FPGA_FW_LA2016 "kingst-la2016-fpga.bitstream" |
33 | #define FPGA_FW_LA2016A "kingst-la2016a1-fpga.bitstream" | |
8b172e78 KG |
34 | #define FPGA_FW_LA1016 "kingst-la1016-fpga.bitstream" |
35 | #define FPGA_FW_LA1016A "kingst-la1016a1-fpga.bitstream" | |
f2cd2deb | 36 | |
96dc954e | 37 | /* USB vendor class control requests, executed by the Cypress FX2 MCU. */ |
84fe94bd | 38 | #define CMD_FPGA_ENABLE 0x10 |
96dc954e GS |
39 | #define CMD_FPGA_SPI 0x20 /* R/W access to FPGA registers via SPI. */ |
40 | #define CMD_BULK_START 0x30 /* Start sample data download via USB EP6 IN. */ | |
41 | #define CMD_BULK_RESET 0x38 /* Flush FIFO of FX2 USB EP6 IN. */ | |
42 | #define CMD_FPGA_INIT 0x50 /* Used before and after FPGA bitstream upload. */ | |
43 | #define CMD_KAUTH 0x60 /* Communicate to auth IC (U10). Not used. */ | |
44 | #define CMD_EEPROM 0xa2 /* R/W access to EEPROM content. */ | |
00849545 | 45 | |
42f6dd55 | 46 | /* |
96dc954e GS |
47 | * FPGA register addresses (base addresses when registers span multiple |
48 | * bytes, in that case data is kept in little endian format). Passed to | |
49 | * CMD_FPGA_SPI requests. The FX2 MCU transparently handles the detail | |
50 | * of SPI transfers encoding the read (1) or write (0) direction in the | |
51 | * MSB of the address field. There are some 60 byte-wide FPGA registers. | |
d6f89d4b GS |
52 | * |
53 | * Unfortunately the FPGA registers change their meaning between the | |
54 | * read and write directions of access, or exclusively provide one of | |
55 | * these directions and not the other. This is an arbitrary vendor's | |
56 | * choice, there is nothing which the sigrok driver could do about it. | |
57 | * Values written to registers typically cannot get read back, neither | |
58 | * verified after writing a configuration, nor queried upon startup for | |
59 | * automatic detection of the current configuration. Neither appear to | |
60 | * be there echo registers for presence and communication checks, nor | |
61 | * version identifying registers, as far as we know. | |
42f6dd55 | 62 | */ |
96dc954e GS |
63 | #define REG_RUN 0x00 /* Read capture status, write start capture. */ |
64 | #define REG_PWM_EN 0x02 /* User PWM channels on/off. */ | |
65 | #define REG_CAPT_MODE 0x03 /* Write 0x00 capture to SDRAM, 0x01 streaming. */ | |
66 | #define REG_BULK 0x08 /* Write start addr, byte count to download samples. */ | |
67 | #define REG_SAMPLING 0x10 /* Write capture config, read capture SDRAM location. */ | |
68 | #define REG_TRIGGER 0x20 /* write level and edge trigger config. */ | |
69 | #define REG_THRESHOLD 0x68 /* Write PWM config to setup input threshold DAC. */ | |
70 | #define REG_PWM1 0x70 /* Write config for user PWM1. */ | |
71 | #define REG_PWM2 0x78 /* Write config for user PWM2. */ | |
f2cd2deb | 72 | |
852c7d14 GS |
73 | /* Bit patterns to write to REG_RUN, setup run mode. */ |
74 | #define RUNMODE_HALT 0x00 | |
75 | #define RUNMODE_RUN 0x03 | |
76 | ||
b711fd8e GS |
77 | /* Bit patterns when reading from REG_RUN, get run state. */ |
78 | #define RUNSTATE_IDLE_BIT (1UL << 0) | |
79 | #define RUNSTATE_DRAM_BIT (1UL << 1) | |
80 | #define RUNSTATE_TRGD_BIT (1UL << 2) | |
81 | #define RUNSTATE_POST_BIT (1UL << 3) | |
82 | ||
f2cd2deb | 83 | static int ctrl_in(const struct sr_dev_inst *sdi, |
1ed93110 GS |
84 | uint8_t bRequest, uint16_t wValue, uint16_t wIndex, |
85 | void *data, uint16_t wLength) | |
f2cd2deb FS |
86 | { |
87 | struct sr_usb_dev_inst *usb; | |
88 | int ret; | |
89 | ||
90 | usb = sdi->conn; | |
91 | ||
411ad77c GS |
92 | ret = libusb_control_transfer(usb->devhdl, |
93 | LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_IN, | |
94 | bRequest, wValue, wIndex, data, wLength, | |
95 | DEFAULT_TIMEOUT_MS); | |
96 | if (ret != wLength) { | |
91f73872 GS |
97 | sr_dbg("USB ctrl in: %d bytes, req %d val %#x idx %d: %s.", |
98 | wLength, bRequest, wValue, wIndex, | |
99 | libusb_error_name(ret)); | |
100 | sr_err("Cannot read %d bytes from USB: %s.", | |
101 | wLength, libusb_error_name(ret)); | |
f2cd2deb FS |
102 | return SR_ERR; |
103 | } | |
104 | ||
105 | return SR_OK; | |
106 | } | |
107 | ||
108 | static int ctrl_out(const struct sr_dev_inst *sdi, | |
1ed93110 GS |
109 | uint8_t bRequest, uint16_t wValue, uint16_t wIndex, |
110 | void *data, uint16_t wLength) | |
f2cd2deb FS |
111 | { |
112 | struct sr_usb_dev_inst *usb; | |
113 | int ret; | |
114 | ||
115 | usb = sdi->conn; | |
116 | ||
411ad77c GS |
117 | ret = libusb_control_transfer(usb->devhdl, |
118 | LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT, | |
119 | bRequest, wValue, wIndex, data, wLength, | |
120 | DEFAULT_TIMEOUT_MS); | |
121 | if (ret != wLength) { | |
91f73872 GS |
122 | sr_dbg("USB ctrl out: %d bytes, req %d val %#x idx %d: %s.", |
123 | wLength, bRequest, wValue, wIndex, | |
124 | libusb_error_name(ret)); | |
125 | sr_err("Cannot write %d bytes to USB: %s.", | |
126 | wLength, libusb_error_name(ret)); | |
f2cd2deb FS |
127 | return SR_ERR; |
128 | } | |
129 | ||
130 | return SR_OK; | |
131 | } | |
132 | ||
d6f89d4b GS |
133 | /* |
134 | * Check the necessity for FPGA bitstream upload, because another upload | |
135 | * would take some 600ms which is undesirable after program startup. Try | |
136 | * to access some FPGA registers and check the values' plausibility. The | |
137 | * check should fail on the safe side, request another upload when in | |
138 | * doubt. A positive response (the request to continue operation with the | |
139 | * currently active bitstream) should be conservative. Accessing multiple | |
140 | * registers is considered cheap compared to the cost of bitstream upload. | |
141 | * | |
142 | * It helps though that both the vendor software and the sigrok driver | |
143 | * use the same bundle of MCU firmware and FPGA bitstream for any of the | |
144 | * supported models. We don't expect to successfully communicate to the | |
145 | * device yet disagree on its protocol. Ideally we would access version | |
146 | * identifying registers for improved robustness, but are not aware of | |
147 | * any. A bitstream reload can always be forced by a power cycle. | |
148 | */ | |
149 | static int check_fpga_bitstream(const struct sr_dev_inst *sdi) | |
150 | { | |
151 | uint8_t init_rsp; | |
152 | int ret; | |
153 | uint16_t run_state; | |
154 | uint8_t pwm_en; | |
155 | size_t read_len; | |
156 | uint8_t buff[sizeof(run_state)]; | |
157 | const uint8_t *rdptr; | |
158 | ||
159 | sr_dbg("Checking operation of the FPGA bitstream."); | |
160 | ||
852c7d14 | 161 | init_rsp = ~0; |
d6f89d4b GS |
162 | ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &init_rsp, sizeof(init_rsp)); |
163 | if (ret != SR_OK || init_rsp != 0) { | |
164 | sr_dbg("FPGA init query failed, or unexpected response."); | |
165 | return SR_ERR_IO; | |
166 | } | |
167 | ||
168 | read_len = sizeof(run_state); | |
169 | ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, buff, read_len); | |
170 | if (ret != SR_OK) { | |
171 | sr_dbg("FPGA register access failed (run state)."); | |
172 | return SR_ERR_IO; | |
173 | } | |
174 | rdptr = buff; | |
175 | run_state = read_u16le_inc(&rdptr); | |
176 | sr_spew("FPGA register: run state 0x%04x.", run_state); | |
177 | if (run_state && (run_state & 0x3) != 0x1) { | |
178 | sr_dbg("Unexpected FPGA register content (run state)."); | |
179 | return SR_ERR_DATA; | |
180 | } | |
181 | if (run_state && (run_state & ~0xf) != 0x85e0) { | |
182 | sr_dbg("Unexpected FPGA register content (run state)."); | |
183 | return SR_ERR_DATA; | |
184 | } | |
185 | ||
186 | read_len = sizeof(pwm_en); | |
187 | ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, buff, read_len); | |
188 | if (ret != SR_OK) { | |
189 | sr_dbg("FPGA register access failed (PWM enable)."); | |
190 | return SR_ERR_IO; | |
191 | } | |
192 | rdptr = buff; | |
193 | pwm_en = read_u8_inc(&rdptr); | |
194 | sr_spew("FPGA register: PWM enable 0x%02x.", pwm_en); | |
195 | if ((pwm_en & 0x3) != 0x0) { | |
196 | sr_dbg("Unexpected FPGA register content (PWM enable)."); | |
197 | return SR_ERR_DATA; | |
198 | } | |
199 | ||
200 | sr_info("Could re-use current FPGA bitstream. No upload required."); | |
201 | return SR_OK; | |
202 | } | |
203 | ||
1ed93110 GS |
204 | static int upload_fpga_bitstream(const struct sr_dev_inst *sdi, |
205 | const char *bitstream_fname) | |
f2cd2deb FS |
206 | { |
207 | struct drv_context *drvc; | |
208 | struct sr_usb_dev_inst *usb; | |
209 | struct sr_resource bitstream; | |
b0d0131e | 210 | uint32_t bitstream_size; |
c3d40037 HK |
211 | uint8_t buffer[sizeof(uint32_t)]; |
212 | uint8_t *wrptr; | |
f2cd2deb | 213 | uint8_t block[4096]; |
3f48ab02 FS |
214 | int len, act_len; |
215 | unsigned int pos; | |
f2cd2deb | 216 | int ret; |
b0d0131e | 217 | unsigned int zero_pad_to; |
f2cd2deb FS |
218 | |
219 | drvc = sdi->driver->context; | |
220 | usb = sdi->conn; | |
221 | ||
9de389b1 | 222 | sr_info("Uploading FPGA bitstream '%s'.", bitstream_fname); |
f2cd2deb | 223 | |
411ad77c GS |
224 | ret = sr_resource_open(drvc->sr_ctx, &bitstream, |
225 | SR_RESOURCE_FIRMWARE, bitstream_fname); | |
f2cd2deb | 226 | if (ret != SR_OK) { |
91f73872 | 227 | sr_err("Cannot find FPGA bitstream %s.", bitstream_fname); |
f2cd2deb FS |
228 | return ret; |
229 | } | |
230 | ||
b0d0131e | 231 | bitstream_size = (uint32_t)bitstream.size; |
c3d40037 | 232 | wrptr = buffer; |
b0d0131e | 233 | write_u32le_inc(&wrptr, bitstream_size); |
411ad77c GS |
234 | ret = ctrl_out(sdi, CMD_FPGA_INIT, 0x00, 0, buffer, wrptr - buffer); |
235 | if (ret != SR_OK) { | |
91f73872 | 236 | sr_err("Cannot initiate FPGA bitstream upload."); |
f2cd2deb FS |
237 | sr_resource_close(drvc->sr_ctx, &bitstream); |
238 | return ret; | |
239 | } | |
b0d0131e GS |
240 | zero_pad_to = bitstream_size; |
241 | zero_pad_to += LA2016_EP2_PADDING - 1; | |
242 | zero_pad_to /= LA2016_EP2_PADDING; | |
243 | zero_pad_to *= LA2016_EP2_PADDING; | |
f2cd2deb FS |
244 | |
245 | pos = 0; | |
246 | while (1) { | |
3f48ab02 | 247 | if (pos < bitstream.size) { |
411ad77c GS |
248 | len = (int)sr_resource_read(drvc->sr_ctx, &bitstream, |
249 | block, sizeof(block)); | |
3f48ab02 | 250 | if (len < 0) { |
91f73872 | 251 | sr_err("Cannot read FPGA bitstream."); |
3f48ab02 FS |
252 | sr_resource_close(drvc->sr_ctx, &bitstream); |
253 | return SR_ERR; | |
254 | } | |
255 | } else { | |
96dc954e | 256 | /* Zero-pad until 'zero_pad_to'. */ |
3f48ab02 FS |
257 | len = zero_pad_to - pos; |
258 | if ((unsigned)len > sizeof(block)) | |
259 | len = sizeof(block); | |
260 | memset(&block, 0, len); | |
f2cd2deb FS |
261 | } |
262 | if (len == 0) | |
263 | break; | |
264 | ||
852c7d14 | 265 | ret = libusb_bulk_transfer(usb->devhdl, USB_EP_FPGA_BITSTREAM, |
1ed93110 | 266 | &block[0], len, &act_len, DEFAULT_TIMEOUT_MS); |
f2cd2deb | 267 | if (ret != 0) { |
91f73872 GS |
268 | sr_dbg("Cannot write FPGA bitstream, block %#x len %d: %s.", |
269 | pos, (int)len, libusb_error_name(ret)); | |
f2cd2deb FS |
270 | ret = SR_ERR; |
271 | break; | |
272 | } | |
273 | if (act_len != len) { | |
91f73872 GS |
274 | sr_dbg("Short write for FPGA bitstream, block %#x len %d: got %d.", |
275 | pos, (int)len, act_len); | |
f2cd2deb FS |
276 | ret = SR_ERR; |
277 | break; | |
278 | } | |
279 | pos += len; | |
280 | } | |
281 | sr_resource_close(drvc->sr_ctx, &bitstream); | |
5eb1b63d | 282 | if (ret != SR_OK) |
f2cd2deb | 283 | return ret; |
91f73872 GS |
284 | sr_info("FPGA bitstream upload (%" PRIu64 " bytes) done.", |
285 | bitstream.size); | |
f2cd2deb | 286 | |
d6f89d4b GS |
287 | return SR_OK; |
288 | } | |
289 | ||
290 | static int enable_fpga_bitstream(const struct sr_dev_inst *sdi) | |
291 | { | |
292 | int ret; | |
411ad77c | 293 | uint8_t resp; |
d6f89d4b | 294 | |
411ad77c GS |
295 | ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &resp, sizeof(resp)); |
296 | if (ret != SR_OK) { | |
91f73872 | 297 | sr_err("Cannot read response after FPGA bitstream upload."); |
f2cd2deb FS |
298 | return ret; |
299 | } | |
411ad77c | 300 | if (resp != 0) { |
91f73872 | 301 | sr_err("Unexpected FPGA bitstream upload response, got 0x%02x, want 0.", |
411ad77c | 302 | resp); |
3f48ab02 FS |
303 | return SR_ERR; |
304 | } | |
852c7d14 | 305 | g_usleep(30 * 1000); |
f2cd2deb | 306 | |
411ad77c GS |
307 | ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x01, 0, NULL, 0); |
308 | if (ret != SR_OK) { | |
91f73872 | 309 | sr_err("Cannot enable FPGA after bitstream upload."); |
f2cd2deb FS |
310 | return ret; |
311 | } | |
852c7d14 | 312 | g_usleep(40 * 1000); |
d6f89d4b | 313 | |
f2cd2deb FS |
314 | return SR_OK; |
315 | } | |
316 | ||
317 | static int set_threshold_voltage(const struct sr_dev_inst *sdi, float voltage) | |
318 | { | |
319 | struct dev_context *devc; | |
f2cd2deb | 320 | int ret; |
1ed93110 | 321 | uint16_t duty_R79, duty_R56; |
f2ad79d1 KG |
322 | uint8_t buf[2 * sizeof(uint16_t)]; |
323 | uint8_t *wrptr; | |
324 | ||
084d6b92 GS |
325 | devc = sdi->priv; |
326 | ||
96dc954e | 327 | /* Clamp threshold setting to valid range for LA2016. */ |
f2ad79d1 KG |
328 | if (voltage > 4.0) { |
329 | voltage = 4.0; | |
1ed93110 | 330 | } else if (voltage < -4.0) { |
f2ad79d1 KG |
331 | voltage = -4.0; |
332 | } | |
333 | ||
334 | /* | |
96dc954e GS |
335 | * Two PWM output channels feed one DAC which generates a bias |
336 | * voltage, which offsets the input probe's voltage level, and | |
337 | * in combination with the FPGA pins' fixed threshold result in | |
338 | * a programmable input threshold from the user's perspective. | |
339 | * The PWM outputs can be seen on R79 and R56 respectively, the | |
340 | * frequency is 100kHz and the duty cycle varies. The R79 PWM | |
341 | * uses three discrete settings. The R56 PWM varies with desired | |
342 | * thresholds and depends on the R79 PWM configuration. See the | |
343 | * schematics comments which discuss the formulae. | |
f2ad79d1 KG |
344 | */ |
345 | if (voltage >= 2.9) { | |
96dc954e | 346 | duty_R79 = 0; /* PWM off (0V). */ |
f2ad79d1 | 347 | duty_R56 = (uint16_t)(302 * voltage - 363); |
c34f4a89 | 348 | } else if (voltage > -0.4) { |
96dc954e | 349 | duty_R79 = 0x00f2; /* 25% duty cycle. */ |
f2ad79d1 | 350 | duty_R56 = (uint16_t)(302 * voltage + 121); |
c34f4a89 GS |
351 | } else { |
352 | duty_R79 = 0x02d7; /* 72% duty cycle. */ | |
353 | duty_R56 = (uint16_t)(302 * voltage + 1090); | |
f2ad79d1 KG |
354 | } |
355 | ||
96dc954e | 356 | /* Clamp duty register values to sensible limits. */ |
f2ad79d1 KG |
357 | if (duty_R56 < 10) { |
358 | duty_R56 = 10; | |
1ed93110 | 359 | } else if (duty_R56 > 1100) { |
f2ad79d1 KG |
360 | duty_R56 = 1100; |
361 | } | |
362 | ||
91f73872 GS |
363 | sr_dbg("Set threshold voltage %.2fV.", voltage); |
364 | sr_dbg("Duty cycle values: R56 0x%04x, R79 0x%04x.", duty_R56, duty_R79); | |
f2ad79d1 KG |
365 | |
366 | wrptr = buf; | |
367 | write_u16le_inc(&wrptr, duty_R56); | |
368 | write_u16le_inc(&wrptr, duty_R79); | |
369 | ||
370 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_THRESHOLD, 0, buf, wrptr - buf); | |
f2cd2deb | 371 | if (ret != SR_OK) { |
91f73872 | 372 | sr_err("Cannot set threshold voltage %.2fV.", voltage); |
f2cd2deb FS |
373 | return ret; |
374 | } | |
375 | devc->threshold_voltage = voltage; | |
376 | ||
377 | return SR_OK; | |
378 | } | |
379 | ||
86d77b75 | 380 | static int enable_pwm(const struct sr_dev_inst *sdi, gboolean p1, gboolean p2) |
f2cd2deb FS |
381 | { |
382 | struct dev_context *devc; | |
383 | uint8_t cfg; | |
384 | int ret; | |
385 | ||
386 | devc = sdi->priv; | |
f2cd2deb | 387 | |
86d77b75 GS |
388 | cfg = 0; |
389 | if (p1) | |
390 | cfg |= 1U << 0; | |
391 | if (p2) | |
392 | cfg |= 1U << 1; | |
91f73872 | 393 | sr_dbg("Set PWM enable %d %d. Config 0x%02x.", p1, p2, cfg); |
86d77b75 | 394 | |
42f6dd55 | 395 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_PWM_EN, 0, &cfg, sizeof(cfg)); |
f2cd2deb | 396 | if (ret != SR_OK) { |
91f73872 | 397 | sr_err("Cannot setup PWM enabled state."); |
f2cd2deb FS |
398 | return ret; |
399 | } | |
86d77b75 | 400 | |
f2cd2deb FS |
401 | devc->pwm_setting[0].enabled = (p1) ? 1 : 0; |
402 | devc->pwm_setting[1].enabled = (p2) ? 1 : 0; | |
403 | ||
404 | return SR_OK; | |
405 | } | |
406 | ||
86d77b75 | 407 | static int configure_pwm(const struct sr_dev_inst *sdi, uint8_t which, |
1ed93110 | 408 | float freq, float duty) |
f2cd2deb | 409 | { |
86d77b75 GS |
410 | static uint8_t ctrl_reg_tab[] = { REG_PWM1, REG_PWM2, }; |
411 | ||
f2cd2deb | 412 | struct dev_context *devc; |
86d77b75 GS |
413 | uint8_t ctrl_reg; |
414 | struct pwm_setting_dev cfg; | |
415 | struct pwm_setting *setting; | |
f2cd2deb | 416 | int ret; |
c3d40037 HK |
417 | uint8_t buf[2 * sizeof(uint32_t)]; |
418 | uint8_t *wrptr; | |
f2cd2deb FS |
419 | |
420 | devc = sdi->priv; | |
421 | ||
86d77b75 | 422 | if (which < 1 || which > ARRAY_SIZE(ctrl_reg_tab)) { |
91f73872 | 423 | sr_err("Invalid PWM channel: %d.", which); |
f2cd2deb FS |
424 | return SR_ERR; |
425 | } | |
86d77b75 | 426 | if (freq < 0 || freq > MAX_PWM_FREQ) { |
91f73872 | 427 | sr_err("Too high a PWM frequency: %.1f.", freq); |
f2cd2deb FS |
428 | return SR_ERR; |
429 | } | |
86d77b75 | 430 | if (duty < 0 || duty > 100) { |
91f73872 | 431 | sr_err("Invalid PWM duty cycle: %f.", duty); |
f2cd2deb FS |
432 | return SR_ERR; |
433 | } | |
434 | ||
86d77b75 | 435 | memset(&cfg, 0, sizeof(cfg)); |
f2cd2deb FS |
436 | cfg.period = (uint32_t)(PWM_CLOCK / freq); |
437 | cfg.duty = (uint32_t)(0.5f + (cfg.period * duty / 100.)); | |
91f73872 | 438 | sr_dbg("Set PWM%d period %d, duty %d.", which, cfg.period, cfg.duty); |
f2cd2deb | 439 | |
86d77b75 | 440 | ctrl_reg = ctrl_reg_tab[which - 1]; |
c3d40037 HK |
441 | wrptr = buf; |
442 | write_u32le_inc(&wrptr, cfg.period); | |
443 | write_u32le_inc(&wrptr, cfg.duty); | |
86d77b75 | 444 | ret = ctrl_out(sdi, CMD_FPGA_SPI, ctrl_reg, 0, buf, wrptr - buf); |
f2cd2deb | 445 | if (ret != SR_OK) { |
91f73872 GS |
446 | sr_err("Cannot setup PWM%d configuration %d %d.", |
447 | which, cfg.period, cfg.duty); | |
f2cd2deb FS |
448 | return ret; |
449 | } | |
86d77b75 | 450 | |
f2cd2deb FS |
451 | setting = &devc->pwm_setting[which - 1]; |
452 | setting->freq = freq; | |
453 | setting->duty = duty; | |
f2cd2deb FS |
454 | |
455 | return SR_OK; | |
456 | } | |
457 | ||
458 | static int set_defaults(const struct sr_dev_inst *sdi) | |
459 | { | |
460 | struct dev_context *devc; | |
461 | int ret; | |
462 | ||
463 | devc = sdi->priv; | |
464 | ||
f2cd2deb FS |
465 | ret = set_threshold_voltage(sdi, devc->threshold_voltage); |
466 | if (ret) | |
467 | return ret; | |
468 | ||
86d77b75 | 469 | ret = enable_pwm(sdi, FALSE, FALSE); |
f2cd2deb FS |
470 | if (ret) |
471 | return ret; | |
472 | ||
86d77b75 | 473 | ret = configure_pwm(sdi, 1, SR_KHZ(1), 50); |
f2cd2deb FS |
474 | if (ret) |
475 | return ret; | |
476 | ||
86d77b75 | 477 | ret = configure_pwm(sdi, 2, SR_KHZ(100), 50); |
f2cd2deb FS |
478 | if (ret) |
479 | return ret; | |
480 | ||
86d77b75 | 481 | ret = enable_pwm(sdi, TRUE, TRUE); |
f2cd2deb FS |
482 | if (ret) |
483 | return ret; | |
484 | ||
485 | return SR_OK; | |
486 | } | |
487 | ||
ea436ba7 GS |
488 | static uint16_t get_channels_mask(const struct sr_dev_inst *sdi) |
489 | { | |
490 | uint16_t channels; | |
491 | GSList *l; | |
492 | struct sr_channel *ch; | |
493 | ||
494 | channels = 0; | |
495 | for (l = sdi->channels; l; l = l->next) { | |
496 | ch = l->data; | |
497 | if (ch->type != SR_CHANNEL_LOGIC) | |
498 | continue; | |
499 | if (!ch->enabled) | |
500 | continue; | |
501 | channels |= 1UL << ch->index; | |
502 | } | |
503 | ||
504 | return channels; | |
505 | } | |
506 | ||
f2cd2deb FS |
507 | static int set_trigger_config(const struct sr_dev_inst *sdi) |
508 | { | |
509 | struct dev_context *devc; | |
510 | struct sr_trigger *trigger; | |
66f5f697 | 511 | struct trigger_cfg cfg; |
f2cd2deb FS |
512 | GSList *stages; |
513 | GSList *channel; | |
514 | struct sr_trigger_stage *stage1; | |
515 | struct sr_trigger_match *match; | |
516 | uint16_t ch_mask; | |
517 | int ret; | |
c3d40037 HK |
518 | uint8_t buf[4 * sizeof(uint32_t)]; |
519 | uint8_t *wrptr; | |
f2cd2deb FS |
520 | |
521 | devc = sdi->priv; | |
522 | trigger = sr_session_trigger_get(sdi->session); | |
523 | ||
524 | memset(&cfg, 0, sizeof(cfg)); | |
525 | ||
ea436ba7 | 526 | cfg.channels = get_channels_mask(sdi); |
f2cd2deb FS |
527 | |
528 | if (trigger && trigger->stages) { | |
529 | stages = trigger->stages; | |
530 | stage1 = stages->data; | |
531 | if (stages->next) { | |
532 | sr_err("Only one trigger stage supported for now."); | |
533 | return SR_ERR; | |
534 | } | |
535 | channel = stage1->matches; | |
536 | while (channel) { | |
537 | match = channel->data; | |
cf057ac4 | 538 | ch_mask = 1UL << match->channel->index; |
f2cd2deb FS |
539 | |
540 | switch (match->match) { | |
541 | case SR_TRIGGER_ZERO: | |
542 | cfg.level |= ch_mask; | |
543 | cfg.high_or_falling &= ~ch_mask; | |
544 | break; | |
545 | case SR_TRIGGER_ONE: | |
546 | cfg.level |= ch_mask; | |
547 | cfg.high_or_falling |= ch_mask; | |
548 | break; | |
549 | case SR_TRIGGER_RISING: | |
550 | if ((cfg.enabled & ~cfg.level)) { | |
91f73872 | 551 | sr_err("Device only supports one edge trigger."); |
f2cd2deb FS |
552 | return SR_ERR; |
553 | } | |
554 | cfg.level &= ~ch_mask; | |
555 | cfg.high_or_falling &= ~ch_mask; | |
556 | break; | |
557 | case SR_TRIGGER_FALLING: | |
558 | if ((cfg.enabled & ~cfg.level)) { | |
91f73872 | 559 | sr_err("Device only supports one edge trigger."); |
f2cd2deb FS |
560 | return SR_ERR; |
561 | } | |
562 | cfg.level &= ~ch_mask; | |
563 | cfg.high_or_falling |= ch_mask; | |
564 | break; | |
565 | default: | |
91f73872 | 566 | sr_err("Unknown trigger condition."); |
f2cd2deb FS |
567 | return SR_ERR; |
568 | } | |
569 | cfg.enabled |= ch_mask; | |
570 | channel = channel->next; | |
571 | } | |
572 | } | |
91f73872 GS |
573 | sr_dbg("Set trigger config: " |
574 | "channels 0x%04x, trigger-enabled 0x%04x, " | |
575 | "level-triggered 0x%04x, high/falling 0x%04x.", | |
576 | cfg.channels, cfg.enabled, cfg.level, cfg.high_or_falling); | |
f2cd2deb | 577 | |
cf057ac4 | 578 | devc->trigger_involved = cfg.enabled != 0; |
f2cd2deb | 579 | |
c3d40037 HK |
580 | wrptr = buf; |
581 | write_u32le_inc(&wrptr, cfg.channels); | |
582 | write_u32le_inc(&wrptr, cfg.enabled); | |
583 | write_u32le_inc(&wrptr, cfg.level); | |
584 | write_u32le_inc(&wrptr, cfg.high_or_falling); | |
852c7d14 GS |
585 | /* TODO |
586 | * Comment on this literal 16. Origin, meaning? Cannot be the | |
587 | * register offset, nor the transfer length. Is it a channels | |
588 | * count that is relevant for 16 and 32 channel models? Is it | |
589 | * an obsolete experiment? | |
590 | */ | |
42f6dd55 | 591 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_TRIGGER, 16, buf, wrptr - buf); |
f2cd2deb | 592 | if (ret != SR_OK) { |
91f73872 | 593 | sr_err("Cannot setup trigger configuration."); |
f2cd2deb FS |
594 | return ret; |
595 | } | |
596 | ||
597 | return SR_OK; | |
598 | } | |
599 | ||
600 | static int set_sample_config(const struct sr_dev_inst *sdi) | |
601 | { | |
602 | struct dev_context *devc; | |
f2cd2deb | 603 | double clock_divisor; |
adab4d91 | 604 | uint16_t divider_u16; |
a38f0f5e | 605 | uint64_t limit_samples; |
adab4d91 GS |
606 | uint64_t pre_trigger_samples; |
607 | uint64_t pre_trigger_memory; | |
608 | uint8_t buf[REG_TRIGGER - REG_SAMPLING]; /* Width of REG_SAMPLING. */ | |
c3d40037 | 609 | uint8_t *wrptr; |
adab4d91 | 610 | int ret; |
f2cd2deb FS |
611 | |
612 | devc = sdi->priv; | |
f2cd2deb | 613 | |
8b172e78 | 614 | if (devc->cur_samplerate > devc->max_samplerate) { |
91f73872 GS |
615 | sr_err("Too high a sample rate: %" PRIu64 ".", |
616 | devc->cur_samplerate); | |
ea436ba7 GS |
617 | return SR_ERR_ARG; |
618 | } | |
619 | if (devc->cur_samplerate < MIN_SAMPLE_RATE_LA2016) { | |
620 | sr_err("Too low a sample rate: %" PRIu64 ".", | |
621 | devc->cur_samplerate); | |
622 | return SR_ERR_ARG; | |
f2cd2deb FS |
623 | } |
624 | ||
8b172e78 | 625 | clock_divisor = devc->max_samplerate / (double)devc->cur_samplerate; |
adab4d91 GS |
626 | if (clock_divisor > 65535) |
627 | return SR_ERR_ARG; | |
628 | divider_u16 = (uint16_t)(clock_divisor + 0.5); | |
629 | devc->cur_samplerate = devc->max_samplerate / divider_u16; | |
f2cd2deb | 630 | |
a38f0f5e GS |
631 | ret = sr_sw_limits_get_remain(&devc->sw_limits, |
632 | &limit_samples, NULL, NULL, NULL); | |
633 | if (ret != SR_OK) { | |
634 | sr_err("Cannot get acquisition limits."); | |
635 | return ret; | |
f2cd2deb | 636 | } |
a38f0f5e GS |
637 | if (limit_samples > LA2016_NUM_SAMPLES_MAX) { |
638 | sr_err("Too high a sample depth: %" PRIu64 ".", limit_samples); | |
639 | return SR_ERR_ARG; | |
640 | } | |
641 | if (limit_samples < LA2016_NUM_SAMPLES_MIN) { | |
642 | sr_err("Too low a sample depth: %" PRIu64 ".", limit_samples); | |
643 | return SR_ERR_ARG; | |
ea436ba7 | 644 | } |
f2cd2deb | 645 | |
adab4d91 GS |
646 | /* |
647 | * The acquisition configuration communicates "pre-trigger" | |
648 | * specs in several formats. sigrok users provide a percentage | |
649 | * (0-100%), which translates to a pre-trigger samples count | |
650 | * (assuming that a total samples count limit was specified). | |
651 | * The device supports hardware compression, which depends on | |
652 | * slowly changing input data to be effective. Fast changing | |
653 | * input data may occupy more space in sample memory than its | |
654 | * uncompressed form would. This is why a third parameter can | |
655 | * limit the amount of sample memory to use for pre-trigger | |
656 | * data. Only the upper 24 bits of that memory size spec get | |
657 | * communicated to the device (written to its FPGA register). | |
658 | */ | |
a38f0f5e | 659 | pre_trigger_samples = limit_samples * devc->capture_ratio / 100; |
adab4d91 GS |
660 | pre_trigger_memory = LA2016_PRE_MEM_LIMIT_BASE; |
661 | pre_trigger_memory *= devc->capture_ratio; | |
662 | pre_trigger_memory /= 100; | |
f2cd2deb | 663 | |
adab4d91 | 664 | sr_dbg("Set sample config: %" PRIu64 "kHz, %" PRIu64 " samples.", |
a38f0f5e | 665 | devc->cur_samplerate / 1000, limit_samples); |
adab4d91 GS |
666 | sr_dbg("Capture ratio %" PRIu64 "%%, count %" PRIu64 ", mem %" PRIu64 ".", |
667 | devc->capture_ratio, pre_trigger_samples, pre_trigger_memory); | |
f2cd2deb | 668 | |
a38f0f5e GS |
669 | if (!devc->trigger_involved) { |
670 | sr_dbg("Voiding pre-trigger setup. No trigger involved."); | |
671 | pre_trigger_samples = 1; | |
672 | pre_trigger_memory = 0x100; | |
673 | } | |
674 | ||
b1a17c1a GS |
675 | /* |
676 | * The acquisition configuration occupies a total of 16 bytes: | |
677 | * - A 34bit total samples count limit (up to 10 billions) that | |
678 | * is kept in a 40bit register. | |
679 | * - A 34bit pre-trigger samples count limit (up to 10 billions) | |
680 | * in another 40bit register. | |
681 | * - A 32bit pre-trigger memory space limit (in bytes) of which | |
682 | * the upper 24bits are kept in an FPGA register. | |
683 | * - A 16bit clock divider which gets applied to the maximum | |
684 | * samplerate of the device. | |
685 | * - An 8bit register of unknown meaning. Currently always 0. | |
686 | */ | |
c3d40037 | 687 | wrptr = buf; |
a38f0f5e | 688 | write_u40le_inc(&wrptr, limit_samples); |
b1a17c1a GS |
689 | write_u40le_inc(&wrptr, pre_trigger_samples); |
690 | write_u24le_inc(&wrptr, pre_trigger_memory >> 8); | |
adab4d91 | 691 | write_u16le_inc(&wrptr, divider_u16); |
0d8e1ffc | 692 | write_u8_inc(&wrptr, 0); |
42f6dd55 | 693 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, wrptr - buf); |
f2cd2deb | 694 | if (ret != SR_OK) { |
91f73872 | 695 | sr_err("Cannot setup acquisition configuration."); |
f2cd2deb FS |
696 | return ret; |
697 | } | |
698 | ||
699 | return SR_OK; | |
700 | } | |
701 | ||
96dc954e GS |
702 | /* |
703 | * FPGA register REG_RUN holds the run state (u16le format). Bit fields | |
704 | * of interest: | |
705 | * bit 0: value 1 = idle | |
706 | * bit 1: value 1 = writing to SDRAM | |
707 | * bit 2: value 0 = waiting for trigger, 1 = trigger seen | |
708 | * bit 3: value 0 = pretrigger sampling, 1 = posttrigger sampling | |
709 | * The meaning of other bit fields is unknown. | |
7601dca7 | 710 | * |
96dc954e | 711 | * Typical values in order of appearance during execution: |
b711fd8e GS |
712 | * 0x85e1: idle, no acquisition pending |
713 | * IDLE set, TRGD don't care, POST don't care; DRAM don't care | |
714 | * "In idle state." Takes precedence over all others. | |
96dc954e GS |
715 | * 0x85e2: pre-sampling, samples before the trigger position, |
716 | * when capture ratio > 0% | |
b711fd8e GS |
717 | * IDLE clear, TRGD clear, POST clear; DRAM don't care |
718 | * "Not idle any more, no post yet, not triggered yet." | |
96dc954e GS |
719 | * 0x85ea: pre-sampling complete, now waiting for the trigger |
720 | * (whilst sampling continuously) | |
b711fd8e GS |
721 | * IDLE clear, TRGD clear, POST set; DRAM don't care |
722 | * "Post set thus after pre, not triggered yet" | |
96dc954e | 723 | * 0x85ee: trigger seen, capturing post-trigger samples, running |
b711fd8e GS |
724 | * IDLE clear, TRGD set, POST set; DRAM don't care |
725 | * "Triggered and in post, not idle yet." | |
96dc954e | 726 | * 0x85ed: idle |
b711fd8e GS |
727 | * IDLE set, TRGD don't care, POST don't care; DRAM don't care |
728 | * "In idle state." TRGD/POST don't care, same meaning as above. | |
f2cd2deb | 729 | */ |
b711fd8e GS |
730 | static const uint16_t runstate_mask_idle = RUNSTATE_IDLE_BIT; |
731 | static const uint16_t runstate_patt_idle = RUNSTATE_IDLE_BIT; | |
732 | static const uint16_t runstate_mask_step = | |
733 | RUNSTATE_IDLE_BIT | RUNSTATE_TRGD_BIT | RUNSTATE_POST_BIT; | |
734 | static const uint16_t runstate_patt_pre_trig = 0; | |
735 | static const uint16_t runstate_patt_wait_trig = RUNSTATE_POST_BIT; | |
736 | static const uint16_t runstate_patt_post_trig = | |
737 | RUNSTATE_TRGD_BIT | RUNSTATE_POST_BIT; | |
738 | ||
f2cd2deb FS |
739 | static uint16_t run_state(const struct sr_dev_inst *sdi) |
740 | { | |
21d68fd9 GS |
741 | static uint16_t previous_state; |
742 | ||
f2cd2deb | 743 | int ret; |
21d68fd9 GS |
744 | uint16_t state; |
745 | uint8_t buff[sizeof(state)]; | |
746 | const uint8_t *rdptr; | |
747 | const char *label; | |
f2cd2deb | 748 | |
411ad77c GS |
749 | ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_RUN, 0, buff, sizeof(state)); |
750 | if (ret != SR_OK) { | |
91f73872 | 751 | sr_err("Cannot read run state."); |
f2cd2deb FS |
752 | return ret; |
753 | } | |
21d68fd9 GS |
754 | rdptr = buff; |
755 | state = read_u16le_inc(&rdptr); | |
7601dca7 | 756 | |
96dc954e GS |
757 | /* |
758 | * Avoid flooding the log, only dump values as they change. | |
759 | * The routine is called about every 50ms. | |
7601dca7 | 760 | */ |
b711fd8e GS |
761 | if (state == previous_state) |
762 | return state; | |
763 | ||
764 | previous_state = state; | |
765 | label = NULL; | |
766 | if ((state & runstate_mask_idle) == runstate_patt_idle) | |
767 | label = "idle"; | |
768 | if ((state & runstate_mask_step) == runstate_patt_pre_trig) | |
769 | label = "pre-trigger sampling"; | |
770 | if ((state & runstate_mask_step) == runstate_patt_wait_trig) | |
771 | label = "sampling, waiting for trigger"; | |
772 | if ((state & runstate_mask_step) == runstate_patt_post_trig) | |
773 | label = "post-trigger sampling"; | |
774 | if (label && *label) | |
775 | sr_dbg("Run state: 0x%04x (%s).", state, label); | |
776 | else | |
777 | sr_dbg("Run state: 0x%04x.", state); | |
f2cd2deb FS |
778 | |
779 | return state; | |
780 | } | |
781 | ||
cf057ac4 | 782 | static int la2016_is_idle(const struct sr_dev_inst *sdi) |
c34f4a89 GS |
783 | { |
784 | uint16_t state; | |
785 | ||
786 | state = run_state(sdi); | |
b711fd8e | 787 | if ((state & runstate_mask_idle) == runstate_patt_idle) |
c34f4a89 GS |
788 | return 1; |
789 | ||
790 | return 0; | |
791 | } | |
792 | ||
793 | static int set_run_mode(const struct sr_dev_inst *sdi, uint8_t mode) | |
f2cd2deb FS |
794 | { |
795 | int ret; | |
796 | ||
411ad77c GS |
797 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_RUN, 0, &mode, sizeof(mode)); |
798 | if (ret != SR_OK) { | |
c34f4a89 | 799 | sr_err("Cannot configure run mode %d.", mode); |
f2cd2deb FS |
800 | return ret; |
801 | } | |
802 | ||
803 | return SR_OK; | |
804 | } | |
805 | ||
806 | static int get_capture_info(const struct sr_dev_inst *sdi) | |
807 | { | |
808 | struct dev_context *devc; | |
809 | int ret; | |
c3d40037 HK |
810 | uint8_t buf[3 * sizeof(uint32_t)]; |
811 | const uint8_t *rdptr; | |
f2cd2deb FS |
812 | |
813 | devc = sdi->priv; | |
814 | ||
411ad77c GS |
815 | ret = ctrl_in(sdi, CMD_FPGA_SPI, REG_SAMPLING, 0, buf, sizeof(buf)); |
816 | if (ret != SR_OK) { | |
91f73872 | 817 | sr_err("Cannot read capture info."); |
f2cd2deb FS |
818 | return ret; |
819 | } | |
c3d40037 HK |
820 | |
821 | rdptr = buf; | |
822 | devc->info.n_rep_packets = read_u32le_inc(&rdptr); | |
823 | devc->info.n_rep_packets_before_trigger = read_u32le_inc(&rdptr); | |
824 | devc->info.write_pos = read_u32le_inc(&rdptr); | |
f2cd2deb | 825 | |
cf057ac4 | 826 | sr_dbg("Capture info: n_rep_packets: 0x%08x/%d, before_trigger: 0x%08x/%d, write_pos: 0x%08x/%d.", |
1ed93110 GS |
827 | devc->info.n_rep_packets, devc->info.n_rep_packets, |
828 | devc->info.n_rep_packets_before_trigger, | |
829 | devc->info.n_rep_packets_before_trigger, | |
830 | devc->info.write_pos, devc->info.write_pos); | |
f2cd2deb | 831 | |
852c7d14 GS |
832 | if (devc->info.n_rep_packets % NUM_PACKETS_IN_CHUNK) { |
833 | sr_warn("Unexpected packets count %lu, not a multiple of %d.", | |
834 | (unsigned long)devc->info.n_rep_packets, | |
835 | NUM_PACKETS_IN_CHUNK); | |
91f73872 | 836 | } |
f2cd2deb FS |
837 | |
838 | return SR_OK; | |
839 | } | |
840 | ||
1ed93110 GS |
841 | SR_PRIV int la2016_upload_firmware(struct sr_context *sr_ctx, |
842 | libusb_device *dev, uint16_t product_id) | |
f2cd2deb FS |
843 | { |
844 | char fw_file[1024]; | |
5eb1b63d | 845 | snprintf(fw_file, sizeof(fw_file), UC_FIRMWARE, product_id); |
40a0b2f4 | 846 | return ezusb_upload_firmware(sr_ctx, dev, USB_CONFIGURATION, fw_file); |
f2cd2deb FS |
847 | } |
848 | ||
849 | SR_PRIV int la2016_setup_acquisition(const struct sr_dev_inst *sdi) | |
850 | { | |
851 | struct dev_context *devc; | |
852 | int ret; | |
853 | uint8_t cmd; | |
854 | ||
855 | devc = sdi->priv; | |
856 | ||
857 | ret = set_threshold_voltage(sdi, devc->threshold_voltage); | |
858 | if (ret != SR_OK) | |
859 | return ret; | |
860 | ||
861 | cmd = 0; | |
411ad77c GS |
862 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_CAPT_MODE, 0, &cmd, sizeof(cmd)); |
863 | if (ret != SR_OK) { | |
91f73872 | 864 | sr_err("Cannot send command to stop sampling."); |
f2cd2deb FS |
865 | return ret; |
866 | } | |
867 | ||
868 | ret = set_trigger_config(sdi); | |
869 | if (ret != SR_OK) | |
870 | return ret; | |
871 | ||
872 | ret = set_sample_config(sdi); | |
873 | if (ret != SR_OK) | |
874 | return ret; | |
875 | ||
876 | return SR_OK; | |
877 | } | |
878 | ||
879 | SR_PRIV int la2016_start_acquisition(const struct sr_dev_inst *sdi) | |
880 | { | |
3ebc1cb2 GS |
881 | int ret; |
882 | ||
852c7d14 | 883 | ret = set_run_mode(sdi, RUNMODE_RUN); |
3ebc1cb2 GS |
884 | if (ret != SR_OK) |
885 | return ret; | |
886 | ||
887 | return SR_OK; | |
f2cd2deb FS |
888 | } |
889 | ||
3ebc1cb2 | 890 | static int la2016_stop_acquisition(const struct sr_dev_inst *sdi) |
f2cd2deb | 891 | { |
3ebc1cb2 GS |
892 | int ret; |
893 | ||
852c7d14 | 894 | ret = set_run_mode(sdi, RUNMODE_HALT); |
3ebc1cb2 GS |
895 | if (ret != SR_OK) |
896 | return ret; | |
897 | ||
898 | return SR_OK; | |
f2cd2deb FS |
899 | } |
900 | ||
901 | SR_PRIV int la2016_abort_acquisition(const struct sr_dev_inst *sdi) | |
902 | { | |
3ebc1cb2 GS |
903 | int ret; |
904 | struct dev_context *devc; | |
905 | ||
906 | ret = la2016_stop_acquisition(sdi); | |
907 | if (ret != SR_OK) | |
908 | return ret; | |
909 | ||
910 | devc = sdi ? sdi->priv : NULL; | |
911 | if (devc && devc->transfer) | |
912 | libusb_cancel_transfer(devc->transfer); | |
913 | ||
914 | return SR_OK; | |
f2cd2deb FS |
915 | } |
916 | ||
cf057ac4 | 917 | static int la2016_start_download(const struct sr_dev_inst *sdi, |
1ed93110 | 918 | libusb_transfer_cb_fn cb) |
f2cd2deb FS |
919 | { |
920 | struct dev_context *devc; | |
921 | struct sr_usb_dev_inst *usb; | |
922 | int ret; | |
c3d40037 HK |
923 | uint8_t wrbuf[2 * sizeof(uint32_t)]; |
924 | uint8_t *wrptr; | |
f2cd2deb FS |
925 | uint32_t to_read; |
926 | uint8_t *buffer; | |
927 | ||
928 | devc = sdi->priv; | |
929 | usb = sdi->conn; | |
930 | ||
411ad77c GS |
931 | ret = get_capture_info(sdi); |
932 | if (ret != SR_OK) | |
f2cd2deb FS |
933 | return ret; |
934 | ||
c3d40037 HK |
935 | devc->n_transfer_packets_to_read = devc->info.n_rep_packets / NUM_PACKETS_IN_CHUNK; |
936 | devc->n_bytes_to_read = devc->n_transfer_packets_to_read * TRANSFER_PACKET_LENGTH; | |
f2cd2deb FS |
937 | devc->read_pos = devc->info.write_pos - devc->n_bytes_to_read; |
938 | devc->n_reps_until_trigger = devc->info.n_rep_packets_before_trigger; | |
939 | ||
91f73872 | 940 | sr_dbg("Want to read %u xfer-packets starting from pos %" PRIu32 ".", |
1ed93110 | 941 | devc->n_transfer_packets_to_read, devc->read_pos); |
f2cd2deb | 942 | |
411ad77c GS |
943 | ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0); |
944 | if (ret != SR_OK) { | |
91f73872 | 945 | sr_err("Cannot reset USB bulk state."); |
f2cd2deb FS |
946 | return ret; |
947 | } | |
91f73872 GS |
948 | sr_dbg("Will read from 0x%08lx, 0x%08x bytes.", |
949 | (unsigned long)devc->read_pos, devc->n_bytes_to_read); | |
c3d40037 HK |
950 | wrptr = wrbuf; |
951 | write_u32le_inc(&wrptr, devc->read_pos); | |
952 | write_u32le_inc(&wrptr, devc->n_bytes_to_read); | |
411ad77c GS |
953 | ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_BULK, 0, wrbuf, wrptr - wrbuf); |
954 | if (ret != SR_OK) { | |
91f73872 | 955 | sr_err("Cannot send USB bulk config."); |
f2cd2deb FS |
956 | return ret; |
957 | } | |
411ad77c GS |
958 | ret = ctrl_out(sdi, CMD_BULK_START, 0x00, 0, NULL, 0); |
959 | if (ret != SR_OK) { | |
91f73872 | 960 | sr_err("Cannot unblock USB bulk transfers."); |
f2cd2deb FS |
961 | return ret; |
962 | } | |
963 | ||
96dc954e GS |
964 | /* |
965 | * Pick a buffer size for all USB transfers. The buffer size | |
966 | * must be a multiple of the endpoint packet size. And cannot | |
967 | * exceed a maximum value. | |
968 | */ | |
f2cd2deb | 969 | to_read = devc->n_bytes_to_read; |
96dc954e GS |
970 | if (to_read >= LA2016_USB_BUFSZ) /* Multiple transfers. */ |
971 | to_read = LA2016_USB_BUFSZ; | |
972 | else /* One transfer. */ | |
e847645b | 973 | to_read = (to_read + (LA2016_EP6_PKTSZ-1)) & ~(LA2016_EP6_PKTSZ-1); |
f2cd2deb FS |
974 | buffer = g_try_malloc(to_read); |
975 | if (!buffer) { | |
91f73872 GS |
976 | sr_dbg("USB bulk transfer size %d bytes.", (int)to_read); |
977 | sr_err("Cannot allocate buffer for USB bulk transfer."); | |
f2cd2deb FS |
978 | return SR_ERR_MALLOC; |
979 | } | |
980 | ||
981 | devc->transfer = libusb_alloc_transfer(0); | |
852c7d14 GS |
982 | libusb_fill_bulk_transfer(devc->transfer, |
983 | usb->devhdl, USB_EP_CAPTURE_DATA | LIBUSB_ENDPOINT_IN, | |
411ad77c | 984 | buffer, to_read, cb, (void *)sdi, DEFAULT_TIMEOUT_MS); |
f2cd2deb | 985 | |
411ad77c GS |
986 | ret = libusb_submit_transfer(devc->transfer); |
987 | if (ret != 0) { | |
91f73872 | 988 | sr_err("Cannot submit USB transfer: %s.", libusb_error_name(ret)); |
f2cd2deb FS |
989 | libusb_free_transfer(devc->transfer); |
990 | devc->transfer = NULL; | |
991 | g_free(buffer); | |
992 | return SR_ERR; | |
993 | } | |
994 | ||
995 | return SR_OK; | |
996 | } | |
997 | ||
480efba2 GS |
998 | /* |
999 | * A chunk (received via USB) contains a number of transfers (USB length | |
1000 | * divided by 16) which contain a number of packets (5 per transfer) which | |
1001 | * contain a number of samples (8bit repeat count per 16bit sample data). | |
1002 | */ | |
dfac9592 | 1003 | static void send_chunk(struct sr_dev_inst *sdi, |
480efba2 | 1004 | const uint8_t *packets, size_t num_xfers) |
dfac9592 GS |
1005 | { |
1006 | struct dev_context *devc; | |
480efba2 | 1007 | size_t num_pkts; |
dfac9592 | 1008 | const uint8_t *rp; |
480efba2 GS |
1009 | uint16_t sample_value; |
1010 | size_t repetitions; | |
1011 | uint8_t sample_buff[sizeof(sample_value)]; | |
dfac9592 GS |
1012 | |
1013 | devc = sdi->priv; | |
1014 | ||
a38f0f5e GS |
1015 | /* Ignore incoming USB data after complete sample data download. */ |
1016 | if (devc->download_finished) | |
1017 | return; | |
dfac9592 | 1018 | |
cf057ac4 | 1019 | if (devc->trigger_involved && !devc->trigger_marked && devc->info.n_rep_packets_before_trigger == 0) { |
a38f0f5e | 1020 | feed_queue_logic_send_trigger(devc->feed_queue); |
cf057ac4 | 1021 | devc->trigger_marked = TRUE; |
dfac9592 GS |
1022 | } |
1023 | ||
1024 | rp = packets; | |
480efba2 GS |
1025 | while (num_xfers--) { |
1026 | num_pkts = NUM_PACKETS_IN_CHUNK; | |
1027 | while (num_pkts--) { | |
dfac9592 | 1028 | |
480efba2 | 1029 | sample_value = read_u16le_inc(&rp); |
dfac9592 | 1030 | repetitions = read_u8_inc(&rp); |
dfac9592 | 1031 | |
dfac9592 | 1032 | devc->total_samples += repetitions; |
480efba2 GS |
1033 | |
1034 | write_u16le(sample_buff, sample_value); | |
a38f0f5e GS |
1035 | feed_queue_logic_submit(devc->feed_queue, |
1036 | sample_buff, repetitions); | |
1037 | sr_sw_limits_update_samples_read(&devc->sw_limits, | |
1038 | repetitions); | |
480efba2 | 1039 | |
cf057ac4 GS |
1040 | if (devc->trigger_involved && !devc->trigger_marked) { |
1041 | if (!--devc->n_reps_until_trigger) { | |
a38f0f5e | 1042 | feed_queue_logic_send_trigger(devc->feed_queue); |
cf057ac4 | 1043 | devc->trigger_marked = TRUE; |
91f73872 | 1044 | sr_dbg("Trigger position after %" PRIu64 " samples, %.6fms.", |
1ed93110 GS |
1045 | devc->total_samples, |
1046 | (double)devc->total_samples / devc->cur_samplerate * 1e3); | |
dfac9592 GS |
1047 | } |
1048 | } | |
1049 | } | |
1050 | (void)read_u8_inc(&rp); /* Skip sequence number. */ | |
1051 | } | |
a38f0f5e GS |
1052 | |
1053 | if (!devc->download_finished && sr_sw_limits_check(&devc->sw_limits)) { | |
1054 | sr_dbg("Acquisition limit reached."); | |
1055 | devc->download_finished = TRUE; | |
1056 | } | |
1057 | if (devc->download_finished) { | |
1058 | sr_dbg("Download finished, flushing session feed queue."); | |
1059 | feed_queue_logic_flush(devc->feed_queue); | |
dfac9592 | 1060 | } |
a38f0f5e | 1061 | sr_dbg("Total samples after chunk: %" PRIu64 ".", devc->total_samples); |
dfac9592 GS |
1062 | } |
1063 | ||
1064 | static void LIBUSB_CALL receive_transfer(struct libusb_transfer *transfer) | |
1065 | { | |
1066 | struct sr_dev_inst *sdi; | |
1067 | struct dev_context *devc; | |
1068 | struct sr_usb_dev_inst *usb; | |
a38f0f5e | 1069 | size_t num_xfers; |
dfac9592 GS |
1070 | int ret; |
1071 | ||
1072 | sdi = transfer->user_data; | |
1073 | devc = sdi->priv; | |
1074 | usb = sdi->conn; | |
1075 | ||
1076 | sr_dbg("receive_transfer(): status %s received %d bytes.", | |
1ed93110 | 1077 | libusb_error_name(transfer->status), transfer->actual_length); |
a38f0f5e GS |
1078 | /* |
1079 | * Implementation detail: A USB transfer timeout is not fatal | |
1080 | * here. We just process whatever was received, empty input is | |
1081 | * perfectly acceptable. Reaching (or exceeding) the sw limits | |
1082 | * or exhausting the device's captured data will complete the | |
1083 | * sample data download. | |
1084 | */ | |
1085 | num_xfers = transfer->actual_length / TRANSFER_PACKET_LENGTH; | |
1086 | send_chunk(sdi, transfer->buffer, num_xfers); | |
dfac9592 GS |
1087 | |
1088 | devc->n_bytes_to_read -= transfer->actual_length; | |
1089 | if (devc->n_bytes_to_read) { | |
1090 | uint32_t to_read = devc->n_bytes_to_read; | |
96dc954e GS |
1091 | /* |
1092 | * Determine read size for the next USB transfer. Make | |
1093 | * the buffer size a multiple of the endpoint packet | |
1094 | * size. Don't exceed a maximum value. | |
1095 | */ | |
dfac9592 GS |
1096 | if (to_read >= LA2016_USB_BUFSZ) |
1097 | to_read = LA2016_USB_BUFSZ; | |
96dc954e | 1098 | else |
dfac9592 | 1099 | to_read = (to_read + (LA2016_EP6_PKTSZ-1)) & ~(LA2016_EP6_PKTSZ-1); |
852c7d14 GS |
1100 | libusb_fill_bulk_transfer(transfer, |
1101 | usb->devhdl, USB_EP_CAPTURE_DATA | LIBUSB_ENDPOINT_IN, | |
1102 | transfer->buffer, to_read, | |
dfac9592 GS |
1103 | receive_transfer, (void *)sdi, DEFAULT_TIMEOUT_MS); |
1104 | ||
411ad77c GS |
1105 | ret = libusb_submit_transfer(transfer); |
1106 | if (ret == 0) | |
dfac9592 | 1107 | return; |
91f73872 GS |
1108 | sr_err("Cannot submit another USB transfer: %s.", |
1109 | libusb_error_name(ret)); | |
dfac9592 GS |
1110 | } |
1111 | ||
1112 | g_free(transfer->buffer); | |
1113 | libusb_free_transfer(transfer); | |
cf057ac4 | 1114 | devc->download_finished = TRUE; |
dfac9592 GS |
1115 | } |
1116 | ||
1117 | SR_PRIV int la2016_receive_data(int fd, int revents, void *cb_data) | |
1118 | { | |
1119 | const struct sr_dev_inst *sdi; | |
1120 | struct dev_context *devc; | |
1121 | struct drv_context *drvc; | |
1122 | struct timeval tv; | |
a38f0f5e | 1123 | int ret; |
dfac9592 GS |
1124 | |
1125 | (void)fd; | |
1126 | (void)revents; | |
1127 | ||
1128 | sdi = cb_data; | |
1129 | devc = sdi->priv; | |
1130 | drvc = sdi->driver->context; | |
1131 | ||
a38f0f5e GS |
1132 | /* |
1133 | * Wait for the acquisition to complete in hardware. | |
1134 | * Periodically check a potentially configured msecs timeout. | |
1135 | */ | |
cf057ac4 GS |
1136 | if (!devc->completion_seen) { |
1137 | if (!la2016_is_idle(sdi)) { | |
a38f0f5e GS |
1138 | if (sr_sw_limits_check(&devc->sw_limits)) { |
1139 | devc->sw_limits.limit_msec = 0; | |
1140 | sr_dbg("Limit reached. Stopping acquisition."); | |
1141 | la2016_stop_acquisition(sdi); | |
1142 | } | |
96dc954e | 1143 | /* Not yet ready for sample data download. */ |
dfac9592 GS |
1144 | return TRUE; |
1145 | } | |
a38f0f5e GS |
1146 | sr_dbg("Acquisition completion seen (hardware)."); |
1147 | devc->sw_limits.limit_msec = 0; | |
cf057ac4 GS |
1148 | devc->completion_seen = TRUE; |
1149 | devc->download_finished = FALSE; | |
1150 | devc->trigger_marked = FALSE; | |
dfac9592 | 1151 | devc->total_samples = 0; |
a38f0f5e GS |
1152 | |
1153 | /* Initiate the download of acquired sample data. */ | |
1154 | std_session_send_df_frame_begin(sdi); | |
1155 | ret = la2016_start_download(sdi, receive_transfer); | |
1156 | if (ret != SR_OK) { | |
91f73872 | 1157 | sr_err("Cannot start acquisition data download."); |
dfac9592 GS |
1158 | return FALSE; |
1159 | } | |
91f73872 | 1160 | sr_dbg("Acquisition data download started."); |
dfac9592 GS |
1161 | |
1162 | return TRUE; | |
1163 | } | |
1164 | ||
a38f0f5e | 1165 | /* Handle USB reception. Drives sample data download. */ |
dfac9592 GS |
1166 | tv.tv_sec = tv.tv_usec = 0; |
1167 | libusb_handle_events_timeout(drvc->sr_ctx->libusb_ctx, &tv); | |
1168 | ||
a38f0f5e | 1169 | /* Postprocess completion of sample data download. */ |
cf057ac4 | 1170 | if (devc->download_finished) { |
91f73872 | 1171 | sr_dbg("Download finished, post processing."); |
dfac9592 GS |
1172 | |
1173 | la2016_stop_acquisition(sdi); | |
a38f0f5e | 1174 | usb_source_remove(sdi->session, drvc->sr_ctx); |
dfac9592 GS |
1175 | devc->transfer = NULL; |
1176 | ||
a38f0f5e GS |
1177 | feed_queue_logic_flush(devc->feed_queue); |
1178 | feed_queue_logic_free(devc->feed_queue); | |
1179 | devc->feed_queue = NULL; | |
1180 | std_session_send_df_frame_end(sdi); | |
1181 | std_session_send_df_end(sdi); | |
1182 | ||
91f73872 | 1183 | sr_dbg("Download finished, done post processing."); |
dfac9592 GS |
1184 | } |
1185 | ||
1186 | return TRUE; | |
1187 | } | |
1188 | ||
f2cd2deb FS |
1189 | SR_PRIV int la2016_init_device(const struct sr_dev_inst *sdi) |
1190 | { | |
8b172e78 | 1191 | struct dev_context *devc; |
f2cd2deb | 1192 | uint16_t state; |
9de389b1 | 1193 | uint8_t buf[8]; |
43d2e52f GS |
1194 | const uint8_t *rdptr; |
1195 | uint8_t date_yy, date_mm; | |
1196 | uint8_t dinv_yy, dinv_mm; | |
9de389b1 | 1197 | uint8_t magic; |
d6f89d4b | 1198 | const char *bitstream_fn; |
9de389b1 | 1199 | int ret; |
f2cd2deb | 1200 | |
8b172e78 KG |
1201 | devc = sdi->priv; |
1202 | ||
96dc954e | 1203 | /* |
43d2e52f GS |
1204 | * Four EEPROM bytes at offset 0x20 are the manufacturing date, |
1205 | * year and month in BCD format, followed by inverted values for | |
1206 | * consistency checks. For example bytes 20 04 df fb translate | |
1207 | * to 2020-04. This information can help identify the vintage of | |
1208 | * devices when unknown magic numbers are seen. | |
9de389b1 | 1209 | */ |
43d2e52f GS |
1210 | ret = ctrl_in(sdi, CMD_EEPROM, 0x20, 0, buf, 4 * sizeof(uint8_t)); |
1211 | if (ret != SR_OK) { | |
1212 | sr_err("Cannot read manufacture date in EEPROM."); | |
1ed93110 | 1213 | } else { |
43d2e52f GS |
1214 | rdptr = &buf[0]; |
1215 | date_yy = read_u8_inc(&rdptr); | |
1216 | date_mm = read_u8_inc(&rdptr); | |
1217 | dinv_yy = read_u8_inc(&rdptr); | |
1218 | dinv_mm = read_u8_inc(&rdptr); | |
1219 | sr_info("Manufacture date: 20%02hx-%02hx.", date_yy, date_mm); | |
1220 | if ((date_mm ^ dinv_mm) != 0xff || (date_yy ^ dinv_yy) != 0xff) | |
1221 | sr_warn("Manufacture date fails checksum test."); | |
f2cd2deb | 1222 | } |
f2cd2deb | 1223 | |
9de389b1 | 1224 | /* |
96dc954e GS |
1225 | * Several Kingst logic analyzer devices share the same USB VID |
1226 | * and PID. The product ID determines which MCU firmware to load. | |
1227 | * The MCU firmware provides access to EEPROM content which then | |
1228 | * allows to identify the device model. Which in turn determines | |
1229 | * which FPGA bitstream to load. Eight bytes at offset 0x08 are | |
1230 | * to get inspected. | |
9de389b1 | 1231 | * |
96dc954e GS |
1232 | * EEPROM content for model identification is kept redundantly |
1233 | * in memory. The values are stored in verbatim and in inverted | |
1234 | * form, multiple copies are kept at different offsets. Example | |
1235 | * data: | |
9de389b1 | 1236 | * |
96dc954e GS |
1237 | * magic 0x08 |
1238 | * | ~magic 0xf7 | |
1239 | * | | | |
1240 | * 08f7000008f710ef | |
1241 | * | | | |
1242 | * | ~magic backup | |
1243 | * magic backup | |
9de389b1 | 1244 | * |
96dc954e GS |
1245 | * Exclusively inspecting the magic byte appears to be sufficient, |
1246 | * other fields seem to be 'don't care'. | |
9de389b1 | 1247 | * |
96dc954e GS |
1248 | * magic 2 == LA2016 using "kingst-la2016-fpga.bitstream" |
1249 | * magic 3 == LA1016 using "kingst-la1016-fpga.bitstream" | |
1250 | * magic 8 == LA2016a using "kingst-la2016a1-fpga.bitstream" | |
1251 | * (latest v1.3.0 PCB, perhaps others) | |
1252 | * magic 9 == LA1016a using "kingst-la1016a1-fpga.bitstream" | |
1253 | * (latest v1.3.0 PCB, perhaps others) | |
9de389b1 | 1254 | * |
96dc954e GS |
1255 | * When EEPROM content does not match the hardware configuration |
1256 | * (the board layout), the software may load but yield incorrect | |
1257 | * results (like swapped channels). The FPGA bitstream itself | |
1258 | * will authenticate with IC U10 and fail when its capabilities | |
1259 | * do not match the hardware model. An LA1016 won't become a | |
1260 | * LA2016 by faking its EEPROM content. | |
9de389b1 | 1261 | */ |
9de389b1 | 1262 | if ((ret = ctrl_in(sdi, CMD_EEPROM, 0x08, 0, &buf, sizeof(buf))) != SR_OK) { |
91f73872 | 1263 | sr_err("Cannot read EEPROM device identifier bytes."); |
f2cd2deb FS |
1264 | return ret; |
1265 | } | |
43d2e52f | 1266 | if ((buf[0] ^ buf[1]) == 0xff) { |
96dc954e | 1267 | /* Primary copy of magic passes complement check. */ |
43d2e52f | 1268 | sr_dbg("Using primary copy of device type magic number."); |
9de389b1 | 1269 | magic = buf[0]; |
43d2e52f | 1270 | } else if ((buf[4] ^ buf[5]) == 0xff) { |
96dc954e | 1271 | /* Backup copy of magic passes complement check. */ |
91f73872 | 1272 | sr_dbg("Using backup copy of device type magic number."); |
9de389b1 | 1273 | magic = buf[4]; |
43d2e52f GS |
1274 | } else { |
1275 | sr_err("Cannot find consistent device type identification."); | |
1276 | magic = 0; | |
f2cd2deb | 1277 | } |
91f73872 | 1278 | sr_dbg("Device type: magic number is %hhu.", magic); |
9de389b1 | 1279 | |
96dc954e | 1280 | /* Select the FPGA bitstream depending on the model. */ |
9de389b1 KG |
1281 | switch (magic) { |
1282 | case 2: | |
d6f89d4b | 1283 | bitstream_fn = FPGA_FW_LA2016; |
8b172e78 KG |
1284 | devc->max_samplerate = MAX_SAMPLE_RATE_LA2016; |
1285 | break; | |
1286 | case 3: | |
d6f89d4b | 1287 | bitstream_fn = FPGA_FW_LA1016; |
8b172e78 | 1288 | devc->max_samplerate = MAX_SAMPLE_RATE_LA1016; |
9de389b1 KG |
1289 | break; |
1290 | case 8: | |
d6f89d4b | 1291 | bitstream_fn = FPGA_FW_LA2016A; |
8b172e78 KG |
1292 | devc->max_samplerate = MAX_SAMPLE_RATE_LA2016; |
1293 | break; | |
1294 | case 9: | |
d6f89d4b | 1295 | bitstream_fn = FPGA_FW_LA1016A; |
8b172e78 | 1296 | devc->max_samplerate = MAX_SAMPLE_RATE_LA1016; |
9de389b1 KG |
1297 | break; |
1298 | default: | |
d6f89d4b GS |
1299 | bitstream_fn = NULL; |
1300 | break; | |
1301 | } | |
1302 | if (!bitstream_fn || !*bitstream_fn) { | |
91f73872 | 1303 | sr_err("Cannot identify as one of the supported models."); |
3f48ab02 FS |
1304 | return SR_ERR; |
1305 | } | |
f2cd2deb | 1306 | |
d6f89d4b GS |
1307 | if (check_fpga_bitstream(sdi) != SR_OK) { |
1308 | ret = upload_fpga_bitstream(sdi, bitstream_fn); | |
1309 | if (ret != SR_OK) { | |
1310 | sr_err("Cannot upload FPGA bitstream."); | |
1311 | return ret; | |
1312 | } | |
1313 | } | |
1314 | ret = enable_fpga_bitstream(sdi); | |
9de389b1 | 1315 | if (ret != SR_OK) { |
d6f89d4b | 1316 | sr_err("Cannot enable FPGA bitstream after upload."); |
9de389b1 KG |
1317 | return ret; |
1318 | } | |
1319 | ||
f2cd2deb | 1320 | state = run_state(sdi); |
9de389b1 | 1321 | if (state != 0x85e9) { |
91f73872 | 1322 | sr_warn("Unexpected run state, want 0x85e9, got 0x%04x.", state); |
9de389b1 | 1323 | } |
f2cd2deb | 1324 | |
00849545 | 1325 | if ((ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0)) != SR_OK) { |
91f73872 | 1326 | sr_err("Cannot reset USB bulk transfer."); |
f2cd2deb FS |
1327 | return ret; |
1328 | } | |
9de389b1 | 1329 | |
91f73872 | 1330 | sr_dbg("Device should be initialized."); |
f2cd2deb | 1331 | |
c34f4a89 GS |
1332 | ret = set_defaults(sdi); |
1333 | if (ret != SR_OK) | |
1334 | return ret; | |
1335 | ||
1336 | return SR_OK; | |
f2cd2deb FS |
1337 | } |
1338 | ||
1339 | SR_PRIV int la2016_deinit_device(const struct sr_dev_inst *sdi) | |
1340 | { | |
1341 | int ret; | |
1342 | ||
00849545 | 1343 | if ((ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x00, 0, NULL, 0)) != SR_OK) { |
91f73872 | 1344 | sr_err("Cannot deinitialize device's FPGA."); |
f2cd2deb FS |
1345 | return ret; |
1346 | } | |
1347 | ||
1348 | return SR_OK; | |
1349 | } |