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3b533202 | 1 | /* |
50985c20 | 2 | * This file is part of the libsigrok project. |
3b533202 BV |
3 | * |
4 | * Copyright (C) 2012 Bert Vermeulen <bert@biot.com> | |
5 | * With protocol information from the hantekdso project, | |
6 | * Copyright (C) 2008 Oleg Khudyakov <prcoder@gmail.com> | |
7 | * | |
8 | * This program is free software: you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation, either version 3 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
caeb8d7a UH |
22 | #ifndef LIBSIGROK_HARDWARE_HANTEK_DSO_PROTOCOL_H |
23 | #define LIBSIGROK_HARDWARE_HANTEK_DSO_PROTOCOL_H | |
3b533202 | 24 | |
3544f848 | 25 | #define LOG_PREFIX "hantek-dso" |
cbc6f3b2 | 26 | |
8c971b6e BV |
27 | #define USB_INTERFACE 0 |
28 | #define USB_CONFIGURATION 1 | |
29 | #define DSO_EP_IN 0x86 | |
30 | #define DSO_EP_OUT 0x02 | |
3b533202 BV |
31 | |
32 | /* FX2 renumeration delay in ms */ | |
8c971b6e | 33 | #define MAX_RENUM_DELAY_MS 3000 |
3b533202 | 34 | |
8c971b6e | 35 | #define MAX_CAPTURE_EMPTY 3 |
3b533202 | 36 | |
8c971b6e BV |
37 | #define DEFAULT_VOLTAGE VDIV_500MV |
38 | #define DEFAULT_FRAMESIZE FRAMESIZE_SMALL | |
39 | #define DEFAULT_TIMEBASE TIME_100us | |
11e33196 | 40 | #define DEFAULT_SAMPLERATE SR_KHZ(10) |
8c971b6e BV |
41 | #define DEFAULT_TRIGGER_SOURCE "CH1" |
42 | #define DEFAULT_COUPLING COUPLING_DC | |
95983cc3 | 43 | #define DEFAULT_CAPTURE_RATIO 100 |
8c971b6e BV |
44 | #define DEFAULT_VERT_OFFSET 0.5 |
45 | #define DEFAULT_VERT_TRIGGERPOS 0.5 | |
3b533202 | 46 | |
8c971b6e | 47 | #define MAX_VERT_TRIGGER 0xfe |
3b533202 BV |
48 | |
49 | /* Hantek DSO-specific protocol values */ | |
8c971b6e | 50 | #define EEPROM_CHANNEL_OFFSETS 0x08 |
3b533202 | 51 | |
034accb5 | 52 | /* All models have this for their "fast" mode. */ |
1a46cc62 | 53 | #define FRAMESIZE_SMALL (10 * 1024) |
3b533202 | 54 | |
ab8df2b1 | 55 | #define NUM_CHANNELS 2 |
b3fd0993 | 56 | |
3b533202 BV |
57 | enum control_requests { |
58 | CTRL_READ_EEPROM = 0xa2, | |
59 | CTRL_GETSPEED = 0xb2, | |
60 | CTRL_BEGINCOMMAND = 0xb3, | |
61 | CTRL_SETOFFSET = 0xb4, | |
e98b7f1b | 62 | CTRL_SETRELAYS = 0xb5, |
3b533202 BV |
63 | }; |
64 | ||
65 | enum dso_commands { | |
87f56d01 PM |
66 | CMD_SET_FILTERS = 0x0, |
67 | CMD_SET_TRIGGER_SAMPLERATE = 0x1, | |
68 | CMD_FORCE_TRIGGER = 0x2, | |
69 | CMD_CAPTURE_START = 0x3, | |
70 | CMD_ENABLE_TRIGGER = 0x4, | |
71 | CMD_GET_CHANNELDATA = 0x5, | |
72 | CMD_GET_CAPTURESTATE = 0x6, | |
73 | CMD_SET_VOLTAGE = 0x7, | |
313deed2 | 74 | /* unused */ |
87f56d01 PM |
75 | CMD_SET_LOGICALDATA = 0x8, |
76 | CMD_GET_LOGICALDATA = 0x9, | |
77 | CMD__UNUSED1 = 0xa, | |
ab8df2b1 UH |
78 | /* |
79 | * For the following and other specials please see | |
80 | * http://openhantek.sourceforge.net/doc/namespaceHantek.html#ac1cd181814cf3da74771c29800b39028 | |
81 | */ | |
87f56d01 PM |
82 | CMD_2250_SET_CHANNELS = 0xb, |
83 | CMD_2250_SET_TRIGGERSOURCE = 0xc, | |
84 | CMD_2250_SET_RECORD_LENGTH = 0xd, | |
85 | CMD_2250_SET_SAMPLERATE = 0xe, | |
86 | CMD_2250_SET_TRIGGERPOS_AND_BUFFER = 0xf, | |
3b533202 BV |
87 | }; |
88 | ||
b58fbd99 | 89 | /* Must match the coupling table. */ |
3b533202 BV |
90 | enum couplings { |
91 | COUPLING_AC = 0, | |
92 | COUPLING_DC, | |
2715c0b8 | 93 | /* TODO not used, how to enable? */ |
e98b7f1b | 94 | COUPLING_GND, |
3b533202 BV |
95 | }; |
96 | ||
b58fbd99 | 97 | /* Must match the timebases table. */ |
3b533202 BV |
98 | enum time_bases { |
99 | TIME_10us = 0, | |
100 | TIME_20us, | |
101 | TIME_40us, | |
102 | TIME_100us, | |
103 | TIME_200us, | |
104 | TIME_400us, | |
105 | TIME_1ms, | |
106 | TIME_2ms, | |
107 | TIME_4ms, | |
108 | TIME_10ms, | |
109 | TIME_20ms, | |
110 | TIME_40ms, | |
111 | TIME_100ms, | |
112 | TIME_200ms, | |
e98b7f1b | 113 | TIME_400ms, |
3b533202 BV |
114 | }; |
115 | ||
b58fbd99 | 116 | /* Must match the vdivs table. */ |
313deed2 BV |
117 | enum { |
118 | VDIV_10MV, | |
119 | VDIV_20MV, | |
120 | VDIV_50MV, | |
121 | VDIV_100MV, | |
122 | VDIV_200MV, | |
123 | VDIV_500MV, | |
124 | VDIV_1V, | |
125 | VDIV_2V, | |
126 | VDIV_5V, | |
127 | }; | |
128 | ||
3b533202 BV |
129 | enum trigger_slopes { |
130 | SLOPE_POSITIVE = 0, | |
e98b7f1b | 131 | SLOPE_NEGATIVE, |
3b533202 BV |
132 | }; |
133 | ||
134 | enum trigger_sources { | |
135 | TRIGGER_CH2 = 0, | |
136 | TRIGGER_CH1, | |
3b533202 | 137 | TRIGGER_EXT, |
3b533202 BV |
138 | }; |
139 | ||
3b533202 BV |
140 | enum capturestates { |
141 | CAPTURE_EMPTY = 0, | |
142 | CAPTURE_FILLING = 1, | |
143 | CAPTURE_READY_8BIT = 2, | |
ab8df2b1 | 144 | CAPTURE_READY_2250 = 3, |
3b533202 BV |
145 | CAPTURE_READY_9BIT = 7, |
146 | CAPTURE_TIMEOUT = 127, | |
e98b7f1b | 147 | CAPTURE_UNKNOWN = 255, |
3b533202 BV |
148 | }; |
149 | ||
150 | enum triggermodes { | |
151 | TRIGGERMODE_AUTO, | |
152 | TRIGGERMODE_NORMAL, | |
e98b7f1b | 153 | TRIGGERMODE_SINGLE, |
3b533202 BV |
154 | }; |
155 | ||
156 | enum states { | |
157 | IDLE, | |
158 | NEW_CAPTURE, | |
159 | CAPTURE, | |
a3508e33 BV |
160 | FETCH_DATA, |
161 | STOPPING, | |
3b533202 BV |
162 | }; |
163 | ||
164 | struct dso_profile { | |
165 | /* VID/PID after cold boot */ | |
166 | uint16_t orig_vid; | |
167 | uint16_t orig_pid; | |
168 | /* VID/PID after firmware upload */ | |
169 | uint16_t fw_vid; | |
170 | uint16_t fw_pid; | |
2c240774 UH |
171 | const char *vendor; |
172 | const char *model; | |
034accb5 | 173 | const uint64_t *buffersizes; |
2c240774 | 174 | const char *firmware; |
3b533202 BV |
175 | }; |
176 | ||
269971dd | 177 | struct dev_context { |
62bb8840 | 178 | const struct dso_profile *profile; |
ae88b97b BV |
179 | uint64_t limit_frames; |
180 | uint64_t num_frames; | |
ba7dd8bb | 181 | GSList *enabled_channels; |
3b533202 BV |
182 | /* We can't keep track of an FX2-based device after upgrading |
183 | * the firmware (it re-enumerates into a different device address | |
184 | * after the upgrade) this is like a global lock. No device will open | |
185 | * until a proper delay after the last device was upgraded. | |
186 | */ | |
fc8fe3e3 | 187 | int64_t fw_updated; |
3b533202 BV |
188 | int epin_maxpacketsize; |
189 | int capture_empty_count; | |
3b533202 BV |
190 | int dev_state; |
191 | ||
e749a8cb | 192 | /* Oscilloscope settings. */ |
6deb361b | 193 | uint64_t samplerate; |
3b533202 | 194 | int timebase; |
417412c8 | 195 | gboolean ch_enabled[2]; |
933defaa BV |
196 | int voltage[2]; |
197 | int coupling[2]; | |
3b533202 BV |
198 | // voltage offset (vertical position) |
199 | float voffset_ch1; | |
200 | float voffset_ch2; | |
201 | float voffset_trigger; | |
202 | uint16_t channel_levels[2][9][2]; | |
e749a8cb | 203 | unsigned int framesize; |
933defaa | 204 | gboolean filter[2]; |
3b533202 | 205 | int triggerslope; |
a370ef19 | 206 | char *triggersource; |
d3f14af7 | 207 | uint64_t capture_ratio; |
3b533202 | 208 | int triggermode; |
e749a8cb BV |
209 | |
210 | /* Frame transfer */ | |
211 | unsigned int samp_received; | |
212 | unsigned int samp_buffered; | |
213 | unsigned int trigger_offset; | |
214 | unsigned char *framebuf; | |
3b533202 BV |
215 | }; |
216 | ||
25a0f108 | 217 | SR_PRIV int dso_open(struct sr_dev_inst *sdi); |
3b533202 | 218 | SR_PRIV void dso_close(struct sr_dev_inst *sdi); |
c118080b BV |
219 | SR_PRIV int dso_enable_trigger(const struct sr_dev_inst *sdi); |
220 | SR_PRIV int dso_force_trigger(const struct sr_dev_inst *sdi); | |
221 | SR_PRIV int dso_init(const struct sr_dev_inst *sdi); | |
222 | SR_PRIV int dso_get_capturestate(const struct sr_dev_inst *sdi, | |
e98b7f1b | 223 | uint8_t *capturestate, uint32_t *trigger_offset); |
c118080b | 224 | SR_PRIV int dso_capture_start(const struct sr_dev_inst *sdi); |
69e19dd7 | 225 | SR_PRIV int dso_get_channeldata(const struct sr_dev_inst *sdi, |
e98b7f1b | 226 | libusb_transfer_cb_fn cb); |
11e33196 | 227 | SR_PRIV int dso_set_trigger_samplerate(const struct sr_dev_inst *sdi); |
12f62ce6 | 228 | SR_PRIV int dso_set_voffsets(const struct sr_dev_inst *sdi); |
3b533202 BV |
229 | |
230 | #endif |