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3ba56876 | 1 | /* |
2 | * This file is part of the libsigrok project. | |
3 | * | |
4 | * Copyright (C) 2010-2012 Håvard Espeland <gus@ping.uio.no>, | |
5 | * Copyright (C) 2010 Martin Stensgård <mastensg@ping.uio.no> | |
6 | * Copyright (C) 2010 Carl Henrik Lunde <chlunde@ping.uio.no> | |
9334ed6c | 7 | * Copyright (C) 2020 Gerhard Sittig <gerhard.sittig@gmx.net> |
3ba56876 | 8 | * |
9 | * This program is free software: you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation, either version 3 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
3ba56876 | 23 | #include <config.h> |
24 | #include "protocol.h" | |
25 | ||
3ba56876 | 26 | /* |
7718f3ca GS |
27 | * Channels are labelled 1-16, see this vendor's image of the cable: |
28 | * http://tools.asix.net/img/sigma_sigmacab_pins_720.jpg (TI/TO are | |
29 | * additional trigger in/out signals). | |
3ba56876 | 30 | */ |
31 | static const char *channel_names[] = { | |
32 | "1", "2", "3", "4", "5", "6", "7", "8", | |
33 | "9", "10", "11", "12", "13", "14", "15", "16", | |
34 | }; | |
35 | ||
53a939ab GS |
36 | static const uint32_t scanopts[] = { |
37 | SR_CONF_CONN, | |
38 | }; | |
39 | ||
3ba56876 | 40 | static const uint32_t drvopts[] = { |
41 | SR_CONF_LOGIC_ANALYZER, | |
42 | }; | |
43 | ||
44 | static const uint32_t devopts[] = { | |
45 | SR_CONF_LIMIT_MSEC | SR_CONF_GET | SR_CONF_SET, | |
2f7e529c | 46 | SR_CONF_LIMIT_SAMPLES | SR_CONF_GET | SR_CONF_SET, |
53a939ab | 47 | SR_CONF_CONN | SR_CONF_GET, |
3ba56876 | 48 | SR_CONF_SAMPLERATE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, |
2d8a5089 GS |
49 | SR_CONF_EXTERNAL_CLOCK | SR_CONF_GET | SR_CONF_SET, |
50 | SR_CONF_EXTERNAL_CLOCK_SOURCE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
51 | SR_CONF_CLOCK_EDGE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST, | |
3ba56876 | 52 | SR_CONF_TRIGGER_MATCH | SR_CONF_LIST, |
53 | SR_CONF_CAPTURE_RATIO | SR_CONF_GET | SR_CONF_SET, | |
5cc292b3 | 54 | /* Consider SR_CONF_TRIGGER_PATTERN (SR_T_STRING, GET/SET) support. */ |
3ba56876 | 55 | }; |
56 | ||
2d8a5089 GS |
57 | static const char *ext_clock_edges[] = { |
58 | [SIGMA_CLOCK_EDGE_RISING] = "rising", | |
59 | [SIGMA_CLOCK_EDGE_FALLING] = "falling", | |
60 | [SIGMA_CLOCK_EDGE_EITHER] = "either", | |
61 | }; | |
62 | ||
3ba56876 | 63 | static const int32_t trigger_matches[] = { |
64 | SR_TRIGGER_ZERO, | |
65 | SR_TRIGGER_ONE, | |
66 | SR_TRIGGER_RISING, | |
67 | SR_TRIGGER_FALLING, | |
68 | }; | |
3ba56876 | 69 | |
3553451f | 70 | static void clear_helper(struct dev_context *devc) |
53279f13 | 71 | { |
7fe1f91f | 72 | (void)sigma_force_close(devc); |
53279f13 UH |
73 | } |
74 | ||
3ba56876 | 75 | static int dev_clear(const struct sr_dev_driver *di) |
76 | { | |
9b4d261f GS |
77 | return std_dev_clear_with_callback(di, |
78 | (std_dev_clear_callback)clear_helper); | |
3ba56876 | 79 | } |
80 | ||
53a939ab | 81 | static gboolean bus_addr_in_devices(int bus, int addr, GSList *devs) |
3ba56876 | 82 | { |
53a939ab | 83 | struct sr_usb_dev_inst *usb; |
3ba56876 | 84 | |
53a939ab GS |
85 | for (/* EMPTY */; devs; devs = devs->next) { |
86 | usb = devs->data; | |
87 | if (usb->bus == bus && usb->address == addr) | |
88 | return TRUE; | |
89 | } | |
3ba56876 | 90 | |
53a939ab GS |
91 | return FALSE; |
92 | } | |
3ba56876 | 93 | |
53a939ab GS |
94 | static gboolean known_vid_pid(const struct libusb_device_descriptor *des) |
95 | { | |
9b4d261f GS |
96 | gboolean is_sigma, is_omega; |
97 | ||
53a939ab GS |
98 | if (des->idVendor != USB_VENDOR_ASIX) |
99 | return FALSE; | |
9b4d261f GS |
100 | is_sigma = des->idProduct == USB_PRODUCT_SIGMA; |
101 | is_omega = des->idProduct == USB_PRODUCT_OMEGA; | |
102 | if (!is_sigma && !is_omega) | |
53a939ab GS |
103 | return FALSE; |
104 | return TRUE; | |
105 | } | |
3ba56876 | 106 | |
53a939ab GS |
107 | static GSList *scan(struct sr_dev_driver *di, GSList *options) |
108 | { | |
109 | struct drv_context *drvc; | |
110 | libusb_context *usbctx; | |
111 | const char *conn; | |
112 | GSList *l, *conn_devices; | |
113 | struct sr_config *src; | |
114 | GSList *devices; | |
115 | libusb_device **devlist, *devitem; | |
116 | int bus, addr; | |
117 | struct libusb_device_descriptor des; | |
118 | struct libusb_device_handle *hdl; | |
119 | int ret; | |
120 | char conn_id[20]; | |
121 | char serno_txt[16]; | |
122 | char *end; | |
d7ce5452 | 123 | unsigned long serno_num, serno_pre; |
53a939ab GS |
124 | enum asix_device_type dev_type; |
125 | const char *dev_text; | |
126 | struct sr_dev_inst *sdi; | |
127 | struct dev_context *devc; | |
128 | size_t devidx, chidx; | |
129 | ||
130 | drvc = di->context; | |
131 | usbctx = drvc->sr_ctx->libusb_ctx; | |
132 | ||
133 | /* Find all devices which match an (optional) conn= spec. */ | |
134 | conn = NULL; | |
135 | for (l = options; l; l = l->next) { | |
136 | src = l->data; | |
137 | switch (src->key) { | |
138 | case SR_CONF_CONN: | |
139 | conn = g_variant_get_string(src->data, NULL); | |
140 | break; | |
141 | } | |
3ba56876 | 142 | } |
53a939ab GS |
143 | conn_devices = NULL; |
144 | if (conn) | |
145 | conn_devices = sr_usb_find(usbctx, conn); | |
146 | if (conn && !conn_devices) | |
147 | return NULL; | |
148 | ||
149 | /* Find all ASIX logic analyzers (which match the connection spec). */ | |
150 | devices = NULL; | |
151 | libusb_get_device_list(usbctx, &devlist); | |
152 | for (devidx = 0; devlist[devidx]; devidx++) { | |
153 | devitem = devlist[devidx]; | |
154 | ||
155 | /* Check for connection match if a user spec was given. */ | |
156 | bus = libusb_get_bus_number(devitem); | |
157 | addr = libusb_get_device_address(devitem); | |
158 | if (conn && !bus_addr_in_devices(bus, addr, conn_devices)) | |
159 | continue; | |
160 | snprintf(conn_id, sizeof(conn_id), "%d.%d", bus, addr); | |
161 | ||
162 | /* | |
163 | * Check for known VID:PID pairs. Get the serial number, | |
164 | * to then derive the device type from it. | |
165 | */ | |
166 | libusb_get_device_descriptor(devitem, &des); | |
167 | if (!known_vid_pid(&des)) | |
168 | continue; | |
169 | if (!des.iSerialNumber) { | |
170 | sr_warn("Cannot get serial number (index 0)."); | |
171 | continue; | |
172 | } | |
173 | ret = libusb_open(devitem, &hdl); | |
174 | if (ret < 0) { | |
175 | sr_warn("Cannot open USB device %04x.%04x: %s.", | |
176 | des.idVendor, des.idProduct, | |
177 | libusb_error_name(ret)); | |
178 | continue; | |
179 | } | |
180 | ret = libusb_get_string_descriptor_ascii(hdl, | |
181 | des.iSerialNumber, | |
182 | (unsigned char *)serno_txt, sizeof(serno_txt)); | |
183 | if (ret < 0) { | |
184 | sr_warn("Cannot get serial number (%s).", | |
185 | libusb_error_name(ret)); | |
186 | libusb_close(hdl); | |
187 | continue; | |
188 | } | |
189 | libusb_close(hdl); | |
190 | ||
191 | /* | |
192 | * All ASIX logic analyzers have a serial number, which | |
193 | * reads as a hex number, and tells the device type. | |
194 | */ | |
d7ce5452 | 195 | ret = sr_atoul_base(serno_txt, &serno_num, &end, 16); |
53a939ab GS |
196 | if (ret != SR_OK || !end || *end) { |
197 | sr_warn("Cannot interpret serial number %s.", serno_txt); | |
198 | continue; | |
199 | } | |
200 | dev_type = ASIX_TYPE_NONE; | |
201 | dev_text = NULL; | |
202 | serno_pre = serno_num >> 16; | |
203 | switch (serno_pre) { | |
204 | case 0xa601: | |
205 | dev_type = ASIX_TYPE_SIGMA; | |
206 | dev_text = "SIGMA"; | |
207 | sr_info("Found SIGMA, serno %s.", serno_txt); | |
208 | break; | |
209 | case 0xa602: | |
210 | dev_type = ASIX_TYPE_SIGMA; | |
211 | dev_text = "SIGMA2"; | |
212 | sr_info("Found SIGMA2, serno %s.", serno_txt); | |
213 | break; | |
214 | case 0xa603: | |
215 | dev_type = ASIX_TYPE_OMEGA; | |
216 | dev_text = "OMEGA"; | |
217 | sr_info("Found OMEGA, serno %s.", serno_txt); | |
218 | if (!ASIX_WITH_OMEGA) { | |
219 | sr_warn("OMEGA support is not implemented yet."); | |
220 | continue; | |
221 | } | |
222 | break; | |
223 | default: | |
224 | sr_warn("Unknown serno %s, skipping.", serno_txt); | |
225 | continue; | |
226 | } | |
227 | ||
228 | /* Create a device instance, add it to the result set. */ | |
229 | ||
230 | sdi = g_malloc0(sizeof(*sdi)); | |
231 | devices = g_slist_append(devices, sdi); | |
232 | sdi->status = SR_ST_INITIALIZING; | |
233 | sdi->vendor = g_strdup("ASIX"); | |
234 | sdi->model = g_strdup(dev_text); | |
235 | sdi->serial_num = g_strdup(serno_txt); | |
236 | sdi->connection_id = g_strdup(conn_id); | |
237 | for (chidx = 0; chidx < ARRAY_SIZE(channel_names); chidx++) | |
238 | sr_channel_new(sdi, chidx, SR_CHANNEL_LOGIC, | |
239 | TRUE, channel_names[chidx]); | |
240 | ||
241 | devc = g_malloc0(sizeof(*devc)); | |
242 | sdi->priv = devc; | |
243 | devc->id.vid = des.idVendor; | |
244 | devc->id.pid = des.idProduct; | |
245 | devc->id.serno = serno_num; | |
246 | devc->id.prefix = serno_pre; | |
247 | devc->id.type = dev_type; | |
156b6879 | 248 | sr_sw_limits_init(&devc->limit.config); |
53a939ab | 249 | devc->capture_ratio = 50; |
3d9373af | 250 | devc->use_triggers = FALSE; |
7fe1f91f | 251 | |
53c8a99c GS |
252 | /* Get current hardware configuration (or use defaults). */ |
253 | (void)sigma_fetch_hw_config(sdi); | |
3ba56876 | 254 | } |
53a939ab GS |
255 | libusb_free_device_list(devlist, 1); |
256 | g_slist_free_full(conn_devices, (GDestroyNotify)sr_usb_dev_inst_free); | |
3ba56876 | 257 | |
53a939ab | 258 | return std_scan_complete(di, devices); |
3ba56876 | 259 | } |
260 | ||
3ba56876 | 261 | static int dev_open(struct sr_dev_inst *sdi) |
262 | { | |
263 | struct dev_context *devc; | |
3ba56876 | 264 | |
265 | devc = sdi->priv; | |
266 | ||
53a939ab GS |
267 | if (devc->id.type == ASIX_TYPE_OMEGA && !ASIX_WITH_OMEGA) { |
268 | sr_err("OMEGA support is not implemented yet."); | |
269 | return SR_ERR_NA; | |
270 | } | |
3ba56876 | 271 | |
7fe1f91f | 272 | return sigma_force_open(sdi); |
3ba56876 | 273 | } |
274 | ||
275 | static int dev_close(struct sr_dev_inst *sdi) | |
276 | { | |
277 | struct dev_context *devc; | |
278 | ||
279 | devc = sdi->priv; | |
280 | ||
7fe1f91f | 281 | return sigma_force_close(devc); |
3ba56876 | 282 | } |
283 | ||
dd7a72ea UH |
284 | static int config_get(uint32_t key, GVariant **data, |
285 | const struct sr_dev_inst *sdi, const struct sr_channel_group *cg) | |
3ba56876 | 286 | { |
287 | struct dev_context *devc; | |
2d8a5089 | 288 | const char *clock_text; |
3ba56876 | 289 | |
290 | (void)cg; | |
291 | ||
292 | if (!sdi) | |
293 | return SR_ERR; | |
294 | devc = sdi->priv; | |
295 | ||
296 | switch (key) { | |
53a939ab GS |
297 | case SR_CONF_CONN: |
298 | *data = g_variant_new_string(sdi->connection_id); | |
299 | break; | |
3ba56876 | 300 | case SR_CONF_SAMPLERATE: |
2d8a5089 GS |
301 | *data = g_variant_new_uint64(devc->clock.samplerate); |
302 | break; | |
303 | case SR_CONF_EXTERNAL_CLOCK: | |
304 | *data = g_variant_new_boolean(devc->clock.use_ext_clock); | |
305 | break; | |
306 | case SR_CONF_EXTERNAL_CLOCK_SOURCE: | |
307 | clock_text = channel_names[devc->clock.clock_pin]; | |
308 | *data = g_variant_new_string(clock_text); | |
309 | break; | |
310 | case SR_CONF_CLOCK_EDGE: | |
311 | clock_text = ext_clock_edges[devc->clock.clock_edge]; | |
312 | *data = g_variant_new_string(clock_text); | |
3ba56876 | 313 | break; |
314 | case SR_CONF_LIMIT_MSEC: | |
2f7e529c | 315 | case SR_CONF_LIMIT_SAMPLES: |
156b6879 | 316 | return sr_sw_limits_config_get(&devc->limit.config, key, data); |
3ba56876 | 317 | case SR_CONF_CAPTURE_RATIO: |
318 | *data = g_variant_new_uint64(devc->capture_ratio); | |
319 | break; | |
320 | default: | |
321 | return SR_ERR_NA; | |
322 | } | |
323 | ||
324 | return SR_OK; | |
325 | } | |
326 | ||
dd7a72ea UH |
327 | static int config_set(uint32_t key, GVariant *data, |
328 | const struct sr_dev_inst *sdi, const struct sr_channel_group *cg) | |
3ba56876 | 329 | { |
330 | struct dev_context *devc; | |
5e78a564 GS |
331 | int ret; |
332 | uint64_t want_rate, have_rate; | |
2d8a5089 | 333 | int idx; |
3ba56876 | 334 | |
335 | (void)cg; | |
336 | ||
3ba56876 | 337 | devc = sdi->priv; |
338 | ||
3ba56876 | 339 | switch (key) { |
340 | case SR_CONF_SAMPLERATE: | |
5e78a564 GS |
341 | want_rate = g_variant_get_uint64(data); |
342 | ret = sigma_normalize_samplerate(want_rate, &have_rate); | |
343 | if (ret != SR_OK) | |
344 | return ret; | |
345 | if (have_rate != want_rate) { | |
346 | char *text_want, *text_have; | |
347 | text_want = sr_samplerate_string(want_rate); | |
348 | text_have = sr_samplerate_string(have_rate); | |
349 | sr_info("Adjusted samplerate %s to %s.", | |
350 | text_want, text_have); | |
351 | g_free(text_want); | |
352 | g_free(text_have); | |
353 | } | |
2d8a5089 GS |
354 | devc->clock.samplerate = have_rate; |
355 | break; | |
356 | case SR_CONF_EXTERNAL_CLOCK: | |
357 | devc->clock.use_ext_clock = g_variant_get_boolean(data); | |
358 | break; | |
359 | case SR_CONF_EXTERNAL_CLOCK_SOURCE: | |
360 | idx = std_str_idx(data, ARRAY_AND_SIZE(channel_names)); | |
361 | if (idx < 0) | |
362 | return SR_ERR_ARG; | |
363 | devc->clock.clock_pin = idx; | |
364 | break; | |
365 | case SR_CONF_CLOCK_EDGE: | |
366 | idx = std_str_idx(data, ARRAY_AND_SIZE(ext_clock_edges)); | |
367 | if (idx < 0) | |
368 | return SR_ERR_ARG; | |
369 | devc->clock.clock_edge = idx; | |
3ba56876 | 370 | break; |
5e78a564 | 371 | case SR_CONF_LIMIT_MSEC: |
3ba56876 | 372 | case SR_CONF_LIMIT_SAMPLES: |
156b6879 | 373 | return sr_sw_limits_config_set(&devc->limit.config, key, data); |
3ba56876 | 374 | case SR_CONF_CAPTURE_RATIO: |
efad7ccc | 375 | devc->capture_ratio = g_variant_get_uint64(data); |
3ba56876 | 376 | break; |
377 | default: | |
758906aa | 378 | return SR_ERR_NA; |
3ba56876 | 379 | } |
380 | ||
758906aa | 381 | return SR_OK; |
3ba56876 | 382 | } |
383 | ||
dd7a72ea UH |
384 | static int config_list(uint32_t key, GVariant **data, |
385 | const struct sr_dev_inst *sdi, const struct sr_channel_group *cg) | |
3ba56876 | 386 | { |
3ba56876 | 387 | switch (key) { |
53a939ab | 388 | case SR_CONF_SCAN_OPTIONS: |
3ba56876 | 389 | case SR_CONF_DEVICE_OPTIONS: |
53a939ab GS |
390 | if (cg) |
391 | return SR_ERR_NA; | |
9b4d261f GS |
392 | return STD_CONFIG_LIST(key, data, sdi, cg, |
393 | scanopts, drvopts, devopts); | |
3ba56876 | 394 | case SR_CONF_SAMPLERATE: |
abcd4771 | 395 | *data = sigma_get_samplerates_list(); |
3ba56876 | 396 | break; |
2d8a5089 GS |
397 | case SR_CONF_EXTERNAL_CLOCK_SOURCE: |
398 | *data = g_variant_new_strv(ARRAY_AND_SIZE(channel_names)); | |
399 | break; | |
400 | case SR_CONF_CLOCK_EDGE: | |
401 | *data = g_variant_new_strv(ARRAY_AND_SIZE(ext_clock_edges)); | |
402 | break; | |
3ba56876 | 403 | case SR_CONF_TRIGGER_MATCH: |
53012da6 | 404 | *data = std_gvar_array_i32(ARRAY_AND_SIZE(trigger_matches)); |
3ba56876 | 405 | break; |
406 | default: | |
407 | return SR_ERR_NA; | |
408 | } | |
409 | ||
410 | return SR_OK; | |
411 | } | |
412 | ||
695dc859 | 413 | static int dev_acquisition_start(const struct sr_dev_inst *sdi) |
3ba56876 | 414 | { |
415 | struct dev_context *devc; | |
419f1095 GS |
416 | uint16_t pindis_mask; |
417 | uint8_t async, div; | |
3d9373af GS |
418 | int ret; |
419 | size_t triggerpin; | |
419f1095 | 420 | uint8_t trigsel2; |
3ba56876 | 421 | struct triggerinout triggerinout_conf; |
422 | struct triggerlut lut; | |
3d9373af | 423 | uint8_t regval, cmd_bytes[4], *wrptr; |
3ba56876 | 424 | |
3ba56876 | 425 | devc = sdi->priv; |
426 | ||
f14e6f7e GS |
427 | /* Convert caller's trigger spec to driver's internal format. */ |
428 | ret = sigma_convert_trigger(sdi); | |
429 | if (ret != SR_OK) { | |
430 | sr_err("Could not configure triggers."); | |
431 | return ret; | |
432 | } | |
433 | ||
5e78a564 GS |
434 | /* |
435 | * Setup the device's samplerate from the value which up to now | |
436 | * just got checked and stored. As a byproduct this can pick and | |
437 | * send firmware to the device, reduce the number of available | |
438 | * logic channels, etc. | |
439 | * | |
440 | * Determine an acquisition timeout from optionally configured | |
441 | * sample count or time limits. Which depends on the samplerate. | |
2d8a5089 | 442 | * Force 50MHz samplerate when external clock is in use. |
5e78a564 | 443 | */ |
2d8a5089 GS |
444 | if (devc->clock.use_ext_clock) { |
445 | if (devc->clock.samplerate != SR_MHZ(50)) | |
446 | sr_info("External clock, forcing 50MHz samplerate."); | |
447 | devc->clock.samplerate = SR_MHZ(50); | |
448 | } | |
5e78a564 GS |
449 | ret = sigma_set_samplerate(sdi); |
450 | if (ret != SR_OK) | |
451 | return ret; | |
452 | ret = sigma_set_acquire_timeout(devc); | |
453 | if (ret != SR_OK) | |
454 | return ret; | |
455 | ||
3ba56876 | 456 | /* Enter trigger programming mode. */ |
0f017b7d GS |
457 | trigsel2 = TRGSEL2_RESET; |
458 | ret = sigma_set_register(devc, WRITE_TRIGGER_SELECT2, trigsel2); | |
88a5f9ea GS |
459 | if (ret != SR_OK) |
460 | return ret; | |
3ba56876 | 461 | |
419f1095 | 462 | trigsel2 = 0; |
2d8a5089 | 463 | if (devc->clock.samplerate >= SR_MHZ(100)) { |
f06fb3e9 | 464 | /* 100 and 200 MHz mode. */ |
419f1095 | 465 | /* TODO Decipher the 0x81 magic number's purpose. */ |
88a5f9ea GS |
466 | ret = sigma_set_register(devc, WRITE_TRIGGER_SELECT2, 0x81); |
467 | if (ret != SR_OK) | |
468 | return ret; | |
3ba56876 | 469 | |
470 | /* Find which pin to trigger on from mask. */ | |
9b4d261f | 471 | for (triggerpin = 0; triggerpin < 8; triggerpin++) { |
3f5f5484 | 472 | if (devc->trigger.risingmask & BIT(triggerpin)) |
9b4d261f | 473 | break; |
3f5f5484 | 474 | if (devc->trigger.fallingmask & BIT(triggerpin)) |
3ba56876 | 475 | break; |
9b4d261f | 476 | } |
3ba56876 | 477 | |
478 | /* Set trigger pin and light LED on trigger. */ | |
419f1095 GS |
479 | trigsel2 = triggerpin & TRGSEL2_PINS_MASK; |
480 | trigsel2 |= TRGSEL2_LEDSEL1; | |
3ba56876 | 481 | |
482 | /* Default rising edge. */ | |
419f1095 | 483 | /* TODO Documentation disagrees, bit set means _rising_ edge. */ |
3ba56876 | 484 | if (devc->trigger.fallingmask) |
419f1095 | 485 | trigsel2 |= TRGSEL2_PINPOL_RISE; |
3ba56876 | 486 | |
2d8a5089 | 487 | } else if (devc->clock.samplerate <= SR_MHZ(50)) { |
419f1095 GS |
488 | /* 50MHz firmware modes. */ |
489 | ||
490 | /* Translate application specs to hardware perspective. */ | |
88a5f9ea GS |
491 | ret = sigma_build_basic_trigger(devc, &lut); |
492 | if (ret != SR_OK) | |
493 | return ret; | |
3ba56876 | 494 | |
419f1095 | 495 | /* Communicate resulting register values to the device. */ |
88a5f9ea GS |
496 | ret = sigma_write_trigger_lut(devc, &lut); |
497 | if (ret != SR_OK) | |
498 | return ret; | |
3ba56876 | 499 | |
419f1095 | 500 | trigsel2 = TRGSEL2_LEDSEL1 | TRGSEL2_LEDSEL0; |
3ba56876 | 501 | } |
502 | ||
503 | /* Setup trigger in and out pins to default values. */ | |
5c231fc4 | 504 | memset(&triggerinout_conf, 0, sizeof(triggerinout_conf)); |
3d9373af GS |
505 | triggerinout_conf.trgout_bytrigger = TRUE; |
506 | triggerinout_conf.trgout_enable = TRUE; | |
a53b8e4d GS |
507 | /* TODO |
508 | * Verify the correctness of this implementation. The previous | |
509 | * version used to assign to a C language struct with bit fields | |
510 | * which is highly non-portable and hard to guess the resulting | |
511 | * raw memory layout or wire transfer content. The C struct's | |
512 | * field names did not match the vendor documentation's names. | |
513 | * Which means that I could not verify "on paper" either. Let's | |
514 | * re-visit this code later during research for trigger support. | |
515 | */ | |
3d9373af | 516 | wrptr = cmd_bytes; |
a53b8e4d GS |
517 | regval = 0; |
518 | if (triggerinout_conf.trgout_bytrigger) | |
519 | regval |= TRGOPT_TRGOOUTEN; | |
520 | write_u8_inc(&wrptr, regval); | |
521 | regval &= ~TRGOPT_CLEAR_MASK; | |
522 | if (triggerinout_conf.trgout_enable) | |
523 | regval |= TRGOPT_TRGOEN; | |
524 | write_u8_inc(&wrptr, regval); | |
88a5f9ea | 525 | ret = sigma_write_register(devc, WRITE_TRIGGER_OPTION, |
3d9373af | 526 | cmd_bytes, wrptr - cmd_bytes); |
88a5f9ea GS |
527 | if (ret != SR_OK) |
528 | return ret; | |
a53b8e4d GS |
529 | |
530 | /* Leave trigger programming mode. */ | |
419f1095 | 531 | ret = sigma_set_register(devc, WRITE_TRIGGER_SELECT2, trigsel2); |
88a5f9ea GS |
532 | if (ret != SR_OK) |
533 | return ret; | |
3ba56876 | 534 | |
419f1095 GS |
535 | /* |
536 | * Samplerate dependent clock and channels configuration. Some | |
537 | * channels by design are not available at higher clock rates. | |
538 | * Register layout differs between firmware variants (depth 1 | |
539 | * with LSB channel mask above 50MHz, depth 4 with more details | |
540 | * up to 50MHz). | |
541 | * | |
542 | * Derive a mask where bits are set for unavailable channels. | |
543 | * Either send the single byte, or the full byte sequence. | |
544 | */ | |
de4c29fa | 545 | pindis_mask = ~BITS_MASK(devc->interp.num_channels); |
2d8a5089 | 546 | if (devc->clock.samplerate > SR_MHZ(50)) { |
419f1095 GS |
547 | ret = sigma_set_register(devc, WRITE_CLOCK_SELECT, |
548 | pindis_mask & 0xff); | |
8256ed15 | 549 | } else { |
3d9373af | 550 | wrptr = cmd_bytes; |
419f1095 GS |
551 | /* Select 50MHz base clock, and divider. */ |
552 | async = 0; | |
2d8a5089 GS |
553 | div = SR_MHZ(50) / devc->clock.samplerate - 1; |
554 | if (devc->clock.use_ext_clock) { | |
555 | async = CLKSEL_CLKSEL8; | |
556 | div = devc->clock.clock_pin + 1; | |
557 | switch (devc->clock.clock_edge) { | |
558 | case SIGMA_CLOCK_EDGE_RISING: | |
559 | div |= CLKSEL_RISING; | |
560 | break; | |
561 | case SIGMA_CLOCK_EDGE_FALLING: | |
562 | div |= CLKSEL_FALLING; | |
563 | break; | |
564 | case SIGMA_CLOCK_EDGE_EITHER: | |
565 | div |= CLKSEL_RISING; | |
566 | div |= CLKSEL_FALLING; | |
567 | break; | |
568 | } | |
569 | } | |
419f1095 GS |
570 | write_u8_inc(&wrptr, async); |
571 | write_u8_inc(&wrptr, div); | |
572 | write_u16be_inc(&wrptr, pindis_mask); | |
573 | ret = sigma_write_register(devc, WRITE_CLOCK_SELECT, | |
3d9373af | 574 | cmd_bytes, wrptr - cmd_bytes); |
3ba56876 | 575 | } |
88a5f9ea GS |
576 | if (ret != SR_OK) |
577 | return ret; | |
3ba56876 | 578 | |
579 | /* Setup maximum post trigger time. */ | |
88a5f9ea | 580 | ret = sigma_set_register(devc, WRITE_POST_TRIGGER, |
9b4d261f | 581 | (devc->capture_ratio * 255) / 100); |
88a5f9ea GS |
582 | if (ret != SR_OK) |
583 | return ret; | |
3ba56876 | 584 | |
585 | /* Start acqusition. */ | |
9b4d261f | 586 | regval = WMR_TRGRES | WMR_SDRAMWRITEEN; |
e0926713 | 587 | if (devc->use_triggers) |
fb65ca09 | 588 | regval |= WMR_TRGEN; |
88a5f9ea GS |
589 | ret = sigma_set_register(devc, WRITE_MODE, regval); |
590 | if (ret != SR_OK) | |
591 | return ret; | |
3ba56876 | 592 | |
88a5f9ea GS |
593 | ret = std_session_send_df_header(sdi); |
594 | if (ret != SR_OK) | |
595 | return ret; | |
3ba56876 | 596 | |
597 | /* Add capture source. */ | |
88a5f9ea | 598 | ret = sr_session_source_add(sdi->session, -1, 0, 10, |
9b4d261f | 599 | sigma_receive_data, (void *)sdi); |
88a5f9ea GS |
600 | if (ret != SR_OK) |
601 | return ret; | |
3ba56876 | 602 | |
de4c29fa | 603 | devc->state = SIGMA_CAPTURE; |
3ba56876 | 604 | |
605 | return SR_OK; | |
606 | } | |
607 | ||
695dc859 | 608 | static int dev_acquisition_stop(struct sr_dev_inst *sdi) |
3ba56876 | 609 | { |
610 | struct dev_context *devc; | |
611 | ||
3ba56876 | 612 | devc = sdi->priv; |
3ba56876 | 613 | |
dde0175d GS |
614 | /* |
615 | * When acquisition is currently running, keep the receive | |
616 | * routine registered and have it stop the acquisition upon the | |
617 | * next invocation. Else unregister the receive routine here | |
618 | * already. The detour is required to have sample data retrieved | |
619 | * for forced acquisition stops. | |
620 | */ | |
de4c29fa GS |
621 | if (devc->state == SIGMA_CAPTURE) { |
622 | devc->state = SIGMA_STOPPING; | |
dde0175d | 623 | } else { |
de4c29fa | 624 | devc->state = SIGMA_IDLE; |
88a5f9ea | 625 | (void)sr_session_source_remove(sdi->session, -1); |
dde0175d | 626 | } |
3ba56876 | 627 | |
628 | return SR_OK; | |
629 | } | |
630 | ||
dd5c48a6 | 631 | static struct sr_dev_driver asix_sigma_driver_info = { |
3ba56876 | 632 | .name = "asix-sigma", |
633 | .longname = "ASIX SIGMA/SIGMA2", | |
634 | .api_version = 1, | |
c2fdcc25 | 635 | .init = std_init, |
700d6b64 | 636 | .cleanup = std_cleanup, |
3ba56876 | 637 | .scan = scan, |
c01bf34c | 638 | .dev_list = std_dev_list, |
3ba56876 | 639 | .dev_clear = dev_clear, |
640 | .config_get = config_get, | |
641 | .config_set = config_set, | |
642 | .config_list = config_list, | |
643 | .dev_open = dev_open, | |
644 | .dev_close = dev_close, | |
645 | .dev_acquisition_start = dev_acquisition_start, | |
646 | .dev_acquisition_stop = dev_acquisition_stop, | |
647 | .context = NULL, | |
648 | }; | |
dd5c48a6 | 649 | SR_REGISTER_DEV_DRIVER(asix_sigma_driver_info); |