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8a05fd71 JL |
1 | ------------------------------------------------------------------------------- |
2 | Microchip ENC28J60 | |
3 | ------------------------------------------------------------------------------- | |
4 | ||
5 | This is an example capture of the Microchip ENC28J60 SPI Ethernet chip. | |
6 | ||
7 | Details: | |
8 | http://ww1.microchip.com/downloads/en/DeviceDoc/39662e.pdf | |
9 | ||
10 | ||
11 | enc28j60-init-and-ping.sr | |
12 | ------------------------- | |
13 | ||
14 | Capture contains the following 3 stages: | |
15 | ||
16 | 1) Initialization phase where control registers are written. | |
17 | 2) Polling phase that waits for the Ethernet link to be up. | |
18 | 3) Two round-trips of ping packets (each consists of 1 RX of ICMP Echo Request | |
19 | packet and 1 TX of ICMP Echo Reply packet). | |
20 | ||
21 | The chip was driven by a custom STM32F446 board running custom bare-metal | |
22 | firmware. | |
23 | ||
24 | ||
25 | Logic analyzer setup | |
26 | -------------------- | |
27 | ||
28 | The logic analyzer used was a DSLogic Plus (at 50MHz, with SPI clock at 16MHz): | |
29 | ||
30 | Probe ENC28J60 | |
31 | -------------------- | |
32 | 0 CS# | |
33 | 1 MISO | |
34 | 2 CLK | |
35 | 3 MOSI |