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Commit | Line | Data |
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f711de81 UH |
1 | ------------------------------------------------------------------------------- |
2 | Analog clock signal | |
3 | ------------------------------------------------------------------------------- | |
4 | ||
5 | This is a set of example captures of a clock signal (rectangle signal) | |
6 | generated using a function generator, sampled using an LA/MSO. | |
7 | ||
8 | ||
9 | Logic analyzer setup | |
10 | -------------------- | |
11 | ||
12 | The logic analyzer used was a Noname LHT00SU1 (at 12MHz): | |
13 | ||
14 | Probe Signal | |
15 | ------------------------------- | |
16 | 1DCH 100kHz clock signal | |
17 | 2DCH same 100kHz clock signal | |
18 | 1ACH same 100kHz clock signal | |
19 |